Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	82570	1			T2	268		T4	169		T5	586
accum_cnt_1000	209186	1			T2	218		T4	939		T5	873
accum_cnt_100	21818	1			T2	32		T4	38		T5	51
accum_cnt_50	54871	1			T2	57		T3	10		T4	41
accum_cnt_10	177828	1			T2	57		T3	39		T4	875
accum_cnt_0	417824	1			T1	28		T2	3146		T3	23

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	252698	1			T1	7		T2	1074		T3	18
class_index[0x1]	252698	1			T1	7		T2	1074		T3	18
class_index[0x2]	252698	1			T1	7		T2	1074		T3	18
class_index[0x3]	252698	1			T1	7		T2	1074		T3	18

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	22134	1			T2	268		T6	210		T20	306
class_index[0x0]	accum_cnt_1000	57578	1			T2	218		T6	349		T19	27
class_index[0x0]	accum_cnt_100	5682	1			T2	13		T6	27		T19	20
class_index[0x0]	accum_cnt_50	18088	1			T2	14		T6	27		T19	13
class_index[0x0]	accum_cnt_10	52685	1			T2	43		T3	9		T4	858
class_index[0x0]	accum_cnt_0	82024	1			T1	7		T3	9		T4	5
class_index[0x1]	accum_cnt_2000	21112	1			T4	158		T5	277		T20	396
class_index[0x1]	accum_cnt_1000	48399	1			T4	169		T5	451		T6	144
class_index[0x1]	accum_cnt_100	4592	1			T2	7		T4	6		T5	25
class_index[0x1]	accum_cnt_50	9442	1			T2	24		T3	6		T4	12
class_index[0x1]	accum_cnt_10	41467	1			T2	6		T3	10		T4	2
class_index[0x1]	accum_cnt_0	116995	1			T1	7		T2	1037		T3	2
class_index[0x2]	accum_cnt_2000	21118	1			T24	561		T21	48		T274	379
class_index[0x2]	accum_cnt_1000	53566	1			T6	14		T31	27		T24	491
class_index[0x2]	accum_cnt_100	5877	1			T2	12		T6	77		T31	1
class_index[0x2]	accum_cnt_50	15361	1			T2	19		T6	73		T31	1
class_index[0x2]	accum_cnt_10	39661	1			T2	8		T3	10		T5	2
class_index[0x2]	accum_cnt_0	108213	1			T1	7		T2	1035		T3	8
class_index[0x3]	accum_cnt_2000	18206	1			T4	11		T5	309		T37	539
class_index[0x3]	accum_cnt_1000	49643	1			T4	770		T5	422		T6	129
class_index[0x3]	accum_cnt_100	5667	1			T4	32		T5	26		T6	26
class_index[0x3]	accum_cnt_50	11980	1			T3	4		T4	29		T5	22
class_index[0x3]	accum_cnt_10	44015	1			T3	10		T4	15		T5	7
class_index[0x3]	accum_cnt_0	110592	1			T1	7		T2	1074		T3	4