Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	6733	1			T38	1		T98	3		T58	1
alert[0x1]	4895	1			T2	23		T38	1		T39	1
alert[0x2]	15295	1			T4	1100		T38	1		T59	4
alert[0x3]	6591	1			T4	184		T23	76		T132	135
alert[0x4]	10666	1			T4	14		T21	13		T23	72
alert[0x5]	5763	1			T4	481		T72	49		T21	1
alert[0x6]	5879	1			T2	44		T4	1704		T39	1
alert[0x7]	7407	1			T18	1		T76	1006		T43	13
alert[0x8]	3897	1			T4	112		T21	2		T78	44
alert[0x9]	6780	1			T2	53		T4	91		T119	4
alert[0xa]	10160	1			T98	7		T58	5		T59	59
alert[0xb]	8596	1			T18	1		T23	73		T117	49
alert[0xc]	4528	1			T2	10		T38	1		T39	1
alert[0xd]	3768	1			T23	665		T22	247		T17	5
alert[0xe]	6643	1			T2	238		T38	1		T59	42
alert[0xf]	10027	1			T18	1		T119	6		T22	58
alert[0x10]	10668	1			T39	1		T23	72		T22	29
alert[0x11]	12817	1			T58	9		T22	22		T132	706
alert[0x12]	5148	1			T4	24		T38	1		T23	47
alert[0x13]	11336	1			T78	715		T22	903		T117	4
alert[0x14]	6928	1			T2	52		T24	1		T72	4
alert[0x15]	8210	1			T31	1		T98	1		T59	492
alert[0x16]	5980	1			T2	6		T4	45		T23	15
alert[0x17]	9060	1			T4	18		T18	1		T24	17
alert[0x18]	6954	1			T17	1		T117	56		T43	262
alert[0x19]	5110	1			T2	1854		T18	1		T24	18
alert[0x1a]	10020	1			T2	82		T18	1		T21	4
alert[0x1b]	4992	1			T58	35		T302	1		T85	52
alert[0x1c]	5200	1			T4	141		T18	1		T117	13
alert[0x1d]	5187	1			T4	3		T78	194		T23	17
alert[0x1e]	5750	1			T2	11		T4	18		T38	1
alert[0x1f]	6562	1			T38	1		T39	1		T21	7
alert[0x20]	2713	1			T24	8		T58	11		T22	275
alert[0x21]	7302	1			T39	1		T78	379		T98	32
alert[0x22]	4903	1			T21	11		T98	2		T59	7
alert[0x23]	5078	1			T17	1		T59	6		T117	29
alert[0x24]	9460	1			T4	379		T39	1		T21	6
alert[0x25]	4225	1			T4	4		T98	2		T59	15
alert[0x26]	9681	1			T4	59		T23	74		T22	954
alert[0x27]	9368	1			T2	5		T38	1		T18	1
alert[0x28]	7029	1			T4	291		T18	1		T23	868
alert[0x29]	4193	1			T2	81		T38	1		T22	10
alert[0x2a]	10974	1			T40	1		T24	4		T78	4774
alert[0x2b]	4657	1			T2	9		T38	1		T23	76
alert[0x2c]	3953	1			T24	1		T23	50		T132	68
alert[0x2d]	6394	1			T18	2		T23	31		T58	1
alert[0x2e]	9795	1			T4	91		T23	40		T59	1
alert[0x2f]	16549	1			T21	5		T98	1		T23	316
alert[0x30]	9571	1			T2	6		T4	148		T59	117
alert[0x31]	5519	1			T39	1		T98	8		T23	17
alert[0x32]	10797	1			T4	227		T24	10		T78	77
alert[0x33]	7598	1			T2	119		T4	107		T38	3
alert[0x34]	3425	1			T72	1		T98	6		T23	39
alert[0x35]	7292	1			T2	100		T4	149		T38	1
alert[0x36]	7871	1			T21	20		T23	57		T119	5
alert[0x37]	8269	1			T38	1		T24	2		T23	73
alert[0x38]	14020	1			T2	20		T4	11		T78	93
alert[0x39]	4034	1			T39	1		T23	6		T59	52
alert[0x3a]	7867	1			T2	133		T132	37		T28	35
alert[0x3b]	8705	1			T4	94		T59	2		T302	1
alert[0x3c]	9021	1			T98	24		T23	27		T59	90
alert[0x3d]	3600	1			T39	1		T22	231		T132	11
alert[0x3e]	3022	1			T4	62		T39	1		T117	3
alert[0x3f]	3280	1			T2	58		T38	1		T78	21
alert[0x40]	3561	1			T18	1		T23	123		T22	1078

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	108489	1			T2	2904		T18	12		T21	16
class_i[0x1]	142203	1			T4	5557		T24	18		T72	53
class_i[0x2]	83780	1			T38	17		T72	1		T39	1
class_i[0x3]	136804	1			T40	1		T31	1		T24	43

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

470612

1

T2

2904

T4

5557

T31

1

alert_ping_fail

664

1

T38

17

T18

12

T40

1

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	6725	1			T98	3		T58	1		T117	6
alert_integrity_fail	alert[0x1]	4882	1			T2	23		T58	1		T17	1
alert_integrity_fail	alert[0x2]	15284	1			T4	1100		T59	4		T303	29
alert_integrity_fail	alert[0x3]	6582	1			T4	184		T23	76		T132	135
alert_integrity_fail	alert[0x4]	10659	1			T4	14		T21	13		T23	72
alert_integrity_fail	alert[0x5]	5750	1			T4	481		T72	49		T21	1
alert_integrity_fail	alert[0x6]	5869	1			T2	44		T4	1704		T22	294
alert_integrity_fail	alert[0x7]	7391	1			T76	1006		T43	13		T303	280
alert_integrity_fail	alert[0x8]	3884	1			T4	112		T21	2		T78	44
alert_integrity_fail	alert[0x9]	6771	1			T2	53		T4	91		T119	4
alert_integrity_fail	alert[0xa]	10144	1			T98	7		T58	5		T59	59
alert_integrity_fail	alert[0xb]	8582	1			T23	73		T117	49		T28	17
alert_integrity_fail	alert[0xc]	4515	1			T2	10		T78	30		T23	50
alert_integrity_fail	alert[0xd]	3756	1			T23	665		T22	247		T17	5
alert_integrity_fail	alert[0xe]	6633	1			T2	238		T59	42		T117	7
alert_integrity_fail	alert[0xf]	10023	1			T119	6		T22	58		T117	29
alert_integrity_fail	alert[0x10]	10659	1			T23	72		T22	29		T117	671
alert_integrity_fail	alert[0x11]	12812	1			T58	9		T22	22		T132	706
alert_integrity_fail	alert[0x12]	5132	1			T4	24		T23	47		T119	1
alert_integrity_fail	alert[0x13]	11333	1			T78	715		T22	903		T117	4
alert_integrity_fail	alert[0x14]	6917	1			T2	52		T24	1		T72	4
alert_integrity_fail	alert[0x15]	8196	1			T31	1		T98	1		T59	492
alert_integrity_fail	alert[0x16]	5968	1			T2	6		T4	45		T23	15
alert_integrity_fail	alert[0x17]	9043	1			T4	18		T24	17		T78	480
alert_integrity_fail	alert[0x18]	6946	1			T17	1		T117	56		T43	262
alert_integrity_fail	alert[0x19]	5101	1			T2	1854		T24	18		T23	81
alert_integrity_fail	alert[0x1a]	10007	1			T2	82		T21	4		T23	222
alert_integrity_fail	alert[0x1b]	4982	1			T58	35		T85	52		T43	371
alert_integrity_fail	alert[0x1c]	5194	1			T4	141		T117	13		T132	255
alert_integrity_fail	alert[0x1d]	5178	1			T4	3		T78	194		T23	17
alert_integrity_fail	alert[0x1e]	5740	1			T2	11		T4	18		T78	32
alert_integrity_fail	alert[0x1f]	6550	1			T21	7		T23	886		T17	51
alert_integrity_fail	alert[0x20]	2707	1			T24	8		T58	11		T22	275
alert_integrity_fail	alert[0x21]	7290	1			T78	379		T98	32		T119	1
alert_integrity_fail	alert[0x22]	4883	1			T21	11		T98	2		T59	7
alert_integrity_fail	alert[0x23]	5072	1			T17	1		T59	6		T117	29
alert_integrity_fail	alert[0x24]	9452	1			T4	379		T21	6		T23	84
alert_integrity_fail	alert[0x25]	4215	1			T4	4		T98	2		T59	15
alert_integrity_fail	alert[0x26]	9675	1			T4	59		T23	74		T22	954
alert_integrity_fail	alert[0x27]	9353	1			T2	5		T59	373		T132	23
alert_integrity_fail	alert[0x28]	7016	1			T4	291		T23	868		T17	1
alert_integrity_fail	alert[0x29]	4182	1			T2	81		T22	10		T59	734
alert_integrity_fail	alert[0x2a]	10959	1			T24	4		T78	4774		T22	171
alert_integrity_fail	alert[0x2b]	4653	1			T2	9		T23	76		T22	376
alert_integrity_fail	alert[0x2c]	3933	1			T24	1		T23	50		T132	68
alert_integrity_fail	alert[0x2d]	6387	1			T23	31		T58	1		T22	39
alert_integrity_fail	alert[0x2e]	9786	1			T4	91		T23	40		T59	1
alert_integrity_fail	alert[0x2f]	16544	1			T21	5		T98	1		T23	316
alert_integrity_fail	alert[0x30]	9562	1			T2	6		T4	148		T59	117
alert_integrity_fail	alert[0x31]	5509	1			T98	8		T23	17		T22	1
alert_integrity_fail	alert[0x32]	10790	1			T4	227		T24	10		T78	77
alert_integrity_fail	alert[0x33]	7583	1			T2	119		T4	107		T22	73
alert_integrity_fail	alert[0x34]	3420	1			T72	1		T98	6		T23	39
alert_integrity_fail	alert[0x35]	7283	1			T2	100		T4	149		T23	22
alert_integrity_fail	alert[0x36]	7863	1			T21	20		T23	57		T119	5
alert_integrity_fail	alert[0x37]	8258	1			T24	2		T23	73		T119	7
alert_integrity_fail	alert[0x38]	14009	1			T2	20		T4	11		T78	93
alert_integrity_fail	alert[0x39]	4026	1			T23	6		T59	52		T132	186
alert_integrity_fail	alert[0x3a]	7857	1			T2	133		T132	37		T28	35
alert_integrity_fail	alert[0x3b]	8694	1			T4	94		T59	2		T85	68
alert_integrity_fail	alert[0x3c]	9012	1			T98	24		T23	27		T59	90
alert_integrity_fail	alert[0x3d]	3591	1			T22	231		T132	11		T42	1
alert_integrity_fail	alert[0x3e]	3010	1			T4	62		T117	3		T132	63
alert_integrity_fail	alert[0x3f]	3273	1			T2	58		T78	21		T23	91
alert_integrity_fail	alert[0x40]	3557	1			T23	123		T22	1078		T117	30
alert_ping_fail	alert[0x0]	8	1			T38	1		T302	1		T304	1
alert_ping_fail	alert[0x1]	13	1			T38	1		T39	1		T304	1
alert_ping_fail	alert[0x2]	11	1			T38	1		T305	1		T306	1
alert_ping_fail	alert[0x3]	9	1			T237	1		T307	1		T308	1
alert_ping_fail	alert[0x4]	7	1			T309	1		T307	1		T234	1
alert_ping_fail	alert[0x5]	13	1			T310	1		T306	1		T301	1
alert_ping_fail	alert[0x6]	10	1			T39	1		T311	1		T312	1
alert_ping_fail	alert[0x7]	16	1			T18	1		T313	1		T314	1
alert_ping_fail	alert[0x8]	13	1			T309	1		T315	1		T234	3
alert_ping_fail	alert[0x9]	9	1			T304	1		T316	1		T306	1
alert_ping_fail	alert[0xa]	16	1			T302	1		T305	1		T316	1
alert_ping_fail	alert[0xb]	14	1			T18	1		T302	1		T317	1
alert_ping_fail	alert[0xc]	13	1			T38	1		T39	1		T304	1
alert_ping_fail	alert[0xd]	12	1			T302	3		T305	1		T309	1
alert_ping_fail	alert[0xe]	10	1			T38	1		T316	1		T311	1
alert_ping_fail	alert[0xf]	4	1			T18	1		T318	1		T319	1
alert_ping_fail	alert[0x10]	9	1			T39	1		T302	2		T306	1
alert_ping_fail	alert[0x11]	5	1			T314	1		T320	2		T321	1
alert_ping_fail	alert[0x12]	16	1			T38	1		T302	1		T309	1
alert_ping_fail	alert[0x13]	3	1			T322	1		T323	1		T324	1
alert_ping_fail	alert[0x14]	11	1			T39	1		T302	1		T237	1
alert_ping_fail	alert[0x15]	14	1			T305	2		T306	1		T314	1
alert_ping_fail	alert[0x16]	12	1			T311	1		T237	1		T234	1
alert_ping_fail	alert[0x17]	17	1			T18	1		T302	1		T304	1
alert_ping_fail	alert[0x18]	8	1			T316	1		T306	1		T308	2
alert_ping_fail	alert[0x19]	9	1			T18	1		T304	1		T316	1
alert_ping_fail	alert[0x1a]	13	1			T18	1		T302	2		T313	2
alert_ping_fail	alert[0x1b]	10	1			T302	1		T312	1		T325	1
alert_ping_fail	alert[0x1c]	6	1			T18	1		T26	1		T317	1
alert_ping_fail	alert[0x1d]	9	1			T305	1		T311	1		T231	1
alert_ping_fail	alert[0x1e]	10	1			T38	1		T39	1		T317	2
alert_ping_fail	alert[0x1f]	12	1			T38	1		T39	1		T302	1
alert_ping_fail	alert[0x20]	6	1			T307	1		T312	1		T234	1
alert_ping_fail	alert[0x21]	12	1			T39	1		T306	1		T326	2
alert_ping_fail	alert[0x22]	20	1			T304	1		T317	1		T298	4
alert_ping_fail	alert[0x23]	6	1			T309	1		T312	1		T327	1
alert_ping_fail	alert[0x24]	8	1			T39	1		T304	1		T306	1
alert_ping_fail	alert[0x25]	10	1			T305	1		T316	1		T237	1
alert_ping_fail	alert[0x26]	6	1			T305	1		T107	1		T320	1
alert_ping_fail	alert[0x27]	15	1			T38	1		T18	1		T39	1
alert_ping_fail	alert[0x28]	13	1			T18	1		T301	1		T314	1
alert_ping_fail	alert[0x29]	11	1			T38	1		T307	1		T308	2
alert_ping_fail	alert[0x2a]	15	1			T40	1		T302	1		T306	1
alert_ping_fail	alert[0x2b]	4	1			T38	1		T317	1		T328	1
alert_ping_fail	alert[0x2c]	20	1			T302	1		T317	1		T298	1
alert_ping_fail	alert[0x2d]	7	1			T18	2		T313	1		T314	1
alert_ping_fail	alert[0x2e]	9	1			T307	1		T312	1		T329	1
alert_ping_fail	alert[0x2f]	5	1			T317	1		T330	1		T331	1
alert_ping_fail	alert[0x30]	9	1			T305	1		T307	1		T66	2
alert_ping_fail	alert[0x31]	10	1			T39	1		T305	1		T314	2
alert_ping_fail	alert[0x32]	7	1			T307	1		T312	1		T107	1
alert_ping_fail	alert[0x33]	15	1			T38	3		T39	1		T317	1
alert_ping_fail	alert[0x34]	5	1			T313	1		T332	1		T331	1
alert_ping_fail	alert[0x35]	9	1			T38	1		T316	1		T306	1
alert_ping_fail	alert[0x36]	8	1			T304	1		T313	1		T234	1
alert_ping_fail	alert[0x37]	11	1			T38	1		T311	1		T329	1
alert_ping_fail	alert[0x38]	11	1			T317	1		T306	1		T314	1
alert_ping_fail	alert[0x39]	8	1			T39	1		T304	1		T316	1
alert_ping_fail	alert[0x3a]	10	1			T329	1		T320	1		T333	2
alert_ping_fail	alert[0x3b]	11	1			T302	1		T305	1		T317	1
alert_ping_fail	alert[0x3c]	9	1			T237	1		T307	1		T107	1
alert_ping_fail	alert[0x3d]	9	1			T39	1		T302	1		T325	1
alert_ping_fail	alert[0x3e]	12	1			T39	1		T317	1		T309	1
alert_ping_fail	alert[0x3f]	7	1			T38	1		T305	1		T309	1
alert_ping_fail	alert[0x40]	4	1			T18	1		T307	1		T308	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	108340	1			T2	2904		T21	16		T22	10788
alert_integrity_fail	class_i[0x1]	142007	1			T4	5557		T24	18		T72	53
alert_integrity_fail	class_i[0x2]	83655	1			T72	1		T21	25		T23	1
alert_integrity_fail	class_i[0x3]	136610	1			T31	1		T24	43		T21	13
alert_ping_fail	class_i[0x0]	149	1			T18	12		T317	12		T310	1
alert_ping_fail	class_i[0x1]	196	1			T39	13		T304	10		T26	1
alert_ping_fail	class_i[0x2]	125	1			T38	17		T39	1		T304	1
alert_ping_fail	class_i[0x3]	194	1			T40	1		T39	1		T302	19