Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.64 99.99 98.72 99.97 100.00 100.00 99.38 99.40


Total test records in report: 804
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T769 /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.2222011969 Feb 18 01:39:54 PM PST 24 Feb 18 01:44:20 PM PST 24 4085011152 ps
T169 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.131336093 Feb 18 01:39:58 PM PST 24 Feb 18 01:43:09 PM PST 24 1911778125 ps
T770 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.3194722241 Feb 18 01:40:13 PM PST 24 Feb 18 01:40:48 PM PST 24 11823893 ps
T771 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.4125378438 Feb 18 01:39:44 PM PST 24 Feb 18 01:40:35 PM PST 24 439255395 ps
T772 /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.533402313 Feb 18 01:40:45 PM PST 24 Feb 18 01:41:07 PM PST 24 13021041 ps
T181 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.180709897 Feb 18 01:40:29 PM PST 24 Feb 18 01:41:01 PM PST 24 114538853 ps
T152 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3361506017 Feb 18 01:39:39 PM PST 24 Feb 18 01:41:41 PM PST 24 842812202 ps
T773 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.3147965390 Feb 18 01:40:08 PM PST 24 Feb 18 01:40:46 PM PST 24 8450761 ps
T164 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2418854376 Feb 18 01:40:23 PM PST 24 Feb 18 01:46:39 PM PST 24 2374940139 ps
T774 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.801232992 Feb 18 01:40:33 PM PST 24 Feb 18 01:41:14 PM PST 24 101630960 ps
T775 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.346458579 Feb 18 01:40:04 PM PST 24 Feb 18 01:40:43 PM PST 24 9921581 ps
T776 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2857841765 Feb 18 01:40:40 PM PST 24 Feb 18 01:41:03 PM PST 24 14361973 ps
T777 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.831995876 Feb 18 01:40:24 PM PST 24 Feb 18 01:40:59 PM PST 24 41223280 ps
T778 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.123276354 Feb 18 01:39:42 PM PST 24 Feb 18 01:46:41 PM PST 24 81438484104 ps
T779 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3525703363 Feb 18 01:40:24 PM PST 24 Feb 18 01:40:55 PM PST 24 7749643 ps
T191 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.2190918430 Feb 18 01:39:23 PM PST 24 Feb 18 01:40:15 PM PST 24 38914607 ps
T165 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.844837113 Feb 18 01:39:23 PM PST 24 Feb 18 01:45:12 PM PST 24 9657364146 ps
T780 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1516203693 Feb 18 01:40:23 PM PST 24 Feb 18 01:41:03 PM PST 24 127161736 ps
T170 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2592804454 Feb 18 01:40:16 PM PST 24 Feb 18 01:45:56 PM PST 24 4075543702 ps
T781 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.3399940435 Feb 18 01:39:41 PM PST 24 Feb 18 01:40:42 PM PST 24 1515056371 ps
T782 /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.3909106682 Feb 18 01:40:41 PM PST 24 Feb 18 01:41:07 PM PST 24 49418173 ps
T158 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.4199657317 Feb 18 01:40:29 PM PST 24 Feb 18 01:43:14 PM PST 24 2042853246 ps
T783 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1147309359 Feb 18 01:40:25 PM PST 24 Feb 18 01:40:56 PM PST 24 10113852 ps
T784 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.316078177 Feb 18 01:40:14 PM PST 24 Feb 18 01:40:54 PM PST 24 130560412 ps
T785 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2726210588 Feb 18 01:40:23 PM PST 24 Feb 18 01:40:58 PM PST 24 48429882 ps
T786 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.3921833673 Feb 18 01:40:41 PM PST 24 Feb 18 01:41:04 PM PST 24 7395037 ps
T171 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3685708140 Feb 18 01:40:17 PM PST 24 Feb 18 01:46:01 PM PST 24 10158128413 ps
T187 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.764173512 Feb 18 01:39:45 PM PST 24 Feb 18 01:42:03 PM PST 24 2388328936 ps
T168 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2175131635 Feb 18 01:40:36 PM PST 24 Feb 18 01:46:08 PM PST 24 4612867887 ps
T787 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.1353798793 Feb 18 01:40:44 PM PST 24 Feb 18 01:41:06 PM PST 24 10858384 ps
T788 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3386593054 Feb 18 01:40:23 PM PST 24 Feb 18 01:41:12 PM PST 24 127455548 ps
T161 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.845840039 Feb 18 01:40:24 PM PST 24 Feb 18 01:46:51 PM PST 24 34664418473 ps
T789 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2704204665 Feb 18 01:39:44 PM PST 24 Feb 18 01:41:03 PM PST 24 489775009 ps
T790 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.1127428785 Feb 18 01:39:59 PM PST 24 Feb 18 01:40:57 PM PST 24 321525706 ps
T358 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1537977820 Feb 18 01:39:44 PM PST 24 Feb 18 01:48:36 PM PST 24 25532517765 ps
T791 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.2964145221 Feb 18 01:40:00 PM PST 24 Feb 18 01:40:43 PM PST 24 68252305 ps
T792 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3363535503 Feb 18 01:40:35 PM PST 24 Feb 18 01:41:29 PM PST 24 1061541680 ps
T184 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.387998488 Feb 18 01:40:38 PM PST 24 Feb 18 01:41:04 PM PST 24 108034778 ps
T167 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.903357726 Feb 18 01:40:00 PM PST 24 Feb 18 01:58:16 PM PST 24 29368415417 ps
T793 /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.3732413521 Feb 18 01:40:45 PM PST 24 Feb 18 01:41:07 PM PST 24 7786816 ps
T794 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3768655671 Feb 18 01:39:30 PM PST 24 Feb 18 01:41:04 PM PST 24 1388532818 ps
T172 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1745156353 Feb 18 01:39:38 PM PST 24 Feb 18 01:43:07 PM PST 24 4684599563 ps
T186 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2882365704 Feb 18 01:40:23 PM PST 24 Feb 18 01:40:56 PM PST 24 145093075 ps
T795 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2539929633 Feb 18 01:40:25 PM PST 24 Feb 18 01:41:07 PM PST 24 94903296 ps
T796 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2667221057 Feb 18 01:39:51 PM PST 24 Feb 18 01:45:23 PM PST 24 17615879020 ps
T797 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2843540351 Feb 18 01:39:49 PM PST 24 Feb 18 01:40:36 PM PST 24 199343169 ps
T798 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1723981113 Feb 18 01:40:00 PM PST 24 Feb 18 01:41:24 PM PST 24 517298951 ps
T799 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2609569535 Feb 18 01:39:38 PM PST 24 Feb 18 01:40:28 PM PST 24 10081285 ps
T800 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3998594390 Feb 18 01:39:32 PM PST 24 Feb 18 01:47:53 PM PST 24 8925844231 ps
T801 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.4163109358 Feb 18 01:40:39 PM PST 24 Feb 18 01:41:50 PM PST 24 697137420 ps
T802 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.2720370248 Feb 18 01:40:18 PM PST 24 Feb 18 01:40:53 PM PST 24 12546050 ps
T803 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.4121805755 Feb 18 01:40:18 PM PST 24 Feb 18 01:41:05 PM PST 24 83967403 ps
T359 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.691424661 Feb 18 01:40:38 PM PST 24 Feb 18 01:50:33 PM PST 24 60476103743 ps
T804 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3703956997 Feb 18 01:39:59 PM PST 24 Feb 18 01:40:43 PM PST 24 438350920 ps

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.1654393567
Short name T6
Test name
Test status
Simulation time 25569077598 ps
CPU time 2586.69 seconds
Started Feb 18 12:39:20 PM PST 24
Finished Feb 18 01:22:30 PM PST 24
Peak memory 297776 kb
Host smart-572b31f5-4de9-4bfb-b745-30ccef46f88e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654393567 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.1654393567
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.1487031925
Short name T11
Test name
Test status
Simulation time 542432930 ps
CPU time 25.94 seconds
Started Feb 18 12:38:33 PM PST 24
Finished Feb 18 12:39:01 PM PST 24
Peak memory 276936 kb
Host smart-d6c4f423-a9e8-4ba1-820a-dc4f2b4e7a95
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1487031925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.1487031925
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.3637132054
Short name T21
Test name
Test status
Simulation time 84769707372 ps
CPU time 1842.18 seconds
Started Feb 18 12:39:49 PM PST 24
Finished Feb 18 01:10:34 PM PST 24
Peak memory 272416 kb
Host smart-81933815-78d1-40b0-bdc7-843fd474aed1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637132054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.3637132054
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3837834699
Short name T245
Test name
Test status
Simulation time 472109265 ps
CPU time 10.31 seconds
Started Feb 18 01:39:40 PM PST 24
Finished Feb 18 01:40:32 PM PST 24
Peak memory 236564 kb
Host smart-37135ef9-61d3-4a2c-ba4e-a739ddaef735
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3837834699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.3837834699
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.2605411554
Short name T23
Test name
Test status
Simulation time 251967217114 ps
CPU time 3686.66 seconds
Started Feb 18 12:38:45 PM PST 24
Finished Feb 18 01:40:16 PM PST 24
Peak memory 288592 kb
Host smart-bac9bdd0-9814-4fc3-827e-1ca8b29b2344
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605411554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.2605411554
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.4132640358
Short name T106
Test name
Test status
Simulation time 58284421566 ps
CPU time 5407.3 seconds
Started Feb 18 12:39:34 PM PST 24
Finished Feb 18 02:09:45 PM PST 24
Peak memory 337320 kb
Host smart-5110df3a-cdc4-41f0-9334-ef302b942920
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132640358 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.4132640358
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.2897194977
Short name T25
Test name
Test status
Simulation time 61323436244 ps
CPU time 1557.18 seconds
Started Feb 18 12:40:00 PM PST 24
Finished Feb 18 01:05:59 PM PST 24
Peak memory 288392 kb
Host smart-b5318cac-6efa-4bb3-8f29-dbae35d6486f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897194977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.2897194977
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2980890745
Short name T145
Test name
Test status
Simulation time 8496914522 ps
CPU time 679.28 seconds
Started Feb 18 01:40:00 PM PST 24
Finished Feb 18 01:52:00 PM PST 24
Peak memory 265424 kb
Host smart-4de77667-6e3b-4456-9ed0-9fa4d4f8e29a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980890745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.2980890745
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.1969862008
Short name T40
Test name
Test status
Simulation time 288286907442 ps
CPU time 1198.73 seconds
Started Feb 18 12:38:59 PM PST 24
Finished Feb 18 12:59:01 PM PST 24
Peak memory 281172 kb
Host smart-f0020f86-1f3c-4a8f-b4fd-61ef2a4aecb5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969862008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.1969862008
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.824544430
Short name T76
Test name
Test status
Simulation time 44104294119 ps
CPU time 2394.12 seconds
Started Feb 18 12:39:17 PM PST 24
Finished Feb 18 01:19:15 PM PST 24
Peak memory 282380 kb
Host smart-abf6ede5-f497-4160-b45d-1ef48c326090
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824544430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.824544430
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.255566057
Short name T137
Test name
Test status
Simulation time 12618839202 ps
CPU time 1158.27 seconds
Started Feb 18 01:39:39 PM PST 24
Finished Feb 18 01:59:39 PM PST 24
Peak memory 265340 kb
Host smart-22168824-403f-4d2a-baeb-9245fcd97c48
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255566057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.255566057
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.945123172
Short name T2
Test name
Test status
Simulation time 27376203147 ps
CPU time 1135.13 seconds
Started Feb 18 12:38:27 PM PST 24
Finished Feb 18 12:57:25 PM PST 24
Peak memory 289260 kb
Host smart-52932900-dd88-4dac-9d4e-0af52398aa9a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945123172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_hand
ler_stress_all.945123172
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.2083302104
Short name T343
Test name
Test status
Simulation time 177424443447 ps
CPU time 2679.75 seconds
Started Feb 18 12:39:17 PM PST 24
Finished Feb 18 01:24:01 PM PST 24
Peak memory 283968 kb
Host smart-a5e0cbf8-b295-47a2-8bd8-3b37dda660b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083302104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.2083302104
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1852060476
Short name T139
Test name
Test status
Simulation time 26066480317 ps
CPU time 1084.01 seconds
Started Feb 18 01:40:31 PM PST 24
Finished Feb 18 01:59:02 PM PST 24
Peak memory 273372 kb
Host smart-9d0eb17a-4cea-4186-aa03-6b787cd2ce5f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852060476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1852060476
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.3364666850
Short name T47
Test name
Test status
Simulation time 51963027698 ps
CPU time 2879.47 seconds
Started Feb 18 12:39:42 PM PST 24
Finished Feb 18 01:27:44 PM PST 24
Peak memory 288616 kb
Host smart-a1a960ac-e482-46cc-b9d5-ec2f386ff561
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364666850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.3364666850
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.3468309061
Short name T262
Test name
Test status
Simulation time 36125154566 ps
CPU time 2145.02 seconds
Started Feb 18 12:39:29 PM PST 24
Finished Feb 18 01:15:17 PM PST 24
Peak memory 281044 kb
Host smart-1f08b6f5-857f-47ae-af3f-f3753f5e074c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468309061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.3468309061
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3795805211
Short name T143
Test name
Test status
Simulation time 1565376493 ps
CPU time 191.24 seconds
Started Feb 18 01:39:56 PM PST 24
Finished Feb 18 01:43:47 PM PST 24
Peak memory 265332 kb
Host smart-003d7e2b-7731-4d3a-aa18-92b47c2eddcc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3795805211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.3795805211
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2318745062
Short name T174
Test name
Test status
Simulation time 1824389458 ps
CPU time 43.32 seconds
Started Feb 18 01:40:37 PM PST 24
Finished Feb 18 01:41:44 PM PST 24
Peak memory 239356 kb
Host smart-bd446c44-9c9b-4648-82b7-cb46fe74de8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2318745062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2318745062
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.2607951899
Short name T301
Test name
Test status
Simulation time 158737301908 ps
CPU time 2183.4 seconds
Started Feb 18 12:39:29 PM PST 24
Finished Feb 18 01:15:55 PM PST 24
Peak memory 286148 kb
Host smart-40f66205-fc23-404c-8092-cefc8f522200
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607951899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.2607951899
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.845840039
Short name T161
Test name
Test status
Simulation time 34664418473 ps
CPU time 357.98 seconds
Started Feb 18 01:40:24 PM PST 24
Finished Feb 18 01:46:51 PM PST 24
Peak memory 272240 kb
Host smart-30432a6f-f340-4f34-b1ca-1b6a4c83568e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=845840039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_erro
rs.845840039
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3087066179
Short name T353
Test name
Test status
Simulation time 9855274 ps
CPU time 1.39 seconds
Started Feb 18 01:40:44 PM PST 24
Finished Feb 18 01:41:06 PM PST 24
Peak memory 235796 kb
Host smart-ba9d2bd5-2322-49d0-9ed0-b6d7ee913a59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3087066179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3087066179
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.3250527644
Short name T39
Test name
Test status
Simulation time 84629911808 ps
CPU time 508.25 seconds
Started Feb 18 12:38:54 PM PST 24
Finished Feb 18 12:47:25 PM PST 24
Peak memory 247260 kb
Host smart-31e46279-17d0-428e-8529-f6c2614f13a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250527644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.3250527644
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.1162741982
Short name T22
Test name
Test status
Simulation time 31215798283 ps
CPU time 1833.19 seconds
Started Feb 18 12:38:37 PM PST 24
Finished Feb 18 01:09:12 PM PST 24
Peak memory 272964 kb
Host smart-3c3cabdd-d448-415b-a328-b05789d67065
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162741982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.1162741982
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2175131635
Short name T168
Test name
Test status
Simulation time 4612867887 ps
CPU time 308.23 seconds
Started Feb 18 01:40:36 PM PST 24
Finished Feb 18 01:46:08 PM PST 24
Peak memory 266308 kb
Host smart-54249654-e346-46d4-a1fe-55e3e52510f3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2175131635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.2175131635
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.207995939
Short name T231
Test name
Test status
Simulation time 151085841167 ps
CPU time 2293.22 seconds
Started Feb 18 12:39:15 PM PST 24
Finished Feb 18 01:17:34 PM PST 24
Peak memory 287204 kb
Host smart-533ba3f8-af79-4527-b590-b2504b4d7deb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207995939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.207995939
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.3429073014
Short name T307
Test name
Test status
Simulation time 11949657047 ps
CPU time 467.15 seconds
Started Feb 18 12:39:43 PM PST 24
Finished Feb 18 12:47:32 PM PST 24
Peak memory 247052 kb
Host smart-68353557-fb1e-4212-b2f8-906fc0d9c840
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429073014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.3429073014
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.368102334
Short name T59
Test name
Test status
Simulation time 764346660647 ps
CPU time 7174.46 seconds
Started Feb 18 12:39:10 PM PST 24
Finished Feb 18 02:38:53 PM PST 24
Peak memory 354008 kb
Host smart-64ec8bed-5600-4d1e-9185-33f4552902f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368102334 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.368102334
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.840028023
Short name T166
Test name
Test status
Simulation time 6527502631 ps
CPU time 220.9 seconds
Started Feb 18 01:40:25 PM PST 24
Finished Feb 18 01:44:36 PM PST 24
Peak memory 265344 kb
Host smart-7e536f7b-5b53-448e-89d3-7d74ff6a1ad4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=840028023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_erro
rs.840028023
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.1039371782
Short name T45
Test name
Test status
Simulation time 14147620022 ps
CPU time 1226.13 seconds
Started Feb 18 12:39:18 PM PST 24
Finished Feb 18 12:59:48 PM PST 24
Peak memory 288492 kb
Host smart-d9b2f055-b3db-4e5c-b808-3760342cc25d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039371782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.1039371782
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1906412065
Short name T153
Test name
Test status
Simulation time 16169038951 ps
CPU time 665.4 seconds
Started Feb 18 01:40:13 PM PST 24
Finished Feb 18 01:51:53 PM PST 24
Peak memory 265420 kb
Host smart-bbe1c175-919a-49aa-8956-e97a676841d4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906412065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.1906412065
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.1768851356
Short name T329
Test name
Test status
Simulation time 9690980171 ps
CPU time 381.99 seconds
Started Feb 18 12:39:06 PM PST 24
Finished Feb 18 12:45:36 PM PST 24
Peak memory 247272 kb
Host smart-83f9d142-0025-4171-b1e5-7d2bb43dc73d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768851356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.1768851356
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.2722573990
Short name T340
Test name
Test status
Simulation time 35456442117 ps
CPU time 2313.31 seconds
Started Feb 18 12:39:23 PM PST 24
Finished Feb 18 01:18:00 PM PST 24
Peak memory 281152 kb
Host smart-35bbf759-53e6-46c1-abbc-09062790f129
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722573990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.2722573990
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.3233154035
Short name T31
Test name
Test status
Simulation time 742533650 ps
CPU time 47.48 seconds
Started Feb 18 12:39:12 PM PST 24
Finished Feb 18 12:40:06 PM PST 24
Peak memory 255784 kb
Host smart-b8a30c80-a9df-44cf-8b5a-bb6da6aeff3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32331
54035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.3233154035
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.1673701161
Short name T323
Test name
Test status
Simulation time 50120417268 ps
CPU time 3044.95 seconds
Started Feb 18 12:39:59 PM PST 24
Finished Feb 18 01:30:46 PM PST 24
Peak memory 288380 kb
Host smart-d341c23b-b2d1-43b2-b5c9-028f60997398
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673701161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.1673701161
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.863601639
Short name T17
Test name
Test status
Simulation time 350826607 ps
CPU time 24.9 seconds
Started Feb 18 12:38:47 PM PST 24
Finished Feb 18 12:39:15 PM PST 24
Peak memory 248320 kb
Host smart-ada5cdcd-a77b-4bba-bca9-5e457279571a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86360
1639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.863601639
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.713092363
Short name T354
Test name
Test status
Simulation time 15581922 ps
CPU time 1.81 seconds
Started Feb 18 01:40:46 PM PST 24
Finished Feb 18 01:41:08 PM PST 24
Peak memory 236604 kb
Host smart-b7a1f8d1-fc2c-40d8-8d02-22b2e3c1d0af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=713092363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.713092363
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.2518361488
Short name T18
Test name
Test status
Simulation time 13546172493 ps
CPU time 308.65 seconds
Started Feb 18 12:39:18 PM PST 24
Finished Feb 18 12:44:30 PM PST 24
Peak memory 246044 kb
Host smart-fcb507d9-d34b-447f-947c-105c94fc1683
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518361488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.2518361488
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.2342152087
Short name T138
Test name
Test status
Simulation time 33789536543 ps
CPU time 1192.4 seconds
Started Feb 18 01:39:56 PM PST 24
Finished Feb 18 02:00:31 PM PST 24
Peak memory 265420 kb
Host smart-e3f4d3f7-a977-4ab1-96e4-ef321b7e3f9b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342152087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.2342152087
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.2244532677
Short name T103
Test name
Test status
Simulation time 14718870099 ps
CPU time 1307.49 seconds
Started Feb 18 12:39:11 PM PST 24
Finished Feb 18 01:01:06 PM PST 24
Peak memory 289236 kb
Host smart-9a741e5e-ef2c-488a-97da-42ba8be9206e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244532677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.2244532677
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.1414033039
Short name T53
Test name
Test status
Simulation time 187509526454 ps
CPU time 2623.78 seconds
Started Feb 18 12:39:44 PM PST 24
Finished Feb 18 01:23:30 PM PST 24
Peak memory 288824 kb
Host smart-b335f73c-7ec4-447b-9b77-6e7d7bf38231
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414033039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.1414033039
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.1207132194
Short name T259
Test name
Test status
Simulation time 4074946697 ps
CPU time 44.34 seconds
Started Feb 18 12:38:17 PM PST 24
Finished Feb 18 12:39:07 PM PST 24
Peak memory 246964 kb
Host smart-6270ba33-0382-4587-83bb-abb04344c840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12071
32194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.1207132194
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.938055038
Short name T309
Test name
Test status
Simulation time 9890691431 ps
CPU time 390.46 seconds
Started Feb 18 12:39:44 PM PST 24
Finished Feb 18 12:46:16 PM PST 24
Peak memory 246188 kb
Host smart-12a01e90-b9f2-4ead-afce-38ed6f9154b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938055038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.938055038
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2128934504
Short name T163
Test name
Test status
Simulation time 17915276319 ps
CPU time 562.84 seconds
Started Feb 18 01:40:09 PM PST 24
Finished Feb 18 01:50:07 PM PST 24
Peak memory 265280 kb
Host smart-3ebc352e-b44d-4ea9-9440-3a9ec42d83c1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128934504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.2128934504
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2418854376
Short name T164
Test name
Test status
Simulation time 2374940139 ps
CPU time 345.86 seconds
Started Feb 18 01:40:23 PM PST 24
Finished Feb 18 01:46:39 PM PST 24
Peak memory 265392 kb
Host smart-4bdbd394-7615-4e1f-a308-9bc97a7cb9fa
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418854376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.2418854376
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.2985325000
Short name T96
Test name
Test status
Simulation time 2232063789 ps
CPU time 36.89 seconds
Started Feb 18 12:38:19 PM PST 24
Finished Feb 18 12:39:04 PM PST 24
Peak memory 240200 kb
Host smart-cde66202-71cd-4e28-8b43-5c22f69ca5b6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2985325000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.2985325000
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.1740255018
Short name T613
Test name
Test status
Simulation time 79404382436 ps
CPU time 2003.8 seconds
Started Feb 18 12:38:33 PM PST 24
Finished Feb 18 01:11:59 PM PST 24
Peak memory 288780 kb
Host smart-30767709-ac86-464a-bd81-6aa3f385ebe2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740255018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.1740255018
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.2997528132
Short name T671
Test name
Test status
Simulation time 22577525813 ps
CPU time 334 seconds
Started Feb 18 12:39:20 PM PST 24
Finished Feb 18 12:44:57 PM PST 24
Peak memory 247368 kb
Host smart-e200fed9-e2bc-4656-baa8-bbb310370bc0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997528132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.2997528132
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.180709897
Short name T181
Test name
Test status
Simulation time 114538853 ps
CPU time 4.64 seconds
Started Feb 18 01:40:29 PM PST 24
Finished Feb 18 01:41:01 PM PST 24
Peak memory 236876 kb
Host smart-4518270b-437f-421d-8089-8517d246e8ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=180709897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.180709897
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2592804454
Short name T170
Test name
Test status
Simulation time 4075543702 ps
CPU time 305.25 seconds
Started Feb 18 01:40:16 PM PST 24
Finished Feb 18 01:45:56 PM PST 24
Peak memory 265340 kb
Host smart-0bd6984b-2e94-40d9-a80e-98ecccf6d7d0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2592804454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.2592804454
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.3824273416
Short name T199
Test name
Test status
Simulation time 31126314 ps
CPU time 3.33 seconds
Started Feb 18 12:39:11 PM PST 24
Finished Feb 18 12:39:21 PM PST 24
Peak memory 248520 kb
Host smart-82945f31-557d-4a97-ae8f-4f39e25f3fbd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3824273416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.3824273416
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.4146079391
Short name T226
Test name
Test status
Simulation time 40299440 ps
CPU time 2.34 seconds
Started Feb 18 12:38:15 PM PST 24
Finished Feb 18 12:38:23 PM PST 24
Peak memory 248548 kb
Host smart-0d402549-7505-4b1a-b492-6ed06f23131c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4146079391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.4146079391
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.395197264
Short name T225
Test name
Test status
Simulation time 41635524 ps
CPU time 3.43 seconds
Started Feb 18 12:38:21 PM PST 24
Finished Feb 18 12:38:32 PM PST 24
Peak memory 248644 kb
Host smart-45a66a50-c4cd-49e5-b6e2-5ae2ff74a7da
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=395197264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.395197264
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.1962656463
Short name T213
Test name
Test status
Simulation time 164434930 ps
CPU time 3.7 seconds
Started Feb 18 12:38:50 PM PST 24
Finished Feb 18 12:38:57 PM PST 24
Peak memory 248528 kb
Host smart-226107da-18d7-485c-b833-fa8c41b0db1b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1962656463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.1962656463
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.3606791800
Short name T299
Test name
Test status
Simulation time 23768887781 ps
CPU time 1286.42 seconds
Started Feb 18 12:38:45 PM PST 24
Finished Feb 18 01:00:16 PM PST 24
Peak memory 285688 kb
Host smart-58d60ead-5ec3-4d44-8e62-cd199c637ca7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606791800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.3606791800
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.3882911897
Short name T293
Test name
Test status
Simulation time 1896266670 ps
CPU time 30.85 seconds
Started Feb 18 12:38:40 PM PST 24
Finished Feb 18 12:39:13 PM PST 24
Peak memory 254472 kb
Host smart-01a51efc-0ef4-4a56-a483-dc74e60f0a75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38829
11897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.3882911897
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.1546948977
Short name T107
Test name
Test status
Simulation time 11673221946 ps
CPU time 219.58 seconds
Started Feb 18 12:38:56 PM PST 24
Finished Feb 18 12:42:39 PM PST 24
Peak memory 247284 kb
Host smart-2b5a5429-4863-4652-bfb6-16726b5960c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546948977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.1546948977
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.3956979995
Short name T289
Test name
Test status
Simulation time 419335937 ps
CPU time 10.41 seconds
Started Feb 18 12:39:10 PM PST 24
Finished Feb 18 12:39:27 PM PST 24
Peak memory 252900 kb
Host smart-06217bef-9ee1-40fc-bd93-f27306cfedcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39569
79995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.3956979995
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.2746662236
Short name T278
Test name
Test status
Simulation time 158296683139 ps
CPU time 6604.18 seconds
Started Feb 18 12:39:05 PM PST 24
Finished Feb 18 02:29:16 PM PST 24
Peak memory 365176 kb
Host smart-b65fca38-88b3-40ae-911a-eb5339db9605
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746662236 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.2746662236
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.4067369786
Short name T290
Test name
Test status
Simulation time 743777104 ps
CPU time 46.3 seconds
Started Feb 18 12:39:11 PM PST 24
Finished Feb 18 12:40:05 PM PST 24
Peak memory 246728 kb
Host smart-97520e77-be27-43e7-92b7-53946c860e30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40673
69786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.4067369786
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.824993105
Short name T349
Test name
Test status
Simulation time 36943546333 ps
CPU time 890.51 seconds
Started Feb 18 12:40:50 PM PST 24
Finished Feb 18 12:55:42 PM PST 24
Peak memory 272524 kb
Host smart-7d0a7b47-2c96-4229-8756-a85af2ee6b47
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824993105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.824993105
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.4281900854
Short name T690
Test name
Test status
Simulation time 56250030718 ps
CPU time 3212.13 seconds
Started Feb 18 12:39:24 PM PST 24
Finished Feb 18 01:33:00 PM PST 24
Peak memory 289432 kb
Host smart-1d4b580e-f0fd-4b2a-b1fb-b70aca03ae40
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281900854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.4281900854
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.3619891122
Short name T256
Test name
Test status
Simulation time 33547679899 ps
CPU time 1857.09 seconds
Started Feb 18 12:39:31 PM PST 24
Finished Feb 18 01:10:31 PM PST 24
Peak memory 268848 kb
Host smart-bd7c27d2-e7cc-4296-99bc-5766f1e12f85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619891122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.3619891122
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.903357726
Short name T167
Test name
Test status
Simulation time 29368415417 ps
CPU time 1057.05 seconds
Started Feb 18 01:40:00 PM PST 24
Finished Feb 18 01:58:16 PM PST 24
Peak memory 265360 kb
Host smart-6cd722f5-b1cb-45be-9719-67dd92a5f3e3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903357726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.903357726
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.2632701100
Short name T19
Test name
Test status
Simulation time 6855967104 ps
CPU time 132.97 seconds
Started Feb 18 12:38:54 PM PST 24
Finished Feb 18 12:41:10 PM PST 24
Peak memory 255884 kb
Host smart-02719633-2ae3-40d4-9482-0d6c755b67cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26327
01100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.2632701100
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2882365704
Short name T186
Test name
Test status
Simulation time 145093075 ps
CPU time 2.73 seconds
Started Feb 18 01:40:23 PM PST 24
Finished Feb 18 01:40:56 PM PST 24
Peak memory 236448 kb
Host smart-e754f6fd-cc5f-4253-b8a3-a239323325c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2882365704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.2882365704
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1197015613
Short name T718
Test name
Test status
Simulation time 10976696 ps
CPU time 1.42 seconds
Started Feb 18 01:40:40 PM PST 24
Finished Feb 18 01:41:03 PM PST 24
Peak memory 235880 kb
Host smart-3d03405e-ae8e-4bf0-bdbe-7c9a2a77b76d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1197015613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1197015613
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.2608190693
Short name T351
Test name
Test status
Simulation time 80881865656 ps
CPU time 685.7 seconds
Started Feb 18 12:38:15 PM PST 24
Finished Feb 18 12:49:46 PM PST 24
Peak memory 264776 kb
Host smart-fbcb9cac-ddc6-4f4a-8f74-143d7f1b5447
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608190693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2608190693
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.1140777757
Short name T257
Test name
Test status
Simulation time 46515045913 ps
CPU time 865.19 seconds
Started Feb 18 12:38:37 PM PST 24
Finished Feb 18 12:53:04 PM PST 24
Peak memory 272968 kb
Host smart-856f8b9e-f375-425b-b9cf-518b968968bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140777757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.1140777757
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.2194401023
Short name T306
Test name
Test status
Simulation time 11969745315 ps
CPU time 473.26 seconds
Started Feb 18 12:38:47 PM PST 24
Finished Feb 18 12:46:44 PM PST 24
Peak memory 247284 kb
Host smart-8fe867d4-d21c-4d79-846f-f8884a2039a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194401023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.2194401023
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.2197272309
Short name T286
Test name
Test status
Simulation time 767354099 ps
CPU time 17.83 seconds
Started Feb 18 12:39:10 PM PST 24
Finished Feb 18 12:39:35 PM PST 24
Peak memory 253488 kb
Host smart-7a70dd16-9b33-40d9-aae8-c754c8b943e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21972
72309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.2197272309
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.1713657221
Short name T237
Test name
Test status
Simulation time 22462320008 ps
CPU time 251.49 seconds
Started Feb 18 12:39:07 PM PST 24
Finished Feb 18 12:43:26 PM PST 24
Peak memory 247248 kb
Host smart-d88324fd-d41f-45c7-9ab5-a968e15a7fe4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713657221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.1713657221
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.1890916288
Short name T280
Test name
Test status
Simulation time 92534230853 ps
CPU time 2844.94 seconds
Started Feb 18 12:39:03 PM PST 24
Finished Feb 18 01:26:31 PM PST 24
Peak memory 288848 kb
Host smart-6d6fee87-3b0f-4fcc-beca-c61b7792e9f2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890916288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.1890916288
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.3514377067
Short name T314
Test name
Test status
Simulation time 13687284938 ps
CPU time 488.44 seconds
Started Feb 18 12:39:05 PM PST 24
Finished Feb 18 12:47:19 PM PST 24
Peak memory 247284 kb
Host smart-341acc57-7efc-4c78-ad18-a91d9077f0b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514377067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.3514377067
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.1859839309
Short name T272
Test name
Test status
Simulation time 215610388 ps
CPU time 13.04 seconds
Started Feb 18 12:38:39 PM PST 24
Finished Feb 18 12:38:54 PM PST 24
Peak memory 248292 kb
Host smart-7cd6b1be-0431-46e9-b594-84f801db82d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18598
39309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.1859839309
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.3807693398
Short name T58
Test name
Test status
Simulation time 918400023 ps
CPU time 60.18 seconds
Started Feb 18 12:38:28 PM PST 24
Finished Feb 18 12:39:30 PM PST 24
Peak memory 255340 kb
Host smart-b8a9e58c-b65e-4409-a9b6-13ded07db818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38076
93398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.3807693398
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.2271417517
Short name T291
Test name
Test status
Simulation time 11413048325 ps
CPU time 59.38 seconds
Started Feb 18 12:39:23 PM PST 24
Finished Feb 18 12:40:26 PM PST 24
Peak memory 254676 kb
Host smart-4422e1d2-2ce4-491b-ba45-0d2b46dc7c99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22714
17517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.2271417517
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.3271634281
Short name T276
Test name
Test status
Simulation time 781052397 ps
CPU time 52.85 seconds
Started Feb 18 12:39:05 PM PST 24
Finished Feb 18 12:40:05 PM PST 24
Peak memory 254748 kb
Host smart-cebeb2a6-39c7-4afb-82c7-7865e4733df4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32716
34281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.3271634281
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.2144898902
Short name T277
Test name
Test status
Simulation time 11533682060 ps
CPU time 109.26 seconds
Started Feb 18 12:40:01 PM PST 24
Finished Feb 18 12:41:52 PM PST 24
Peak memory 256116 kb
Host smart-63603845-aeb8-43d5-a3f4-9fd2fd914227
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144898902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.2144898902
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.1255726860
Short name T279
Test name
Test status
Simulation time 60503887124 ps
CPU time 1915.6 seconds
Started Feb 18 12:38:53 PM PST 24
Finished Feb 18 01:10:51 PM PST 24
Peak memory 286576 kb
Host smart-fef4c4f2-e378-44d7-9c4f-aa944e94b109
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255726860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.1255726860
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.2467618164
Short name T154
Test name
Test status
Simulation time 24903859940 ps
CPU time 357.99 seconds
Started Feb 18 01:40:35 PM PST 24
Finished Feb 18 01:46:58 PM PST 24
Peak memory 272608 kb
Host smart-22a1242a-f333-428c-841c-fb314af871d2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2467618164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.2467618164
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.513371817
Short name T185
Test name
Test status
Simulation time 138424145 ps
CPU time 2.52 seconds
Started Feb 18 01:39:38 PM PST 24
Finished Feb 18 01:40:31 PM PST 24
Peak memory 236660 kb
Host smart-709e4b51-41ef-4789-b63c-d4f59feac792
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=513371817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.513371817
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3769089540
Short name T182
Test name
Test status
Simulation time 8109054470 ps
CPU time 73.98 seconds
Started Feb 18 01:39:58 PM PST 24
Finished Feb 18 01:41:51 PM PST 24
Peak memory 236796 kb
Host smart-d616480e-c471-45da-b2a5-73b9c53b8d20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3769089540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.3769089540
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1976970121
Short name T180
Test name
Test status
Simulation time 307117917 ps
CPU time 36.18 seconds
Started Feb 18 01:40:08 PM PST 24
Finished Feb 18 01:41:20 PM PST 24
Peak memory 240308 kb
Host smart-ecf40836-3d38-463d-9e12-8cac44bb6b82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1976970121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.1976970121
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.387998488
Short name T184
Test name
Test status
Simulation time 108034778 ps
CPU time 3.35 seconds
Started Feb 18 01:40:38 PM PST 24
Finished Feb 18 01:41:04 PM PST 24
Peak memory 236520 kb
Host smart-da1e191b-960d-4bd0-84bb-08b8d1bc3ae0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=387998488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.387998488
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.764173512
Short name T187
Test name
Test status
Simulation time 2388328936 ps
CPU time 90.11 seconds
Started Feb 18 01:39:45 PM PST 24
Finished Feb 18 01:42:03 PM PST 24
Peak memory 236740 kb
Host smart-d647ed9a-aa01-4561-8239-71ca26e37961
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=764173512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.764173512
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2795776999
Short name T173
Test name
Test status
Simulation time 109135572 ps
CPU time 3.74 seconds
Started Feb 18 01:39:51 PM PST 24
Finished Feb 18 01:40:34 PM PST 24
Peak memory 236804 kb
Host smart-50697704-0031-4c5b-8495-eb4806665c84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2795776999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.2795776999
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.1198971404
Short name T179
Test name
Test status
Simulation time 883082369 ps
CPU time 56.33 seconds
Started Feb 18 01:39:57 PM PST 24
Finished Feb 18 01:41:35 PM PST 24
Peak memory 239388 kb
Host smart-02812c6b-c1a8-4957-ac26-240ab7592b02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1198971404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.1198971404
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.4207397978
Short name T144
Test name
Test status
Simulation time 1171438391 ps
CPU time 129.49 seconds
Started Feb 18 01:40:10 PM PST 24
Finished Feb 18 01:42:55 PM PST 24
Peak memory 264624 kb
Host smart-35ac0c8a-4cb5-4964-828c-f568491ffc3b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4207397978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.4207397978
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3989528521
Short name T188
Test name
Test status
Simulation time 102458137 ps
CPU time 5.96 seconds
Started Feb 18 01:40:39 PM PST 24
Finished Feb 18 01:41:07 PM PST 24
Peak memory 237076 kb
Host smart-a47d6477-3b67-48b5-acc2-584ad02fb9e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3989528521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.3989528521
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.642742821
Short name T183
Test name
Test status
Simulation time 50562342 ps
CPU time 2.71 seconds
Started Feb 18 01:40:03 PM PST 24
Finished Feb 18 01:40:44 PM PST 24
Peak memory 236472 kb
Host smart-01799efe-8923-4536-873c-50fc31313dc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=642742821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.642742821
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.2190918430
Short name T191
Test name
Test status
Simulation time 38914607 ps
CPU time 3.64 seconds
Started Feb 18 01:39:23 PM PST 24
Finished Feb 18 01:40:15 PM PST 24
Peak memory 237540 kb
Host smart-4c10f21d-4f63-4044-9027-29a664f28215
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2190918430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.2190918430
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.2628492657
Short name T190
Test name
Test status
Simulation time 471520622 ps
CPU time 36.06 seconds
Started Feb 18 01:40:21 PM PST 24
Finished Feb 18 01:41:28 PM PST 24
Peak memory 239352 kb
Host smart-9fefd5ce-5d90-4371-9239-300ecdc69ff0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2628492657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.2628492657
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.869209714
Short name T196
Test name
Test status
Simulation time 1220297197 ps
CPU time 76.36 seconds
Started Feb 18 01:40:24 PM PST 24
Finished Feb 18 01:42:10 PM PST 24
Peak memory 240392 kb
Host smart-93119a80-f85c-4bea-b8de-49cc3a1a19e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=869209714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.869209714
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2494152093
Short name T195
Test name
Test status
Simulation time 88273585 ps
CPU time 5.21 seconds
Started Feb 18 01:40:45 PM PST 24
Finished Feb 18 01:41:11 PM PST 24
Peak memory 236512 kb
Host smart-0246dbbe-af37-4c37-8908-c71877fbaec2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2494152093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.2494152093
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.173250066
Short name T14
Test name
Test status
Simulation time 92883836972 ps
CPU time 1486.05 seconds
Started Feb 18 12:39:35 PM PST 24
Finished Feb 18 01:04:23 PM PST 24
Peak memory 271364 kb
Host smart-ab75f525-5f4a-4af9-9ba1-ec0789862340
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173250066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.173250066
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2186919731
Short name T250
Test name
Test status
Simulation time 4664709146 ps
CPU time 165.66 seconds
Started Feb 18 01:39:30 PM PST 24
Finished Feb 18 01:42:55 PM PST 24
Peak memory 236592 kb
Host smart-130adcc8-af68-4f2b-9d71-2d085c6ae9a5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2186919731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.2186919731
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3998594390
Short name T800
Test name
Test status
Simulation time 8925844231 ps
CPU time 461.48 seconds
Started Feb 18 01:39:32 PM PST 24
Finished Feb 18 01:47:53 PM PST 24
Peak memory 236608 kb
Host smart-65df22f3-326c-477b-b3ca-69b191a47b4e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3998594390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.3998594390
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1247942918
Short name T767
Test name
Test status
Simulation time 185066096 ps
CPU time 5.92 seconds
Started Feb 18 01:39:38 PM PST 24
Finished Feb 18 01:40:26 PM PST 24
Peak memory 240468 kb
Host smart-3132ac58-f1ff-42d7-8c6d-8b7928140a49
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1247942918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.1247942918
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.2695661079
Short name T766
Test name
Test status
Simulation time 541961210 ps
CPU time 5.27 seconds
Started Feb 18 01:39:30 PM PST 24
Finished Feb 18 01:40:16 PM PST 24
Peak memory 239404 kb
Host smart-c71ae362-ebaa-4a23-860c-2d3f054a2452
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2695661079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.2695661079
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.3811729715
Short name T752
Test name
Test status
Simulation time 30394984 ps
CPU time 1.4 seconds
Started Feb 18 01:39:24 PM PST 24
Finished Feb 18 01:40:03 PM PST 24
Peak memory 235720 kb
Host smart-8367b928-0168-49db-8b10-8ff57bdf8bf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3811729715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.3811729715
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3768655671
Short name T794
Test name
Test status
Simulation time 1388532818 ps
CPU time 48.36 seconds
Started Feb 18 01:39:30 PM PST 24
Finished Feb 18 01:41:04 PM PST 24
Peak memory 244724 kb
Host smart-57a19629-cb34-40c5-8aef-48d3f75580fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3768655671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.3768655671
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.844837113
Short name T165
Test name
Test status
Simulation time 9657364146 ps
CPU time 311.19 seconds
Started Feb 18 01:39:23 PM PST 24
Finished Feb 18 01:45:12 PM PST 24
Peak memory 271232 kb
Host smart-a3d9619e-60dd-43da-b66d-025747bc27bf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=844837113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_error
s.844837113
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.871743854
Short name T160
Test name
Test status
Simulation time 12179719923 ps
CPU time 984.06 seconds
Started Feb 18 01:39:22 PM PST 24
Finished Feb 18 01:56:25 PM PST 24
Peak memory 265332 kb
Host smart-27ed8037-e314-409e-99b1-71c97d6f54bf
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871743854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.871743854
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.2664924401
Short name T729
Test name
Test status
Simulation time 215612090 ps
CPU time 7.6 seconds
Started Feb 18 01:39:25 PM PST 24
Finished Feb 18 01:40:11 PM PST 24
Peak memory 251984 kb
Host smart-6b32fc22-386a-457d-b8e3-180a56aa8716
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2664924401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.2664924401
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3416459904
Short name T204
Test name
Test status
Simulation time 1212551085 ps
CPU time 160.4 seconds
Started Feb 18 01:39:38 PM PST 24
Finished Feb 18 01:43:00 PM PST 24
Peak memory 240416 kb
Host smart-25db15f9-6400-4926-9ab4-e66bb041de3f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3416459904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.3416459904
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2563233309
Short name T246
Test name
Test status
Simulation time 16124268250 ps
CPU time 224.11 seconds
Started Feb 18 01:39:39 PM PST 24
Finished Feb 18 01:44:11 PM PST 24
Peak memory 235696 kb
Host smart-85d74d90-23cf-456d-859a-4d9c22feeeda
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2563233309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.2563233309
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2390792993
Short name T755
Test name
Test status
Simulation time 196792931 ps
CPU time 3.34 seconds
Started Feb 18 01:39:39 PM PST 24
Finished Feb 18 01:40:24 PM PST 24
Peak memory 240452 kb
Host smart-bdb84d9f-4a20-45cf-b1e7-b2023b1e8a6b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2390792993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.2390792993
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2609569535
Short name T799
Test name
Test status
Simulation time 10081285 ps
CPU time 1.64 seconds
Started Feb 18 01:39:38 PM PST 24
Finished Feb 18 01:40:28 PM PST 24
Peak memory 235772 kb
Host smart-ca323fed-918c-4c7f-942e-0bbe877ef85d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2609569535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.2609569535
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.2351273492
Short name T725
Test name
Test status
Simulation time 255452198 ps
CPU time 17.63 seconds
Started Feb 18 01:39:39 PM PST 24
Finished Feb 18 01:40:37 PM PST 24
Peak memory 243848 kb
Host smart-dd7aa521-812c-4fd8-abaf-26a2611cf976
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2351273492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.2351273492
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3361506017
Short name T152
Test name
Test status
Simulation time 842812202 ps
CPU time 79.85 seconds
Started Feb 18 01:39:39 PM PST 24
Finished Feb 18 01:41:41 PM PST 24
Peak memory 256704 kb
Host smart-354d0c6a-bfec-4330-8f03-82a96d45d0d3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3361506017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.3361506017
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2827654058
Short name T135
Test name
Test status
Simulation time 108463565283 ps
CPU time 539.33 seconds
Started Feb 18 01:39:32 PM PST 24
Finished Feb 18 01:49:11 PM PST 24
Peak memory 265368 kb
Host smart-664aed3f-c769-44fe-bacd-6192b80f9ff0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827654058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.2827654058
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.93276825
Short name T733
Test name
Test status
Simulation time 50727269 ps
CPU time 6.86 seconds
Started Feb 18 01:39:54 PM PST 24
Finished Feb 18 01:40:43 PM PST 24
Peak memory 252248 kb
Host smart-58eb41df-9410-42bf-8242-fda96370441c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=93276825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.93276825
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.3302022125
Short name T706
Test name
Test status
Simulation time 131971038 ps
CPU time 15.41 seconds
Started Feb 18 01:40:18 PM PST 24
Finished Feb 18 01:41:07 PM PST 24
Peak memory 256308 kb
Host smart-24b67956-0e15-41bd-a029-732a3c39ba99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302022125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.3302022125
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1755748029
Short name T206
Test name
Test status
Simulation time 184136385 ps
CPU time 7.83 seconds
Started Feb 18 01:40:13 PM PST 24
Finished Feb 18 01:40:55 PM PST 24
Peak memory 240464 kb
Host smart-a50c68fd-6db7-4721-847c-349746027b95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1755748029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1755748029
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.4208300785
Short name T711
Test name
Test status
Simulation time 41447663 ps
CPU time 1.37 seconds
Started Feb 18 01:40:41 PM PST 24
Finished Feb 18 01:41:04 PM PST 24
Peak memory 236440 kb
Host smart-ed635c86-4ed4-4f12-9dd4-34b6a605d35f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4208300785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.4208300785
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.1054488450
Short name T708
Test name
Test status
Simulation time 763307030 ps
CPU time 26.57 seconds
Started Feb 18 01:40:12 PM PST 24
Finished Feb 18 01:41:13 PM PST 24
Peak memory 244728 kb
Host smart-2066b894-c6c2-4355-aec4-da516321dc0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1054488450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.1054488450
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3508086606
Short name T150
Test name
Test status
Simulation time 11533957091 ps
CPU time 412.2 seconds
Started Feb 18 01:40:13 PM PST 24
Finished Feb 18 01:47:40 PM PST 24
Peak memory 265224 kb
Host smart-9f3a19ee-ee94-4926-98f0-4c6e3ef245b2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508086606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.3508086606
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.577320019
Short name T712
Test name
Test status
Simulation time 270331778 ps
CPU time 10.4 seconds
Started Feb 18 01:40:14 PM PST 24
Finished Feb 18 01:40:59 PM PST 24
Peak memory 252828 kb
Host smart-6eeaec72-7c09-431d-aee8-7358d335cbd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=577320019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.577320019
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.298167489
Short name T295
Test name
Test status
Simulation time 940113440 ps
CPU time 65.21 seconds
Started Feb 18 01:40:12 PM PST 24
Finished Feb 18 01:41:51 PM PST 24
Peak memory 245216 kb
Host smart-25b1511f-69f7-41ca-baff-5230d828f896
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=298167489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.298167489
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.831995876
Short name T777
Test name
Test status
Simulation time 41223280 ps
CPU time 5.8 seconds
Started Feb 18 01:40:24 PM PST 24
Finished Feb 18 01:40:59 PM PST 24
Peak memory 240456 kb
Host smart-df09288a-dc75-42f0-9713-0c77d48f24c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=831995876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.831995876
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.3194722241
Short name T770
Test name
Test status
Simulation time 11823893 ps
CPU time 1.58 seconds
Started Feb 18 01:40:13 PM PST 24
Finished Feb 18 01:40:48 PM PST 24
Peak memory 235828 kb
Host smart-4af7c566-f77e-4660-afe9-f86af9c495d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3194722241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.3194722241
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.4121805755
Short name T803
Test name
Test status
Simulation time 83967403 ps
CPU time 13.59 seconds
Started Feb 18 01:40:18 PM PST 24
Finished Feb 18 01:41:05 PM PST 24
Peak memory 244704 kb
Host smart-25245c4a-de9a-4101-8831-07c873025058
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4121805755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.4121805755
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3425780720
Short name T162
Test name
Test status
Simulation time 807354006 ps
CPU time 90.3 seconds
Started Feb 18 01:40:10 PM PST 24
Finished Feb 18 01:42:15 PM PST 24
Peak memory 257088 kb
Host smart-b673d8bc-d3e2-484b-bcda-35eb448ff79e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3425780720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.3425780720
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2865760645
Short name T736
Test name
Test status
Simulation time 206824236 ps
CPU time 12.85 seconds
Started Feb 18 01:40:13 PM PST 24
Finished Feb 18 01:41:00 PM PST 24
Peak memory 247628 kb
Host smart-4624e731-454e-47e9-943e-56d25a422787
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2865760645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.2865760645
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1940033737
Short name T255
Test name
Test status
Simulation time 74228082 ps
CPU time 6.18 seconds
Started Feb 18 01:40:16 PM PST 24
Finished Feb 18 01:40:57 PM PST 24
Peak memory 236548 kb
Host smart-ddc636da-5720-4ae5-b29e-59a0026475eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1940033737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.1940033737
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3525703363
Short name T779
Test name
Test status
Simulation time 7749643 ps
CPU time 1.45 seconds
Started Feb 18 01:40:24 PM PST 24
Finished Feb 18 01:40:55 PM PST 24
Peak memory 236608 kb
Host smart-eaee7f62-7175-446a-bc11-30dd4a1ede7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3525703363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.3525703363
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1014178775
Short name T734
Test name
Test status
Simulation time 1476699958 ps
CPU time 25.08 seconds
Started Feb 18 01:40:19 PM PST 24
Finished Feb 18 01:41:16 PM PST 24
Peak memory 240448 kb
Host smart-51b43fd8-ef99-4489-b184-9fa6f200210f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1014178775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.1014178775
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.1868371057
Short name T148
Test name
Test status
Simulation time 4330801926 ps
CPU time 308.61 seconds
Started Feb 18 01:40:16 PM PST 24
Finished Feb 18 01:45:58 PM PST 24
Peak memory 267812 kb
Host smart-a7e11b53-d1e8-44ed-85d1-46cf232ece78
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868371057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.1868371057
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2539929633
Short name T795
Test name
Test status
Simulation time 94903296 ps
CPU time 12.48 seconds
Started Feb 18 01:40:25 PM PST 24
Finished Feb 18 01:41:07 PM PST 24
Peak memory 248408 kb
Host smart-b782d027-c257-4c69-b9f1-09a207aff79f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2539929633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.2539929633
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2956609307
Short name T763
Test name
Test status
Simulation time 2259130795 ps
CPU time 38.79 seconds
Started Feb 18 01:40:26 PM PST 24
Finished Feb 18 01:41:33 PM PST 24
Peak memory 239328 kb
Host smart-5dd89a9c-7628-4b5b-b37f-e5e44429d080
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2956609307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.2956609307
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3386593054
Short name T788
Test name
Test status
Simulation time 127455548 ps
CPU time 19.29 seconds
Started Feb 18 01:40:23 PM PST 24
Finished Feb 18 01:41:12 PM PST 24
Peak memory 256876 kb
Host smart-f94cb83f-2bc4-4dd5-9b27-3024a054fdc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386593054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.3386593054
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.700300350
Short name T247
Test name
Test status
Simulation time 517497490 ps
CPU time 10.23 seconds
Started Feb 18 01:40:19 PM PST 24
Finished Feb 18 01:41:01 PM PST 24
Peak memory 236516 kb
Host smart-18b3a3f3-3771-43e8-b235-b3fd952fa81c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=700300350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.700300350
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.2720370248
Short name T802
Test name
Test status
Simulation time 12546050 ps
CPU time 1.44 seconds
Started Feb 18 01:40:18 PM PST 24
Finished Feb 18 01:40:53 PM PST 24
Peak memory 235756 kb
Host smart-e2093843-5185-428a-928e-68689e635c37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2720370248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.2720370248
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1343968079
Short name T717
Test name
Test status
Simulation time 171256046 ps
CPU time 21.83 seconds
Started Feb 18 01:40:17 PM PST 24
Finished Feb 18 01:41:12 PM PST 24
Peak memory 244740 kb
Host smart-f7d318dc-dda6-4920-95ad-b2b84c8b5e4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1343968079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.1343968079
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3685708140
Short name T171
Test name
Test status
Simulation time 10158128413 ps
CPU time 311.09 seconds
Started Feb 18 01:40:17 PM PST 24
Finished Feb 18 01:46:01 PM PST 24
Peak memory 267936 kb
Host smart-1b31cece-0825-4456-b516-c3274bbf080b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685708140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.3685708140
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2096523471
Short name T251
Test name
Test status
Simulation time 139054632 ps
CPU time 9.58 seconds
Started Feb 18 01:40:25 PM PST 24
Finished Feb 18 01:41:04 PM PST 24
Peak memory 248572 kb
Host smart-7b6cee82-682b-4314-9812-4ac576772c4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2096523471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.2096523471
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1516203693
Short name T780
Test name
Test status
Simulation time 127161736 ps
CPU time 10.3 seconds
Started Feb 18 01:40:23 PM PST 24
Finished Feb 18 01:41:03 PM PST 24
Peak memory 252440 kb
Host smart-1c95d679-85f9-4686-aa77-18c449838e65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516203693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.1516203693
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.1864819603
Short name T735
Test name
Test status
Simulation time 254477503 ps
CPU time 4.69 seconds
Started Feb 18 01:40:25 PM PST 24
Finished Feb 18 01:40:59 PM PST 24
Peak memory 235648 kb
Host smart-5b4e3e60-2318-4d06-8af3-730c2fee9d2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1864819603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.1864819603
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.4216163503
Short name T721
Test name
Test status
Simulation time 12424739 ps
CPU time 1.45 seconds
Started Feb 18 01:40:24 PM PST 24
Finished Feb 18 01:40:55 PM PST 24
Peak memory 236596 kb
Host smart-f2e30058-0235-4a16-bdce-f44d6e121ec7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4216163503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.4216163503
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.738543720
Short name T203
Test name
Test status
Simulation time 1227124815 ps
CPU time 43.32 seconds
Started Feb 18 01:40:25 PM PST 24
Finished Feb 18 01:41:39 PM PST 24
Peak memory 248608 kb
Host smart-98d2d7cc-8a53-4044-bf20-f7347097a8e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=738543720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_out
standing.738543720
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.4199657317
Short name T158
Test name
Test status
Simulation time 2042853246 ps
CPU time 138.3 seconds
Started Feb 18 01:40:29 PM PST 24
Finished Feb 18 01:43:14 PM PST 24
Peak memory 257044 kb
Host smart-ff87775a-f173-47b0-9cc3-5a7fd845c9d7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4199657317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.4199657317
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.3169372472
Short name T740
Test name
Test status
Simulation time 71628444 ps
CPU time 5.24 seconds
Started Feb 18 01:40:23 PM PST 24
Finished Feb 18 01:40:58 PM PST 24
Peak memory 248556 kb
Host smart-a2c7ce3e-9c3e-488e-ab78-cdad4b5c19db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3169372472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.3169372472
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.801232992
Short name T774
Test name
Test status
Simulation time 101630960 ps
CPU time 15.68 seconds
Started Feb 18 01:40:33 PM PST 24
Finished Feb 18 01:41:14 PM PST 24
Peak memory 256784 kb
Host smart-d503ee39-b732-4eb4-bc74-53fb221dc9b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801232992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.alert_handler_csr_mem_rw_with_rand_reset.801232992
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2726210588
Short name T785
Test name
Test status
Simulation time 48429882 ps
CPU time 4.8 seconds
Started Feb 18 01:40:23 PM PST 24
Finished Feb 18 01:40:58 PM PST 24
Peak memory 240404 kb
Host smart-0165f744-57e4-434d-baa7-671c166a180b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2726210588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.2726210588
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1147309359
Short name T783
Test name
Test status
Simulation time 10113852 ps
CPU time 1.4 seconds
Started Feb 18 01:40:25 PM PST 24
Finished Feb 18 01:40:56 PM PST 24
Peak memory 236616 kb
Host smart-5aaffe22-d298-41d8-9fa9-afda64bc636c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1147309359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.1147309359
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2016445853
Short name T759
Test name
Test status
Simulation time 4773408280 ps
CPU time 18.42 seconds
Started Feb 18 01:40:39 PM PST 24
Finished Feb 18 01:41:20 PM PST 24
Peak memory 244632 kb
Host smart-07a034cb-03ad-4f7d-9e75-a7e42778659d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2016445853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.2016445853
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1249983094
Short name T155
Test name
Test status
Simulation time 8972682673 ps
CPU time 337.56 seconds
Started Feb 18 01:40:22 PM PST 24
Finished Feb 18 01:46:30 PM PST 24
Peak memory 265344 kb
Host smart-472a9596-84f9-4eed-a530-3cf05aed983c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249983094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.1249983094
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1555973068
Short name T747
Test name
Test status
Simulation time 1321012363 ps
CPU time 8.39 seconds
Started Feb 18 01:40:24 PM PST 24
Finished Feb 18 01:41:02 PM PST 24
Peak memory 248208 kb
Host smart-24888642-f348-4bf2-88d5-5ee2242ee9f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1555973068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.1555973068
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1275944758
Short name T192
Test name
Test status
Simulation time 514679683 ps
CPU time 9.77 seconds
Started Feb 18 01:40:35 PM PST 24
Finished Feb 18 01:41:09 PM PST 24
Peak memory 236492 kb
Host smart-96b3298e-be43-459a-a3cf-2e4de9fff7c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1275944758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1275944758
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1719162328
Short name T720
Test name
Test status
Simulation time 703135743 ps
CPU time 25.45 seconds
Started Feb 18 01:40:39 PM PST 24
Finished Feb 18 01:41:27 PM PST 24
Peak memory 244704 kb
Host smart-3c906941-d11a-4e33-86e1-19487e85c1f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1719162328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.1719162328
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3786157160
Short name T146
Test name
Test status
Simulation time 8468221679 ps
CPU time 349.83 seconds
Started Feb 18 01:40:45 PM PST 24
Finished Feb 18 01:46:55 PM PST 24
Peak memory 265336 kb
Host smart-8caa9507-d532-4742-9fb1-c9ab10bcea8b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3786157160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.3786157160
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3809245089
Short name T140
Test name
Test status
Simulation time 2175636607 ps
CPU time 333.09 seconds
Started Feb 18 01:40:37 PM PST 24
Finished Feb 18 01:46:33 PM PST 24
Peak memory 265360 kb
Host smart-383105ed-b932-4347-8e0f-2e55a6852883
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809245089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.3809245089
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.2375287645
Short name T754
Test name
Test status
Simulation time 327436783 ps
CPU time 22.44 seconds
Started Feb 18 01:40:45 PM PST 24
Finished Feb 18 01:41:28 PM PST 24
Peak memory 254064 kb
Host smart-6ac36152-076c-425d-87f8-80e321130bc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2375287645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.2375287645
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.2309955851
Short name T704
Test name
Test status
Simulation time 176656302 ps
CPU time 20.01 seconds
Started Feb 18 01:40:41 PM PST 24
Finished Feb 18 01:41:23 PM PST 24
Peak memory 256768 kb
Host smart-d406864b-1d30-48f5-ad0a-7fbda0f9b471
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309955851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.2309955851
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.1642110803
Short name T761
Test name
Test status
Simulation time 183612520 ps
CPU time 4.57 seconds
Started Feb 18 01:40:31 PM PST 24
Finished Feb 18 01:41:02 PM PST 24
Peak memory 236504 kb
Host smart-fb54b80b-193f-457b-9788-b8c5fee84393
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1642110803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.1642110803
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.3193209004
Short name T177
Test name
Test status
Simulation time 18884150 ps
CPU time 1.46 seconds
Started Feb 18 01:40:38 PM PST 24
Finished Feb 18 01:41:02 PM PST 24
Peak memory 236604 kb
Host smart-5f80fb8f-d0f0-45ca-9c9c-b55b22e5c363
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3193209004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.3193209004
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2041607313
Short name T707
Test name
Test status
Simulation time 740908675 ps
CPU time 24.25 seconds
Started Feb 18 01:40:35 PM PST 24
Finished Feb 18 01:41:24 PM PST 24
Peak memory 244712 kb
Host smart-9c4e5ea7-5e3e-4017-b706-307db73798fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2041607313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.2041607313
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1311321870
Short name T141
Test name
Test status
Simulation time 7823860075 ps
CPU time 575.05 seconds
Started Feb 18 01:40:44 PM PST 24
Finished Feb 18 01:50:40 PM PST 24
Peak memory 267752 kb
Host smart-d5d8b64d-ff90-4faa-a836-1f5e99a8c381
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311321870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.1311321870
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3363535503
Short name T792
Test name
Test status
Simulation time 1061541680 ps
CPU time 29.74 seconds
Started Feb 18 01:40:35 PM PST 24
Finished Feb 18 01:41:29 PM PST 24
Peak memory 246464 kb
Host smart-afc1979b-c35e-43f0-a4a6-7c2e638db19c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3363535503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.3363535503
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.3247796804
Short name T249
Test name
Test status
Simulation time 74726156 ps
CPU time 5.75 seconds
Started Feb 18 01:40:39 PM PST 24
Finished Feb 18 01:41:07 PM PST 24
Peak memory 236388 kb
Host smart-d638ef24-5298-48d1-b071-cc4c2f7b0f4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3247796804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.3247796804
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.533402313
Short name T772
Test name
Test status
Simulation time 13021041 ps
CPU time 1.74 seconds
Started Feb 18 01:40:45 PM PST 24
Finished Feb 18 01:41:07 PM PST 24
Peak memory 235816 kb
Host smart-391e1015-5a99-47d7-9177-bb5eb24870c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=533402313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.533402313
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3335066911
Short name T731
Test name
Test status
Simulation time 349248473 ps
CPU time 23.53 seconds
Started Feb 18 01:40:36 PM PST 24
Finished Feb 18 01:41:23 PM PST 24
Peak memory 240408 kb
Host smart-44f398a1-37d0-4951-943c-400fe0326158
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3335066911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.3335066911
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.2152852894
Short name T742
Test name
Test status
Simulation time 290586637 ps
CPU time 19.89 seconds
Started Feb 18 01:40:36 PM PST 24
Finished Feb 18 01:41:20 PM PST 24
Peak memory 253604 kb
Host smart-06aba02e-36c8-4e8c-826c-61a200988c66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2152852894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.2152852894
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.1238977969
Short name T194
Test name
Test status
Simulation time 98436611 ps
CPU time 7.68 seconds
Started Feb 18 01:40:37 PM PST 24
Finished Feb 18 01:41:08 PM PST 24
Peak memory 236504 kb
Host smart-73c1a557-6940-4490-8d5b-0ec3a3beaddc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1238977969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.1238977969
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.3949520407
Short name T176
Test name
Test status
Simulation time 7993997 ps
CPU time 1.54 seconds
Started Feb 18 01:40:41 PM PST 24
Finished Feb 18 01:41:04 PM PST 24
Peak memory 235616 kb
Host smart-84fdcf3f-b784-4d74-8386-c37b2618c74e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3949520407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.3949520407
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.4163109358
Short name T801
Test name
Test status
Simulation time 697137420 ps
CPU time 48.91 seconds
Started Feb 18 01:40:39 PM PST 24
Finished Feb 18 01:41:50 PM PST 24
Peak memory 244724 kb
Host smart-dcdf42fb-07dd-423c-9d52-e20f76d51262
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4163109358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.4163109358
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1982875695
Short name T159
Test name
Test status
Simulation time 1672791641 ps
CPU time 86.74 seconds
Started Feb 18 01:40:45 PM PST 24
Finished Feb 18 01:42:32 PM PST 24
Peak memory 257072 kb
Host smart-55fb2d72-e1c5-4fef-aa73-0fc220f27f92
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1982875695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.1982875695
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.691424661
Short name T359
Test name
Test status
Simulation time 60476103743 ps
CPU time 572.19 seconds
Started Feb 18 01:40:38 PM PST 24
Finished Feb 18 01:50:33 PM PST 24
Peak memory 265336 kb
Host smart-f40f37ac-52bf-45da-9dc6-3b8aa1c9046f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691424661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.691424661
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3330643225
Short name T728
Test name
Test status
Simulation time 81980299 ps
CPU time 9.19 seconds
Started Feb 18 01:40:36 PM PST 24
Finished Feb 18 01:41:09 PM PST 24
Peak memory 248708 kb
Host smart-ce487d93-3362-49b2-9f0f-c571244056d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3330643225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.3330643225
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3099771750
Short name T714
Test name
Test status
Simulation time 7915421945 ps
CPU time 127.59 seconds
Started Feb 18 01:39:49 PM PST 24
Finished Feb 18 01:42:39 PM PST 24
Peak memory 240488 kb
Host smart-8695bb75-d4ee-4a8c-afb4-01b470b1fed6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3099771750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.3099771750
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.123276354
Short name T778
Test name
Test status
Simulation time 81438484104 ps
CPU time 379.78 seconds
Started Feb 18 01:39:42 PM PST 24
Finished Feb 18 01:46:41 PM PST 24
Peak memory 236464 kb
Host smart-f268b458-e70a-485a-99a5-cd190d8989af
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=123276354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.123276354
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.4125378438
Short name T771
Test name
Test status
Simulation time 439255395 ps
CPU time 8.34 seconds
Started Feb 18 01:39:44 PM PST 24
Finished Feb 18 01:40:35 PM PST 24
Peak memory 240440 kb
Host smart-4bde68a0-a6ae-4031-a700-47e7225367fd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4125378438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.4125378438
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.216853571
Short name T719
Test name
Test status
Simulation time 538423767 ps
CPU time 8.29 seconds
Started Feb 18 01:39:49 PM PST 24
Finished Feb 18 01:40:39 PM PST 24
Peak memory 236516 kb
Host smart-1fd7259f-00b1-47ea-b9be-cd67beff8a99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=216853571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.216853571
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.1486616484
Short name T357
Test name
Test status
Simulation time 7289145 ps
CPU time 1.37 seconds
Started Feb 18 01:39:44 PM PST 24
Finished Feb 18 01:40:32 PM PST 24
Peak memory 235724 kb
Host smart-0b9be9e5-1e14-4196-ae4b-320627267318
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1486616484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.1486616484
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2704204665
Short name T789
Test name
Test status
Simulation time 489775009 ps
CPU time 38.27 seconds
Started Feb 18 01:39:44 PM PST 24
Finished Feb 18 01:41:03 PM PST 24
Peak memory 244724 kb
Host smart-434f2ca9-32af-4d07-a4d7-7ab04e33b5ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2704204665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.2704204665
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1745156353
Short name T172
Test name
Test status
Simulation time 4684599563 ps
CPU time 166.45 seconds
Started Feb 18 01:39:38 PM PST 24
Finished Feb 18 01:43:07 PM PST 24
Peak memory 257072 kb
Host smart-694e8070-adc5-40e0-81ab-a1c83e27e545
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1745156353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.1745156353
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.3399940435
Short name T781
Test name
Test status
Simulation time 1515056371 ps
CPU time 14.93 seconds
Started Feb 18 01:39:41 PM PST 24
Finished Feb 18 01:40:42 PM PST 24
Peak memory 248364 kb
Host smart-acc97aea-678d-40b4-8599-daacbc1ef2b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3399940435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.3399940435
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2888055838
Short name T750
Test name
Test status
Simulation time 8571503 ps
CPU time 1.59 seconds
Started Feb 18 01:40:35 PM PST 24
Finished Feb 18 01:41:01 PM PST 24
Peak memory 236536 kb
Host smart-dd875739-d15e-4bc6-8b2b-299a101518d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2888055838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.2888055838
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.4222957285
Short name T765
Test name
Test status
Simulation time 16369801 ps
CPU time 1.65 seconds
Started Feb 18 01:40:35 PM PST 24
Finished Feb 18 01:41:01 PM PST 24
Peak memory 236604 kb
Host smart-5cf2efa9-1c59-4e89-97cf-7ed677400b1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4222957285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.4222957285
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2857841765
Short name T776
Test name
Test status
Simulation time 14361973 ps
CPU time 1.37 seconds
Started Feb 18 01:40:40 PM PST 24
Finished Feb 18 01:41:03 PM PST 24
Peak memory 234748 kb
Host smart-d1b187b9-9933-410e-bafd-348c91d54fd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2857841765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.2857841765
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.3921833673
Short name T786
Test name
Test status
Simulation time 7395037 ps
CPU time 1.53 seconds
Started Feb 18 01:40:41 PM PST 24
Finished Feb 18 01:41:04 PM PST 24
Peak memory 235616 kb
Host smart-458717e4-d2a4-48b3-adb7-c529d4f3d39d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3921833673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.3921833673
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.3598862251
Short name T762
Test name
Test status
Simulation time 45319427 ps
CPU time 1.28 seconds
Started Feb 18 01:40:37 PM PST 24
Finished Feb 18 01:41:02 PM PST 24
Peak memory 235596 kb
Host smart-eb0d6aa6-185f-48e1-8700-c98f0fe58b92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3598862251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.3598862251
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.4256614153
Short name T743
Test name
Test status
Simulation time 7961741 ps
CPU time 1.46 seconds
Started Feb 18 01:40:37 PM PST 24
Finished Feb 18 01:41:02 PM PST 24
Peak memory 236616 kb
Host smart-3444333e-53f9-4064-b9ba-1d999b025154
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4256614153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.4256614153
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.1313940480
Short name T744
Test name
Test status
Simulation time 33367364 ps
CPU time 1.34 seconds
Started Feb 18 01:40:51 PM PST 24
Finished Feb 18 01:41:10 PM PST 24
Peak memory 234756 kb
Host smart-508eb3e7-30c0-4bb5-82fd-d8f2048b098f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1313940480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.1313940480
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.502197417
Short name T716
Test name
Test status
Simulation time 7165028 ps
CPU time 1.33 seconds
Started Feb 18 01:40:49 PM PST 24
Finished Feb 18 01:41:09 PM PST 24
Peak memory 236572 kb
Host smart-c3232fd9-d227-462b-ae07-702a07a3232a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=502197417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.502197417
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.2887102262
Short name T723
Test name
Test status
Simulation time 11934801 ps
CPU time 1.32 seconds
Started Feb 18 01:40:43 PM PST 24
Finished Feb 18 01:41:05 PM PST 24
Peak memory 236604 kb
Host smart-f85811f5-529a-4e88-9f8f-72eb3e3e6636
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2887102262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.2887102262
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.4213370338
Short name T356
Test name
Test status
Simulation time 10953918 ps
CPU time 1.67 seconds
Started Feb 18 01:40:44 PM PST 24
Finished Feb 18 01:41:06 PM PST 24
Peak memory 235692 kb
Host smart-60b15bb6-08de-4662-93fb-6f98ce1efa2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4213370338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.4213370338
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2667221057
Short name T796
Test name
Test status
Simulation time 17615879020 ps
CPU time 292.29 seconds
Started Feb 18 01:39:51 PM PST 24
Finished Feb 18 01:45:23 PM PST 24
Peak memory 239004 kb
Host smart-7415ef1a-ec87-4cfa-8137-9b81119aad97
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2667221057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.2667221057
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.2222011969
Short name T769
Test name
Test status
Simulation time 4085011152 ps
CPU time 224.53 seconds
Started Feb 18 01:39:54 PM PST 24
Finished Feb 18 01:44:20 PM PST 24
Peak memory 236600 kb
Host smart-17ca3adf-9d68-4f1a-bb85-6123e3bc72d4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2222011969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.2222011969
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1928815522
Short name T738
Test name
Test status
Simulation time 72360721 ps
CPU time 3.38 seconds
Started Feb 18 01:39:53 PM PST 24
Finished Feb 18 01:40:39 PM PST 24
Peak memory 240452 kb
Host smart-d6ee3fc1-16ee-42a0-ad5e-0357003ff10c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1928815522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.1928815522
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2924150493
Short name T760
Test name
Test status
Simulation time 35454091 ps
CPU time 3.41 seconds
Started Feb 18 01:39:59 PM PST 24
Finished Feb 18 01:40:43 PM PST 24
Peak memory 236524 kb
Host smart-b60f44f4-a2eb-4e04-9122-23e6a1f67200
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2924150493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.2924150493
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.311469704
Short name T709
Test name
Test status
Simulation time 13400027 ps
CPU time 1.31 seconds
Started Feb 18 01:39:49 PM PST 24
Finished Feb 18 01:40:32 PM PST 24
Peak memory 234692 kb
Host smart-eab19775-bde6-4725-88f7-86fb50b77a2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=311469704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.311469704
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.3750813437
Short name T248
Test name
Test status
Simulation time 702064006 ps
CPU time 50.69 seconds
Started Feb 18 01:39:52 PM PST 24
Finished Feb 18 01:41:24 PM PST 24
Peak memory 244736 kb
Host smart-84560620-9817-4cd6-b7ff-7798ea14a473
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3750813437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.3750813437
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2630719965
Short name T147
Test name
Test status
Simulation time 2038132002 ps
CPU time 227.98 seconds
Started Feb 18 01:40:00 PM PST 24
Finished Feb 18 01:44:27 PM PST 24
Peak memory 270844 kb
Host smart-b8c70e3a-4253-4dd6-8205-36556fbb1617
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2630719965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.2630719965
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1537977820
Short name T358
Test name
Test status
Simulation time 25532517765 ps
CPU time 490.39 seconds
Started Feb 18 01:39:44 PM PST 24
Finished Feb 18 01:48:36 PM PST 24
Peak memory 265328 kb
Host smart-be0edce3-b03d-472f-9ef4-5c3d11548218
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537977820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.1537977820
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3105126069
Short name T727
Test name
Test status
Simulation time 212012045 ps
CPU time 16.14 seconds
Started Feb 18 01:39:40 PM PST 24
Finished Feb 18 01:40:37 PM PST 24
Peak memory 248784 kb
Host smart-bb5e81d9-a1df-4a2a-be75-1c2225bfe9a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3105126069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.3105126069
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.1353798793
Short name T787
Test name
Test status
Simulation time 10858384 ps
CPU time 1.41 seconds
Started Feb 18 01:40:44 PM PST 24
Finished Feb 18 01:41:06 PM PST 24
Peak memory 234764 kb
Host smart-a3b7c264-afd2-4ad5-9a94-2a7b5896c487
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1353798793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.1353798793
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.1162904961
Short name T252
Test name
Test status
Simulation time 25113560 ps
CPU time 1.56 seconds
Started Feb 18 01:40:47 PM PST 24
Finished Feb 18 01:41:08 PM PST 24
Peak memory 236536 kb
Host smart-6eb8af42-f1d7-4b30-89cc-f6b058e01685
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1162904961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.1162904961
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.2294055272
Short name T254
Test name
Test status
Simulation time 14826361 ps
CPU time 1.76 seconds
Started Feb 18 01:40:44 PM PST 24
Finished Feb 18 01:41:06 PM PST 24
Peak memory 235692 kb
Host smart-0ae233f9-60f8-455e-bebc-9dc3a28f465e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2294055272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.2294055272
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.3732413521
Short name T793
Test name
Test status
Simulation time 7786816 ps
CPU time 1.44 seconds
Started Feb 18 01:40:45 PM PST 24
Finished Feb 18 01:41:07 PM PST 24
Peak memory 234712 kb
Host smart-0ddf74b2-780d-4eca-8905-3616164be49d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3732413521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.3732413521
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1897201577
Short name T741
Test name
Test status
Simulation time 8562074 ps
CPU time 1.61 seconds
Started Feb 18 01:40:42 PM PST 24
Finished Feb 18 01:41:05 PM PST 24
Peak memory 235884 kb
Host smart-a9cbb282-37c2-4f3a-a70f-caf3a75bf7ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1897201577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.1897201577
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.4130454163
Short name T713
Test name
Test status
Simulation time 9772221 ps
CPU time 1.6 seconds
Started Feb 18 01:40:49 PM PST 24
Finished Feb 18 01:41:10 PM PST 24
Peak memory 235772 kb
Host smart-122869bb-5d7c-41f9-a76c-ed725e1727f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4130454163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.4130454163
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.2432824126
Short name T748
Test name
Test status
Simulation time 9468609 ps
CPU time 1.59 seconds
Started Feb 18 01:40:43 PM PST 24
Finished Feb 18 01:41:06 PM PST 24
Peak memory 235712 kb
Host smart-1daec43a-e006-42a2-a345-61cc4b9174ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2432824126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.2432824126
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.4264294125
Short name T739
Test name
Test status
Simulation time 12127516 ps
CPU time 1.3 seconds
Started Feb 18 01:40:46 PM PST 24
Finished Feb 18 01:41:07 PM PST 24
Peak memory 235724 kb
Host smart-05618e47-691f-4851-b599-5ec4879c6f28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4264294125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.4264294125
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1400423756
Short name T205
Test name
Test status
Simulation time 4587307456 ps
CPU time 150.93 seconds
Started Feb 18 01:39:59 PM PST 24
Finished Feb 18 01:43:10 PM PST 24
Peak memory 239792 kb
Host smart-49dd2d1f-f5cd-48ef-8f2e-6208613eff45
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1400423756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.1400423756
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.144504237
Short name T768
Test name
Test status
Simulation time 10183240346 ps
CPU time 344.29 seconds
Started Feb 18 01:39:56 PM PST 24
Finished Feb 18 01:46:23 PM PST 24
Peak memory 240472 kb
Host smart-58b4a204-7ab0-4179-b93e-c5795d8b9446
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=144504237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.144504237
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2843540351
Short name T797
Test name
Test status
Simulation time 199343169 ps
CPU time 4.8 seconds
Started Feb 18 01:39:49 PM PST 24
Finished Feb 18 01:40:36 PM PST 24
Peak memory 240440 kb
Host smart-c64d698f-dca5-4dcc-a5a5-15507abb7049
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2843540351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.2843540351
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.2629474431
Short name T737
Test name
Test status
Simulation time 188942182 ps
CPU time 8.22 seconds
Started Feb 18 01:39:57 PM PST 24
Finished Feb 18 01:40:47 PM PST 24
Peak memory 236528 kb
Host smart-391298ed-6271-4b7d-b81c-5e148df356dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2629474431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.2629474431
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.3147965390
Short name T773
Test name
Test status
Simulation time 8450761 ps
CPU time 1.59 seconds
Started Feb 18 01:40:08 PM PST 24
Finished Feb 18 01:40:46 PM PST 24
Peak memory 235732 kb
Host smart-8518ebc9-28c2-49d8-be2a-d2a916b0e9ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3147965390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.3147965390
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.941551363
Short name T193
Test name
Test status
Simulation time 324258759 ps
CPU time 21.87 seconds
Started Feb 18 01:39:56 PM PST 24
Finished Feb 18 01:40:56 PM PST 24
Peak memory 243848 kb
Host smart-77dce092-9289-4585-b329-7204b50a9dfe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=941551363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outs
tanding.941551363
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1901464675
Short name T136
Test name
Test status
Simulation time 57600085395 ps
CPU time 501.55 seconds
Started Feb 18 01:39:53 PM PST 24
Finished Feb 18 01:48:57 PM PST 24
Peak memory 265368 kb
Host smart-b99168ee-9b71-485d-8f84-3a60cf913706
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901464675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.1901464675
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.3659929198
Short name T746
Test name
Test status
Simulation time 54690582 ps
CPU time 7.33 seconds
Started Feb 18 01:39:59 PM PST 24
Finished Feb 18 01:40:47 PM PST 24
Peak memory 247516 kb
Host smart-0a03942f-0b51-47bb-ab54-a8ee8b878527
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3659929198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.3659929198
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2674680374
Short name T175
Test name
Test status
Simulation time 49860825 ps
CPU time 2.3 seconds
Started Feb 18 01:40:05 PM PST 24
Finished Feb 18 01:40:44 PM PST 24
Peak memory 236476 kb
Host smart-6e0be5b5-b547-4b26-8da9-753a3eba6d3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2674680374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.2674680374
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.4004672466
Short name T253
Test name
Test status
Simulation time 11855648 ps
CPU time 1.75 seconds
Started Feb 18 01:40:45 PM PST 24
Finished Feb 18 01:41:07 PM PST 24
Peak memory 235700 kb
Host smart-b18ddb21-e98f-43d6-ad40-68db52136a4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4004672466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.4004672466
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3376179100
Short name T726
Test name
Test status
Simulation time 6676308 ps
CPU time 1.46 seconds
Started Feb 18 01:40:44 PM PST 24
Finished Feb 18 01:41:07 PM PST 24
Peak memory 236612 kb
Host smart-d0b7a0cc-f441-400a-8ab1-867151586337
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3376179100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.3376179100
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2424032665
Short name T355
Test name
Test status
Simulation time 9583548 ps
CPU time 1.37 seconds
Started Feb 18 01:40:46 PM PST 24
Finished Feb 18 01:41:07 PM PST 24
Peak memory 235752 kb
Host smart-65bacab2-7466-4446-8547-af6c7b3e2e33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2424032665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.2424032665
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.2142740372
Short name T710
Test name
Test status
Simulation time 7120629 ps
CPU time 1.4 seconds
Started Feb 18 01:40:46 PM PST 24
Finished Feb 18 01:41:07 PM PST 24
Peak memory 235780 kb
Host smart-36a3cab3-0a62-4baa-b549-2cbf80c7e095
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2142740372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.2142740372
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.3633284063
Short name T715
Test name
Test status
Simulation time 15091956 ps
CPU time 1.55 seconds
Started Feb 18 01:40:45 PM PST 24
Finished Feb 18 01:41:07 PM PST 24
Peak memory 236596 kb
Host smart-f44a223e-3121-4eba-b21d-1e0374c35f8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3633284063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.3633284063
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3698745076
Short name T352
Test name
Test status
Simulation time 9423959 ps
CPU time 1.24 seconds
Started Feb 18 01:40:45 PM PST 24
Finished Feb 18 01:41:07 PM PST 24
Peak memory 235724 kb
Host smart-39aed741-3ac2-4861-8a41-a5f865adc2cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3698745076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.3698745076
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.804247141
Short name T702
Test name
Test status
Simulation time 10885595 ps
CPU time 1.64 seconds
Started Feb 18 01:40:45 PM PST 24
Finished Feb 18 01:41:07 PM PST 24
Peak memory 235744 kb
Host smart-26c6bdb4-fb89-4985-970b-9ee1ae0e137e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=804247141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.804247141
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.4201758424
Short name T732
Test name
Test status
Simulation time 11537711 ps
CPU time 1.42 seconds
Started Feb 18 01:40:49 PM PST 24
Finished Feb 18 01:41:09 PM PST 24
Peak memory 235808 kb
Host smart-4337d92a-31d8-4972-a02d-b8e1cf880552
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4201758424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.4201758424
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1407546574
Short name T751
Test name
Test status
Simulation time 10415048 ps
CPU time 1.24 seconds
Started Feb 18 01:40:48 PM PST 24
Finished Feb 18 01:41:08 PM PST 24
Peak memory 235728 kb
Host smart-5509f791-bf47-4081-8321-8aceb60b46f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1407546574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.1407546574
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.3723144092
Short name T749
Test name
Test status
Simulation time 35621426 ps
CPU time 1.43 seconds
Started Feb 18 01:40:48 PM PST 24
Finished Feb 18 01:41:09 PM PST 24
Peak memory 235740 kb
Host smart-a8f2fccb-9108-4d01-8cc9-dfa6c706c1d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3723144092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.3723144092
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.44158578
Short name T705
Test name
Test status
Simulation time 284582376 ps
CPU time 16.33 seconds
Started Feb 18 01:39:58 PM PST 24
Finished Feb 18 01:40:54 PM PST 24
Peak memory 251068 kb
Host smart-05f3fe8e-9993-4393-8d2f-0ea42f3b06dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44158578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 5.alert_handler_csr_mem_rw_with_rand_reset.44158578
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.4202692880
Short name T703
Test name
Test status
Simulation time 126115809 ps
CPU time 5.04 seconds
Started Feb 18 01:40:04 PM PST 24
Finished Feb 18 01:40:47 PM PST 24
Peak memory 236524 kb
Host smart-43b798c7-351b-4fce-a5b0-e7e0dbbf6812
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4202692880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.4202692880
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.241730047
Short name T764
Test name
Test status
Simulation time 11376391 ps
CPU time 1.35 seconds
Started Feb 18 01:39:55 PM PST 24
Finished Feb 18 01:40:37 PM PST 24
Peak memory 234628 kb
Host smart-4e3adffa-9dd7-4dae-b668-a13ea96d8c13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=241730047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.241730047
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.2215437549
Short name T724
Test name
Test status
Simulation time 89117005 ps
CPU time 13.18 seconds
Started Feb 18 01:39:58 PM PST 24
Finished Feb 18 01:40:57 PM PST 24
Peak memory 239588 kb
Host smart-55206908-6161-4e46-a1be-b00564733894
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2215437549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.2215437549
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.131336093
Short name T169
Test name
Test status
Simulation time 1911778125 ps
CPU time 150.75 seconds
Started Feb 18 01:39:58 PM PST 24
Finished Feb 18 01:43:09 PM PST 24
Peak memory 257084 kb
Host smart-d50299bb-ae74-4274-a12a-ea484e763cc6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=131336093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_error
s.131336093
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2993742463
Short name T701
Test name
Test status
Simulation time 231588810 ps
CPU time 19.55 seconds
Started Feb 18 01:39:56 PM PST 24
Finished Feb 18 01:40:56 PM PST 24
Peak memory 248692 kb
Host smart-c3d06f7f-5271-4bd7-ac2d-afbd59c2a71b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2993742463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.2993742463
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3703956997
Short name T804
Test name
Test status
Simulation time 438350920 ps
CPU time 4.9 seconds
Started Feb 18 01:39:59 PM PST 24
Finished Feb 18 01:40:43 PM PST 24
Peak memory 239412 kb
Host smart-316ffb5e-02a3-45ac-91b9-29a57fdb0d50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3703956997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.3703956997
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.346458579
Short name T775
Test name
Test status
Simulation time 9921581 ps
CPU time 1.6 seconds
Started Feb 18 01:40:04 PM PST 24
Finished Feb 18 01:40:43 PM PST 24
Peak memory 236612 kb
Host smart-05211b84-0712-4040-8643-e3b681c6106a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=346458579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.346458579
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1723981113
Short name T798
Test name
Test status
Simulation time 517298951 ps
CPU time 45.15 seconds
Started Feb 18 01:40:00 PM PST 24
Finished Feb 18 01:41:24 PM PST 24
Peak memory 244736 kb
Host smart-df42c88f-b0d0-4830-8beb-234671566bdc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1723981113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.1723981113
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.760779471
Short name T156
Test name
Test status
Simulation time 15168659353 ps
CPU time 194.36 seconds
Started Feb 18 01:39:53 PM PST 24
Finished Feb 18 01:43:50 PM PST 24
Peak memory 265336 kb
Host smart-c7336033-0c8b-426b-8488-dd2516c858e8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=760779471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_error
s.760779471
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1171199033
Short name T700
Test name
Test status
Simulation time 119231934 ps
CPU time 8.91 seconds
Started Feb 18 01:40:01 PM PST 24
Finished Feb 18 01:40:49 PM PST 24
Peak memory 248588 kb
Host smart-9f794634-c990-499e-aef1-20a42130d079
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1171199033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.1171199033
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.2964145221
Short name T791
Test name
Test status
Simulation time 68252305 ps
CPU time 4.43 seconds
Started Feb 18 01:40:00 PM PST 24
Finished Feb 18 01:40:43 PM PST 24
Peak memory 236452 kb
Host smart-e23017d6-dfc5-49cb-80ba-e4b38ac0360c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2964145221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.2964145221
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3539192670
Short name T722
Test name
Test status
Simulation time 12041245 ps
CPU time 1.73 seconds
Started Feb 18 01:40:05 PM PST 24
Finished Feb 18 01:40:43 PM PST 24
Peak memory 236568 kb
Host smart-4aa6251f-80df-428c-84e7-ab644b05dbaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3539192670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3539192670
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2854858355
Short name T753
Test name
Test status
Simulation time 264728238 ps
CPU time 22.13 seconds
Started Feb 18 01:40:00 PM PST 24
Finished Feb 18 01:41:01 PM PST 24
Peak memory 240472 kb
Host smart-f61af4e4-511c-4033-a715-95046b110449
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2854858355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.2854858355
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1940069794
Short name T151
Test name
Test status
Simulation time 1243238606 ps
CPU time 120.84 seconds
Started Feb 18 01:40:00 PM PST 24
Finished Feb 18 01:42:42 PM PST 24
Peak memory 265236 kb
Host smart-16ea7925-9d92-4a0a-8735-58757511fa8d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1940069794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.1940069794
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.2567678985
Short name T142
Test name
Test status
Simulation time 7014976064 ps
CPU time 471.95 seconds
Started Feb 18 01:40:05 PM PST 24
Finished Feb 18 01:48:34 PM PST 24
Peak memory 265492 kb
Host smart-c871328c-4b3e-420e-a384-efe16ca33537
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567678985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.2567678985
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.1127428785
Short name T790
Test name
Test status
Simulation time 321525706 ps
CPU time 18.46 seconds
Started Feb 18 01:39:59 PM PST 24
Finished Feb 18 01:40:57 PM PST 24
Peak memory 247632 kb
Host smart-141cf887-b6af-416d-978d-e8aad8755cdd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1127428785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.1127428785
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3251651209
Short name T758
Test name
Test status
Simulation time 335733953 ps
CPU time 12.81 seconds
Started Feb 18 01:40:10 PM PST 24
Finished Feb 18 01:40:57 PM PST 24
Peak memory 256752 kb
Host smart-1f8e2909-d16b-42cf-a464-aedd450adbc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251651209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.3251651209
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.316078177
Short name T784
Test name
Test status
Simulation time 130560412 ps
CPU time 6 seconds
Started Feb 18 01:40:14 PM PST 24
Finished Feb 18 01:40:54 PM PST 24
Peak memory 236460 kb
Host smart-206e79e8-bc3b-43f9-85da-6a6c76792b51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=316078177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.316078177
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.3482417359
Short name T730
Test name
Test status
Simulation time 8471558 ps
CPU time 1.3 seconds
Started Feb 18 01:40:08 PM PST 24
Finished Feb 18 01:40:45 PM PST 24
Peak memory 236604 kb
Host smart-007447ac-7b28-4302-8587-4919bcfe5a01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3482417359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.3482417359
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.1503534163
Short name T757
Test name
Test status
Simulation time 264049388 ps
CPU time 19.94 seconds
Started Feb 18 01:40:13 PM PST 24
Finished Feb 18 01:41:07 PM PST 24
Peak memory 244704 kb
Host smart-bf79d8e5-6c95-4d40-87dd-0480eb5e2a0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1503534163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.1503534163
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3553095640
Short name T157
Test name
Test status
Simulation time 2980367697 ps
CPU time 203.83 seconds
Started Feb 18 01:40:09 PM PST 24
Finished Feb 18 01:44:08 PM PST 24
Peak memory 265204 kb
Host smart-0468fdfe-87da-4448-9839-2d277550e903
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3553095640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.3553095640
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3085044110
Short name T699
Test name
Test status
Simulation time 105821779 ps
CPU time 15.15 seconds
Started Feb 18 01:40:13 PM PST 24
Finished Feb 18 01:41:02 PM PST 24
Peak memory 248056 kb
Host smart-6075ef33-2ac5-49d6-9b61-41f57dd2863e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3085044110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.3085044110
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1518891184
Short name T189
Test name
Test status
Simulation time 563074417 ps
CPU time 22.77 seconds
Started Feb 18 01:40:35 PM PST 24
Finished Feb 18 01:41:22 PM PST 24
Peak memory 236608 kb
Host smart-b79f1843-58c5-4a11-816c-9f75fa6339f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1518891184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.1518891184
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.3909106682
Short name T782
Test name
Test status
Simulation time 49418173 ps
CPU time 4.98 seconds
Started Feb 18 01:40:41 PM PST 24
Finished Feb 18 01:41:07 PM PST 24
Peak memory 236524 kb
Host smart-07a36e26-e093-47c0-bd6f-91b4f6020253
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3909106682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.3909106682
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.3199003507
Short name T178
Test name
Test status
Simulation time 7300098 ps
CPU time 1.31 seconds
Started Feb 18 01:40:10 PM PST 24
Finished Feb 18 01:40:46 PM PST 24
Peak memory 236608 kb
Host smart-04da55b2-1d96-4a57-819d-cf7c1d990293
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3199003507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.3199003507
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.2639700356
Short name T745
Test name
Test status
Simulation time 357626806 ps
CPU time 11.59 seconds
Started Feb 18 01:40:11 PM PST 24
Finished Feb 18 01:40:58 PM PST 24
Peak memory 243832 kb
Host smart-d06759b5-de70-452e-99f8-a5335655ac63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2639700356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.2639700356
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1867068375
Short name T149
Test name
Test status
Simulation time 7484446069 ps
CPU time 94.09 seconds
Started Feb 18 01:40:07 PM PST 24
Finished Feb 18 01:42:18 PM PST 24
Peak memory 257116 kb
Host smart-77ef5788-0d13-432b-8ee4-b725520cfce3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1867068375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.1867068375
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.3347189423
Short name T756
Test name
Test status
Simulation time 44755405 ps
CPU time 5.61 seconds
Started Feb 18 01:40:06 PM PST 24
Finished Feb 18 01:40:48 PM PST 24
Peak memory 253820 kb
Host smart-336c2b1c-4e17-4f78-a1c4-42537faac16a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3347189423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.3347189423
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.1391703490
Short name T449
Test name
Test status
Simulation time 145015310278 ps
CPU time 2225.69 seconds
Started Feb 18 12:38:26 PM PST 24
Finished Feb 18 01:15:34 PM PST 24
Peak memory 272480 kb
Host smart-c8511b5d-510a-4f65-9ed5-bef2c1b59112
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391703490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.1391703490
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.551292305
Short name T648
Test name
Test status
Simulation time 676224390 ps
CPU time 18.62 seconds
Started Feb 18 12:38:28 PM PST 24
Finished Feb 18 12:38:49 PM PST 24
Peak memory 248232 kb
Host smart-9d2b4c4a-84d4-4157-9186-61914c3e890a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=551292305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.551292305
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.548260854
Short name T415
Test name
Test status
Simulation time 1328253283 ps
CPU time 68.95 seconds
Started Feb 18 12:38:34 PM PST 24
Finished Feb 18 12:39:46 PM PST 24
Peak memory 255532 kb
Host smart-d6dc5bd2-61c8-4133-83cd-502e3dc41af4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54826
0854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.548260854
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.195404884
Short name T548
Test name
Test status
Simulation time 173489129 ps
CPU time 14.6 seconds
Started Feb 18 12:38:30 PM PST 24
Finished Feb 18 12:38:47 PM PST 24
Peak memory 254752 kb
Host smart-0e0c8276-df4b-448f-8fb9-4cb5a7c65f75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19540
4884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.195404884
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.680527661
Short name T464
Test name
Test status
Simulation time 89846037700 ps
CPU time 1491.5 seconds
Started Feb 18 12:38:27 PM PST 24
Finished Feb 18 01:03:21 PM PST 24
Peak memory 272012 kb
Host smart-bcc2e036-7d53-47a8-950c-14fa907d79c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680527661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.680527661
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.1243937361
Short name T472
Test name
Test status
Simulation time 7297518280 ps
CPU time 240.31 seconds
Started Feb 18 12:38:37 PM PST 24
Finished Feb 18 12:42:39 PM PST 24
Peak memory 246272 kb
Host smart-ae15ff78-7d98-4a2e-ac15-69d217e93009
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243937361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.1243937361
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.1364752153
Short name T544
Test name
Test status
Simulation time 1622162343 ps
CPU time 25.55 seconds
Started Feb 18 12:38:35 PM PST 24
Finished Feb 18 12:39:03 PM PST 24
Peak memory 248296 kb
Host smart-bb420713-1252-4fd8-add0-29b89902f8f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13647
52153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.1364752153
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.2674116838
Short name T628
Test name
Test status
Simulation time 1084613806 ps
CPU time 54.83 seconds
Started Feb 18 12:38:27 PM PST 24
Finished Feb 18 12:39:24 PM PST 24
Peak memory 254564 kb
Host smart-d7515066-283f-4ef2-8f51-d18e8f7dfee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26741
16838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.2674116838
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.3497568128
Short name T13
Test name
Test status
Simulation time 690242975 ps
CPU time 19.68 seconds
Started Feb 18 12:38:34 PM PST 24
Finished Feb 18 12:38:56 PM PST 24
Peak memory 268512 kb
Host smart-3522dd47-d26c-43e5-95f1-81212a835378
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3497568128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.3497568128
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.3116756969
Short name T460
Test name
Test status
Simulation time 393604525 ps
CPU time 21.63 seconds
Started Feb 18 12:38:17 PM PST 24
Finished Feb 18 12:38:45 PM PST 24
Peak memory 248296 kb
Host smart-e0d1082f-a856-4dab-8437-eb3aaed4c4c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31167
56969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.3116756969
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.977373197
Short name T458
Test name
Test status
Simulation time 703823305 ps
CPU time 20.58 seconds
Started Feb 18 12:38:35 PM PST 24
Finished Feb 18 12:38:58 PM PST 24
Peak memory 255160 kb
Host smart-fb7fe797-3f81-431d-8b36-431b89a31657
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977373197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_hand
ler_stress_all.977373197
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.3555529716
Short name T647
Test name
Test status
Simulation time 58756000821 ps
CPU time 5501.7 seconds
Started Feb 18 12:38:30 PM PST 24
Finished Feb 18 02:10:15 PM PST 24
Peak memory 354396 kb
Host smart-88dc79c7-d4fb-48f9-aae4-737e2876155b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555529716 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.3555529716
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.3236000442
Short name T426
Test name
Test status
Simulation time 2137653560 ps
CPU time 18.39 seconds
Started Feb 18 12:38:30 PM PST 24
Finished Feb 18 12:38:50 PM PST 24
Peak memory 247988 kb
Host smart-c963fd13-42d3-4177-a010-9a23ad31e5da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32360
00442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.3236000442
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.3737160483
Short name T90
Test name
Test status
Simulation time 707529856 ps
CPU time 20.9 seconds
Started Feb 18 12:38:54 PM PST 24
Finished Feb 18 12:39:18 PM PST 24
Peak memory 254428 kb
Host smart-31011a1e-c0d1-48aa-bde3-12f786b363a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37371
60483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.3737160483
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.1458990577
Short name T338
Test name
Test status
Simulation time 50320863883 ps
CPU time 1391.62 seconds
Started Feb 18 12:38:39 PM PST 24
Finished Feb 18 01:01:52 PM PST 24
Peak memory 286940 kb
Host smart-b4f18a4d-a75f-4ae2-8d72-2e24e1e04611
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458990577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.1458990577
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.3960039215
Short name T209
Test name
Test status
Simulation time 90866190990 ps
CPU time 2572.84 seconds
Started Feb 18 12:38:39 PM PST 24
Finished Feb 18 01:21:35 PM PST 24
Peak memory 281212 kb
Host smart-fdc6ea93-63af-4c7f-bac8-d1b697ec2d38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960039215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3960039215
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.727368571
Short name T542
Test name
Test status
Simulation time 8445804031 ps
CPU time 189.1 seconds
Started Feb 18 12:38:34 PM PST 24
Finished Feb 18 12:41:46 PM PST 24
Peak memory 247044 kb
Host smart-c6817218-9a8c-414e-88e8-1c310128a611
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727368571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.727368571
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.2671652364
Short name T607
Test name
Test status
Simulation time 78547865 ps
CPU time 7.35 seconds
Started Feb 18 12:38:30 PM PST 24
Finished Feb 18 12:38:39 PM PST 24
Peak memory 248320 kb
Host smart-80594591-0d97-4090-9501-0d680703f828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26716
52364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.2671652364
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.2598166711
Short name T82
Test name
Test status
Simulation time 200046391 ps
CPU time 20.53 seconds
Started Feb 18 12:38:24 PM PST 24
Finished Feb 18 12:38:47 PM PST 24
Peak memory 255136 kb
Host smart-ab240616-810e-4341-8a97-db89e0897266
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25981
66711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.2598166711
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.2128863162
Short name T29
Test name
Test status
Simulation time 948111542 ps
CPU time 25.43 seconds
Started Feb 18 12:38:43 PM PST 24
Finished Feb 18 12:39:12 PM PST 24
Peak memory 276952 kb
Host smart-165da814-bbb6-417d-bc5f-2ae0c9fa0d62
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2128863162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.2128863162
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.3033537631
Short name T266
Test name
Test status
Simulation time 778284375 ps
CPU time 49.07 seconds
Started Feb 18 12:38:48 PM PST 24
Finished Feb 18 12:39:40 PM PST 24
Peak memory 254932 kb
Host smart-2110326f-ed9c-4ce8-a153-f30588127c78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30335
37631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.3033537631
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.553737670
Short name T588
Test name
Test status
Simulation time 186165221 ps
CPU time 10.82 seconds
Started Feb 18 12:38:17 PM PST 24
Finished Feb 18 12:38:34 PM PST 24
Peak memory 248372 kb
Host smart-1f01bd4f-6779-4bc7-9ef0-907da5e1b8e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55373
7670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.553737670
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.1972891128
Short name T471
Test name
Test status
Simulation time 261357382329 ps
CPU time 3266.62 seconds
Started Feb 18 12:38:18 PM PST 24
Finished Feb 18 01:32:51 PM PST 24
Peak memory 288540 kb
Host smart-bcdf0a10-bc53-4a82-80be-e3c2eb5e8bbe
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972891128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.1972891128
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.1995305681
Short name T218
Test name
Test status
Simulation time 106395269 ps
CPU time 2.78 seconds
Started Feb 18 12:38:53 PM PST 24
Finished Feb 18 12:38:59 PM PST 24
Peak memory 248648 kb
Host smart-7ca0321f-b2f7-4933-9c2e-c79cf8263154
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1995305681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.1995305681
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.2967300544
Short name T652
Test name
Test status
Simulation time 88084216105 ps
CPU time 2519.21 seconds
Started Feb 18 12:39:03 PM PST 24
Finished Feb 18 01:21:07 PM PST 24
Peak memory 283512 kb
Host smart-4ba1d6f8-a219-4fef-9173-b4ff3f6bee25
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967300544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.2967300544
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.3801378051
Short name T70
Test name
Test status
Simulation time 1726479166 ps
CPU time 20.19 seconds
Started Feb 18 12:38:44 PM PST 24
Finished Feb 18 12:39:07 PM PST 24
Peak memory 240084 kb
Host smart-db2f5c07-3754-4c2b-8857-d51fb978319a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3801378051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.3801378051
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.2798467843
Short name T516
Test name
Test status
Simulation time 659242334 ps
CPU time 57.27 seconds
Started Feb 18 12:39:06 PM PST 24
Finished Feb 18 12:40:11 PM PST 24
Peak memory 255712 kb
Host smart-b114a63f-88f1-4b79-be2d-f1d9698f7ad0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27984
67843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2798467843
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.3296863282
Short name T432
Test name
Test status
Simulation time 811770944 ps
CPU time 45.26 seconds
Started Feb 18 12:38:51 PM PST 24
Finished Feb 18 12:39:44 PM PST 24
Peak memory 253916 kb
Host smart-263fc97b-fb54-4a7c-920f-ad785ad51224
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32968
63282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.3296863282
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.517517462
Short name T629
Test name
Test status
Simulation time 12660498698 ps
CPU time 1358.99 seconds
Started Feb 18 12:38:56 PM PST 24
Finished Feb 18 01:01:39 PM PST 24
Peak memory 286784 kb
Host smart-2871688f-9511-437a-b2f1-25c7bfe95705
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517517462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.517517462
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.3169587665
Short name T626
Test name
Test status
Simulation time 29797166009 ps
CPU time 618.45 seconds
Started Feb 18 12:39:11 PM PST 24
Finished Feb 18 12:49:37 PM PST 24
Peak memory 247308 kb
Host smart-09f276ef-fbb5-4050-800f-e8164b26a4e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169587665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3169587665
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.2062251740
Short name T530
Test name
Test status
Simulation time 2648616481 ps
CPU time 77.43 seconds
Started Feb 18 12:38:52 PM PST 24
Finished Feb 18 12:40:12 PM PST 24
Peak memory 255692 kb
Host smart-30112203-7a88-459a-89f2-70bb41648a98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20622
51740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.2062251740
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.1757521395
Short name T501
Test name
Test status
Simulation time 648398838 ps
CPU time 11.93 seconds
Started Feb 18 12:38:45 PM PST 24
Finished Feb 18 12:39:01 PM PST 24
Peak memory 254260 kb
Host smart-c9c166f9-a9eb-412b-8a7d-a2377041cbbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17575
21395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.1757521395
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.1737988392
Short name T503
Test name
Test status
Simulation time 1365310062 ps
CPU time 23.85 seconds
Started Feb 18 12:38:53 PM PST 24
Finished Feb 18 12:39:20 PM PST 24
Peak memory 255060 kb
Host smart-eb922041-6246-4c37-b7eb-1bca693e3d6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17379
88392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.1737988392
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.1262175072
Short name T371
Test name
Test status
Simulation time 1387434602 ps
CPU time 31.22 seconds
Started Feb 18 12:38:46 PM PST 24
Finished Feb 18 12:39:21 PM PST 24
Peak memory 248324 kb
Host smart-b6e237fc-1d2b-44fc-be3e-2ad4acfbdf77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12621
75072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.1262175072
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.1217545486
Short name T537
Test name
Test status
Simulation time 123538593273 ps
CPU time 1035.06 seconds
Started Feb 18 12:39:08 PM PST 24
Finished Feb 18 12:56:31 PM PST 24
Peak memory 281260 kb
Host smart-49076f48-cdd3-408b-9eef-5b74021b382f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217545486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.1217545486
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.1339325277
Short name T576
Test name
Test status
Simulation time 73216729610 ps
CPU time 1139.79 seconds
Started Feb 18 12:39:07 PM PST 24
Finished Feb 18 12:58:14 PM PST 24
Peak memory 264664 kb
Host smart-813d09b9-b526-40c5-b763-25ce2589cda8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339325277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.1339325277
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.2065997400
Short name T575
Test name
Test status
Simulation time 1656899247 ps
CPU time 10.55 seconds
Started Feb 18 12:38:54 PM PST 24
Finished Feb 18 12:39:08 PM PST 24
Peak memory 240096 kb
Host smart-54fa7bb5-6c42-4bbd-8757-72cd2251f77c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2065997400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.2065997400
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.20371926
Short name T625
Test name
Test status
Simulation time 18120368258 ps
CPU time 104.05 seconds
Started Feb 18 12:38:41 PM PST 24
Finished Feb 18 12:40:26 PM PST 24
Peak memory 247636 kb
Host smart-62aeb581-375e-4d68-9eec-b48382ff03ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20371
926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.20371926
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.1432414230
Short name T670
Test name
Test status
Simulation time 322903827 ps
CPU time 16.26 seconds
Started Feb 18 12:38:47 PM PST 24
Finished Feb 18 12:39:07 PM PST 24
Peak memory 250716 kb
Host smart-841777b8-f925-45dc-8166-1b47b179794c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14324
14230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.1432414230
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1069395778
Short name T296
Test name
Test status
Simulation time 58551678303 ps
CPU time 1122.13 seconds
Started Feb 18 12:38:39 PM PST 24
Finished Feb 18 12:57:30 PM PST 24
Peak memory 272940 kb
Host smart-65831313-7d95-450c-9de1-5b6903751af7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069395778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1069395778
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.2232612896
Short name T593
Test name
Test status
Simulation time 13048607736 ps
CPU time 1277.27 seconds
Started Feb 18 12:38:46 PM PST 24
Finished Feb 18 01:00:07 PM PST 24
Peak memory 288468 kb
Host smart-7669efdb-9d7e-44e7-be4b-07aa607278f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232612896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.2232612896
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.4230729436
Short name T496
Test name
Test status
Simulation time 715935283 ps
CPU time 25.18 seconds
Started Feb 18 12:38:55 PM PST 24
Finished Feb 18 12:39:24 PM PST 24
Peak memory 255364 kb
Host smart-b214d499-f6fc-4558-b041-30568deb4324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42307
29436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.4230729436
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.1060197923
Short name T638
Test name
Test status
Simulation time 3387589013 ps
CPU time 52.98 seconds
Started Feb 18 12:38:51 PM PST 24
Finished Feb 18 12:39:47 PM PST 24
Peak memory 254948 kb
Host smart-285e5e71-bcd5-4e17-bd3f-554b2bbd09c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10601
97923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.1060197923
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.2275549414
Short name T446
Test name
Test status
Simulation time 4101238703 ps
CPU time 34.08 seconds
Started Feb 18 12:38:49 PM PST 24
Finished Feb 18 12:39:26 PM PST 24
Peak memory 248372 kb
Host smart-abeafd15-3f63-4a94-8505-cc82c41344e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22755
49414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.2275549414
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.3833717247
Short name T541
Test name
Test status
Simulation time 156098668 ps
CPU time 7.21 seconds
Started Feb 18 12:39:11 PM PST 24
Finished Feb 18 12:39:26 PM PST 24
Peak memory 250088 kb
Host smart-05432680-9de0-415b-88c9-ad66f5206ca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38337
17247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.3833717247
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.1925481779
Short name T52
Test name
Test status
Simulation time 33490336129 ps
CPU time 1605.47 seconds
Started Feb 18 12:39:09 PM PST 24
Finished Feb 18 01:06:01 PM PST 24
Peak memory 297940 kb
Host smart-0640386d-f93b-4c9b-9038-aaac5006ae1f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925481779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.1925481779
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.2153164480
Short name T215
Test name
Test status
Simulation time 54038274 ps
CPU time 4.45 seconds
Started Feb 18 12:38:55 PM PST 24
Finished Feb 18 12:39:03 PM PST 24
Peak memory 248648 kb
Host smart-a809fba7-30dc-4a46-ae6f-fd748878def9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2153164480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.2153164480
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.2140830598
Short name T375
Test name
Test status
Simulation time 18185193033 ps
CPU time 862.59 seconds
Started Feb 18 12:39:00 PM PST 24
Finished Feb 18 12:53:26 PM PST 24
Peak memory 268980 kb
Host smart-360cef03-09e4-4000-b143-8d556ad46f74
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140830598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.2140830598
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.2146846792
Short name T498
Test name
Test status
Simulation time 1831051287 ps
CPU time 22.27 seconds
Started Feb 18 12:38:57 PM PST 24
Finished Feb 18 12:39:23 PM PST 24
Peak memory 240096 kb
Host smart-948866eb-5552-435b-b247-a9e1c87347cc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2146846792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.2146846792
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.1405663283
Short name T577
Test name
Test status
Simulation time 9674274566 ps
CPU time 150.17 seconds
Started Feb 18 12:38:37 PM PST 24
Finished Feb 18 12:41:09 PM PST 24
Peak memory 255656 kb
Host smart-17cb43ae-9963-4c7b-a91c-a2c04d06d39e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14056
63283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.1405663283
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.1929233996
Short name T77
Test name
Test status
Simulation time 656324660 ps
CPU time 25.66 seconds
Started Feb 18 12:39:05 PM PST 24
Finished Feb 18 12:39:36 PM PST 24
Peak memory 254196 kb
Host smart-6b29690d-20c1-4242-819f-ae97e4a3a888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19292
33996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.1929233996
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.972800375
Short name T675
Test name
Test status
Simulation time 37961926542 ps
CPU time 1031.39 seconds
Started Feb 18 12:39:10 PM PST 24
Finished Feb 18 12:56:28 PM PST 24
Peak memory 272680 kb
Host smart-cc58714a-5914-4b04-940c-106e2146272a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972800375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.972800375
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.4043679925
Short name T201
Test name
Test status
Simulation time 4719993147 ps
CPU time 531.81 seconds
Started Feb 18 12:39:11 PM PST 24
Finished Feb 18 12:48:11 PM PST 24
Peak memory 264852 kb
Host smart-3e279e77-7904-4a83-8c67-5d9f850e3593
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043679925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.4043679925
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.1606470038
Short name T505
Test name
Test status
Simulation time 11605208081 ps
CPU time 248.4 seconds
Started Feb 18 12:38:51 PM PST 24
Finished Feb 18 12:43:02 PM PST 24
Peak memory 246228 kb
Host smart-69ab06e7-60ae-4dea-9508-ecc721b76199
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606470038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.1606470038
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.1512375825
Short name T513
Test name
Test status
Simulation time 630036262 ps
CPU time 9.71 seconds
Started Feb 18 12:38:44 PM PST 24
Finished Feb 18 12:38:58 PM PST 24
Peak memory 248332 kb
Host smart-f0f22fed-927d-481c-8ae4-1ed634fe1acc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15123
75825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.1512375825
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.1565059347
Short name T240
Test name
Test status
Simulation time 2417547628 ps
CPU time 37.01 seconds
Started Feb 18 12:39:03 PM PST 24
Finished Feb 18 12:39:44 PM PST 24
Peak memory 255040 kb
Host smart-9577a979-14f7-4cdd-840a-0619b5b499d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15650
59347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.1565059347
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.1968791675
Short name T419
Test name
Test status
Simulation time 86608690 ps
CPU time 10.09 seconds
Started Feb 18 12:38:47 PM PST 24
Finished Feb 18 12:39:01 PM PST 24
Peak memory 253304 kb
Host smart-47b63ae8-02dc-448c-a838-e992423a93b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19687
91675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.1968791675
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.574654269
Short name T71
Test name
Test status
Simulation time 126578630 ps
CPU time 12.8 seconds
Started Feb 18 12:38:49 PM PST 24
Finished Feb 18 12:39:05 PM PST 24
Peak memory 254140 kb
Host smart-25af578f-c3de-4d3e-b76c-dd1520dfc9d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57465
4269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.574654269
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.2684594676
Short name T263
Test name
Test status
Simulation time 23011577755 ps
CPU time 1548.47 seconds
Started Feb 18 12:38:55 PM PST 24
Finished Feb 18 01:04:47 PM PST 24
Peak memory 268308 kb
Host smart-5080e2bc-5741-4141-960c-0d7fab8bc0dc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684594676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.2684594676
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.1938317066
Short name T198
Test name
Test status
Simulation time 23558929961 ps
CPU time 1783.86 seconds
Started Feb 18 12:38:54 PM PST 24
Finished Feb 18 01:08:41 PM PST 24
Peak memory 282792 kb
Host smart-82a4427d-b893-403a-97d7-db531bcabff0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938317066 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.1938317066
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.3801492815
Short name T227
Test name
Test status
Simulation time 111974292 ps
CPU time 2.88 seconds
Started Feb 18 12:38:57 PM PST 24
Finished Feb 18 12:39:04 PM PST 24
Peak memory 248624 kb
Host smart-9d9da90d-7d5b-4fd9-ba84-baa7afab1c1f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3801492815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.3801492815
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.3288157173
Short name T500
Test name
Test status
Simulation time 760047340 ps
CPU time 10.96 seconds
Started Feb 18 12:38:54 PM PST 24
Finished Feb 18 12:39:08 PM PST 24
Peak memory 240112 kb
Host smart-c2b01149-ab52-43e6-8693-8351b06456c9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3288157173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3288157173
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.1122288361
Short name T611
Test name
Test status
Simulation time 419516482 ps
CPU time 19.48 seconds
Started Feb 18 12:39:06 PM PST 24
Finished Feb 18 12:39:38 PM PST 24
Peak memory 255292 kb
Host smart-03ef83ac-7587-4a53-b312-a99767f9597a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11222
88361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.1122288361
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.2260674353
Short name T666
Test name
Test status
Simulation time 71990625 ps
CPU time 5.31 seconds
Started Feb 18 12:39:09 PM PST 24
Finished Feb 18 12:39:22 PM PST 24
Peak memory 238412 kb
Host smart-3c69cd57-8257-4eae-97a4-3c01b19e8c30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22606
74353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.2260674353
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.608505084
Short name T298
Test name
Test status
Simulation time 47069388095 ps
CPU time 2704.9 seconds
Started Feb 18 12:39:04 PM PST 24
Finished Feb 18 01:24:15 PM PST 24
Peak memory 289136 kb
Host smart-4689cbef-acb6-4d99-9b1a-e2a7bc1f78d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608505084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.608505084
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.3487950105
Short name T265
Test name
Test status
Simulation time 171695380124 ps
CPU time 2650.59 seconds
Started Feb 18 12:39:03 PM PST 24
Finished Feb 18 01:23:18 PM PST 24
Peak memory 288800 kb
Host smart-ad79f7b7-2ae7-48a7-9972-7ca7a00201ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487950105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.3487950105
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.88629705
Short name T473
Test name
Test status
Simulation time 519322267 ps
CPU time 27.47 seconds
Started Feb 18 12:38:40 PM PST 24
Finished Feb 18 12:39:09 PM PST 24
Peak memory 248296 kb
Host smart-1fb1320d-a305-445a-80d4-9377e83dc18c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88629
705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.88629705
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.3868472330
Short name T127
Test name
Test status
Simulation time 738255612 ps
CPU time 33.62 seconds
Started Feb 18 12:38:39 PM PST 24
Finished Feb 18 12:39:15 PM PST 24
Peak memory 254592 kb
Host smart-d9728312-be75-4c36-b16a-096d20a689e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38684
72330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.3868472330
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.386869288
Short name T552
Test name
Test status
Simulation time 313416213 ps
CPU time 20.69 seconds
Started Feb 18 12:38:58 PM PST 24
Finished Feb 18 12:39:23 PM PST 24
Peak memory 256500 kb
Host smart-3f597cee-64ed-4e50-9969-c183e647d6dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38686
9288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.386869288
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.1585996080
Short name T659
Test name
Test status
Simulation time 35763334199 ps
CPU time 1058.13 seconds
Started Feb 18 12:38:55 PM PST 24
Finished Feb 18 12:56:36 PM PST 24
Peak memory 284228 kb
Host smart-16f62601-794c-40e3-9d7e-44160488d07a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585996080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.1585996080
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.1180855916
Short name T228
Test name
Test status
Simulation time 19266026 ps
CPU time 2.7 seconds
Started Feb 18 12:39:00 PM PST 24
Finished Feb 18 12:39:06 PM PST 24
Peak memory 248552 kb
Host smart-2eb0d74c-bb53-4548-a6e9-78c302187673
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1180855916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.1180855916
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.169740569
Short name T407
Test name
Test status
Simulation time 75428992956 ps
CPU time 1943.47 seconds
Started Feb 18 12:38:52 PM PST 24
Finished Feb 18 01:11:18 PM PST 24
Peak memory 282720 kb
Host smart-33337564-73b9-4f48-b661-5f32ac307f2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169740569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.169740569
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.2317882445
Short name T643
Test name
Test status
Simulation time 741234730 ps
CPU time 17.9 seconds
Started Feb 18 12:38:47 PM PST 24
Finished Feb 18 12:39:08 PM PST 24
Peak memory 240108 kb
Host smart-4d9984e5-03db-48fb-bc41-9350f2208b00
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2317882445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.2317882445
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.2830526261
Short name T581
Test name
Test status
Simulation time 4837039379 ps
CPU time 74.96 seconds
Started Feb 18 12:39:10 PM PST 24
Finished Feb 18 12:40:32 PM PST 24
Peak memory 247732 kb
Host smart-08018d11-64ab-4566-bee2-716751a6b336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28305
26261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.2830526261
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.235164708
Short name T230
Test name
Test status
Simulation time 1670447449 ps
CPU time 54.85 seconds
Started Feb 18 12:38:59 PM PST 24
Finished Feb 18 12:39:58 PM PST 24
Peak memory 254624 kb
Host smart-7b6f1fa7-d1aa-4059-bddf-41f953a59fef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23516
4708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.235164708
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.2315391727
Short name T300
Test name
Test status
Simulation time 180228352539 ps
CPU time 1450.5 seconds
Started Feb 18 12:38:54 PM PST 24
Finished Feb 18 01:03:08 PM PST 24
Peak memory 268880 kb
Host smart-7c4c06fb-93ee-448e-99a6-056d92821ade
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315391727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.2315391727
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.2004228098
Short name T421
Test name
Test status
Simulation time 57485000135 ps
CPU time 768.6 seconds
Started Feb 18 12:39:03 PM PST 24
Finished Feb 18 12:51:55 PM PST 24
Peak memory 272832 kb
Host smart-f8ccf4f8-70ce-4878-bd76-9412a55f2853
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004228098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.2004228098
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.2518302288
Short name T332
Test name
Test status
Simulation time 24074966522 ps
CPU time 157.19 seconds
Started Feb 18 12:38:57 PM PST 24
Finished Feb 18 12:41:37 PM PST 24
Peak memory 246372 kb
Host smart-9b1b62db-d5bb-4bd5-8d84-66f148e10636
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518302288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.2518302288
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.1781005602
Short name T515
Test name
Test status
Simulation time 1101785131 ps
CPU time 57.35 seconds
Started Feb 18 12:38:53 PM PST 24
Finished Feb 18 12:39:53 PM PST 24
Peak memory 248320 kb
Host smart-86b66e9f-1d1f-4521-aeb1-7c26dbf30dc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17810
05602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.1781005602
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.1172089391
Short name T488
Test name
Test status
Simulation time 1131945128 ps
CPU time 62.53 seconds
Started Feb 18 12:38:58 PM PST 24
Finished Feb 18 12:40:04 PM PST 24
Peak memory 246968 kb
Host smart-31c8f155-1a57-4ec2-b7ed-477856620e9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11720
89391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.1172089391
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.2173774310
Short name T87
Test name
Test status
Simulation time 1007899624 ps
CPU time 24.95 seconds
Started Feb 18 12:38:56 PM PST 24
Finished Feb 18 12:39:25 PM PST 24
Peak memory 254364 kb
Host smart-cac7afaf-f0a4-44e5-b3ce-629e06597e7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21737
74310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.2173774310
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.3472644526
Short name T673
Test name
Test status
Simulation time 1281581644 ps
CPU time 31.66 seconds
Started Feb 18 12:38:59 PM PST 24
Finished Feb 18 12:39:34 PM PST 24
Peak memory 248324 kb
Host smart-953b8c85-09f9-409a-bb8a-bfc66b32d555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34726
44526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.3472644526
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.2379332896
Short name T221
Test name
Test status
Simulation time 26027303 ps
CPU time 2.34 seconds
Started Feb 18 12:38:58 PM PST 24
Finished Feb 18 12:39:04 PM PST 24
Peak memory 248564 kb
Host smart-c6eb7603-ad7f-4944-867e-a5205be140a8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2379332896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.2379332896
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.266956216
Short name T642
Test name
Test status
Simulation time 27164455934 ps
CPU time 703.71 seconds
Started Feb 18 12:38:52 PM PST 24
Finished Feb 18 12:50:38 PM PST 24
Peak memory 265788 kb
Host smart-1c44aadb-015f-4c87-9e79-28dc4eadf626
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266956216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.266956216
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.3581103076
Short name T489
Test name
Test status
Simulation time 859170470 ps
CPU time 11.19 seconds
Started Feb 18 12:38:59 PM PST 24
Finished Feb 18 12:39:14 PM PST 24
Peak memory 240028 kb
Host smart-a4976b55-f666-4781-9a2f-0aff295588a3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3581103076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.3581103076
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.1439327728
Short name T402
Test name
Test status
Simulation time 5857210886 ps
CPU time 101.06 seconds
Started Feb 18 12:39:16 PM PST 24
Finished Feb 18 12:41:02 PM PST 24
Peak memory 255888 kb
Host smart-36cc43f5-6f7e-425e-bdf6-65ab41fa4532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14393
27728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.1439327728
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.3156560682
Short name T555
Test name
Test status
Simulation time 1770152632 ps
CPU time 54.6 seconds
Started Feb 18 12:38:53 PM PST 24
Finished Feb 18 12:39:51 PM PST 24
Peak memory 254604 kb
Host smart-8f35b9fd-9b2b-4ccf-a3a2-4e19f6740f19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31565
60682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.3156560682
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.2963424571
Short name T678
Test name
Test status
Simulation time 142653273954 ps
CPU time 1978.72 seconds
Started Feb 18 12:38:55 PM PST 24
Finished Feb 18 01:11:58 PM PST 24
Peak memory 272580 kb
Host smart-fc0ac740-aed8-4117-a6ec-c36ed2db09b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963424571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.2963424571
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.2529350583
Short name T573
Test name
Test status
Simulation time 38513146049 ps
CPU time 2367.16 seconds
Started Feb 18 12:38:58 PM PST 24
Finished Feb 18 01:18:29 PM PST 24
Peak memory 282760 kb
Host smart-3951706b-c99f-4d01-8459-372e6ff98b51
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529350583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.2529350583
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.2601842093
Short name T667
Test name
Test status
Simulation time 6281737387 ps
CPU time 265.86 seconds
Started Feb 18 12:38:51 PM PST 24
Finished Feb 18 12:43:20 PM PST 24
Peak memory 247384 kb
Host smart-ce4627f9-4aee-4411-8655-67ae32f124c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601842093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.2601842093
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.3036721591
Short name T32
Test name
Test status
Simulation time 1024439279 ps
CPU time 27.75 seconds
Started Feb 18 12:38:57 PM PST 24
Finished Feb 18 12:39:28 PM PST 24
Peak memory 248316 kb
Host smart-4bcd9450-1604-42f3-9673-f6cd30954df7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30367
21591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.3036721591
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.3369232241
Short name T238
Test name
Test status
Simulation time 285815450 ps
CPU time 14.37 seconds
Started Feb 18 12:38:57 PM PST 24
Finished Feb 18 12:39:15 PM PST 24
Peak memory 248424 kb
Host smart-ef6fb928-3403-4e90-b6b2-20ae86de9f00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33692
32241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.3369232241
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.1142058845
Short name T630
Test name
Test status
Simulation time 1977003964 ps
CPU time 29.39 seconds
Started Feb 18 12:39:07 PM PST 24
Finished Feb 18 12:39:44 PM PST 24
Peak memory 253980 kb
Host smart-2ef199ce-0380-4d8f-8d81-9e7cc0f6f9e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11420
58845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.1142058845
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.1513104886
Short name T508
Test name
Test status
Simulation time 7735609910 ps
CPU time 44.28 seconds
Started Feb 18 12:38:46 PM PST 24
Finished Feb 18 12:39:34 PM PST 24
Peak memory 248380 kb
Host smart-b97b84ab-2f71-4e65-b39b-a6c84d4e9967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15131
04886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.1513104886
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.3670173829
Short name T640
Test name
Test status
Simulation time 510161767 ps
CPU time 44.53 seconds
Started Feb 18 12:38:57 PM PST 24
Finished Feb 18 12:39:45 PM PST 24
Peak memory 255888 kb
Host smart-b3eb90d8-ba09-4620-ac6f-fce6ebcb4e5a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670173829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.3670173829
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.3276452005
Short name T222
Test name
Test status
Simulation time 59480647 ps
CPU time 2.27 seconds
Started Feb 18 12:38:55 PM PST 24
Finished Feb 18 12:39:00 PM PST 24
Peak memory 248524 kb
Host smart-f66cedd1-2da0-48e6-a022-1ad8b1a1a124
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3276452005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.3276452005
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.977378238
Short name T697
Test name
Test status
Simulation time 250175134034 ps
CPU time 1695.03 seconds
Started Feb 18 12:38:41 PM PST 24
Finished Feb 18 01:06:59 PM PST 24
Peak memory 272224 kb
Host smart-667a0d4c-53c9-4e33-8790-88060c3e48be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977378238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.977378238
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.3303632852
Short name T239
Test name
Test status
Simulation time 336231258 ps
CPU time 17.47 seconds
Started Feb 18 12:38:58 PM PST 24
Finished Feb 18 12:39:19 PM PST 24
Peak memory 248304 kb
Host smart-eb2dfba6-e74a-4f1f-96fd-795f4facf3b8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3303632852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.3303632852
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.1373004592
Short name T604
Test name
Test status
Simulation time 1619803919 ps
CPU time 23.9 seconds
Started Feb 18 12:38:52 PM PST 24
Finished Feb 18 12:39:18 PM PST 24
Peak memory 247928 kb
Host smart-b0750496-98a5-4e07-bbe0-4adf5fd3d1f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13730
04592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.1373004592
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.3514052947
Short name T8
Test name
Test status
Simulation time 4138701182 ps
CPU time 31.1 seconds
Started Feb 18 12:38:53 PM PST 24
Finished Feb 18 12:39:27 PM PST 24
Peak memory 253924 kb
Host smart-1e192d8b-887a-48c4-8c4d-f9591e46dd6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35140
52947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.3514052947
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.365913282
Short name T339
Test name
Test status
Simulation time 14127512760 ps
CPU time 1230.51 seconds
Started Feb 18 12:38:54 PM PST 24
Finished Feb 18 12:59:28 PM PST 24
Peak memory 287748 kb
Host smart-17cd59a2-8c4c-47e2-a85f-6f39a3f8cae2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365913282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.365913282
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.215540353
Short name T123
Test name
Test status
Simulation time 35833588339 ps
CPU time 1594.57 seconds
Started Feb 18 12:38:58 PM PST 24
Finished Feb 18 01:05:37 PM PST 24
Peak memory 288944 kb
Host smart-284aad14-f32e-457d-9456-d1f1ed6eb35a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215540353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.215540353
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.3782347467
Short name T418
Test name
Test status
Simulation time 9860400621 ps
CPU time 109.07 seconds
Started Feb 18 12:39:03 PM PST 24
Finished Feb 18 12:40:55 PM PST 24
Peak memory 246244 kb
Host smart-7966be89-59bd-48b0-a8ba-bc4b35bed4aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782347467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3782347467
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.2450316783
Short name T591
Test name
Test status
Simulation time 1371877252 ps
CPU time 39.6 seconds
Started Feb 18 12:38:58 PM PST 24
Finished Feb 18 12:39:41 PM PST 24
Peak memory 255304 kb
Host smart-41675086-de61-403b-9346-a75d19971279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24503
16783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.2450316783
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.1333277631
Short name T51
Test name
Test status
Simulation time 944148115 ps
CPU time 58.26 seconds
Started Feb 18 12:38:59 PM PST 24
Finished Feb 18 12:40:00 PM PST 24
Peak memory 253928 kb
Host smart-91aff79e-5f5e-4698-91ed-fb335d307f30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13332
77631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.1333277631
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.2500795664
Short name T413
Test name
Test status
Simulation time 1109586488 ps
CPU time 67.65 seconds
Started Feb 18 12:39:03 PM PST 24
Finished Feb 18 12:40:14 PM PST 24
Peak memory 255580 kb
Host smart-f5ae003c-d8a8-4e87-babf-27c994f2f53f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25007
95664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.2500795664
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.3998471993
Short name T396
Test name
Test status
Simulation time 401010354 ps
CPU time 32.47 seconds
Started Feb 18 12:38:59 PM PST 24
Finished Feb 18 12:39:35 PM PST 24
Peak memory 248336 kb
Host smart-d4158dbd-220a-4cc9-89b7-a162802ab51c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39984
71993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.3998471993
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.1672932245
Short name T271
Test name
Test status
Simulation time 62634003342 ps
CPU time 2003.34 seconds
Started Feb 18 12:38:57 PM PST 24
Finished Feb 18 01:12:24 PM PST 24
Peak memory 289288 kb
Host smart-246e2d9e-7796-403c-a4f1-8933053c29a0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672932245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.1672932245
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.1959660636
Short name T129
Test name
Test status
Simulation time 183057837764 ps
CPU time 6867.12 seconds
Started Feb 18 12:38:55 PM PST 24
Finished Feb 18 02:33:26 PM PST 24
Peak memory 354336 kb
Host smart-226ed135-d7be-478f-9b2b-2141313cc90b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959660636 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.1959660636
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.2440592492
Short name T214
Test name
Test status
Simulation time 43650350 ps
CPU time 2.29 seconds
Started Feb 18 12:39:05 PM PST 24
Finished Feb 18 12:39:13 PM PST 24
Peak memory 248652 kb
Host smart-5acc0cc2-b9f1-4126-9970-d1e7163a1da3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2440592492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.2440592492
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.2458935707
Short name T600
Test name
Test status
Simulation time 104405667508 ps
CPU time 1576.56 seconds
Started Feb 18 12:38:56 PM PST 24
Finished Feb 18 01:05:16 PM PST 24
Peak memory 272512 kb
Host smart-d75eaa39-ebf2-493e-aa39-8816583c442e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458935707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.2458935707
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.3635036818
Short name T210
Test name
Test status
Simulation time 733630702 ps
CPU time 30.02 seconds
Started Feb 18 12:38:54 PM PST 24
Finished Feb 18 12:39:27 PM PST 24
Peak memory 240104 kb
Host smart-ba54340d-ad10-40e7-af45-2d510569d180
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3635036818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.3635036818
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.503112658
Short name T641
Test name
Test status
Simulation time 638199071 ps
CPU time 47.93 seconds
Started Feb 18 12:39:00 PM PST 24
Finished Feb 18 12:39:51 PM PST 24
Peak memory 255604 kb
Host smart-4707a5e7-6b2a-4e5c-a4b6-943b4393ab55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50311
2658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.503112658
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.4073634147
Short name T429
Test name
Test status
Simulation time 972381949 ps
CPU time 31.14 seconds
Started Feb 18 12:39:03 PM PST 24
Finished Feb 18 12:39:37 PM PST 24
Peak memory 254760 kb
Host smart-c66167d0-6747-4468-b26a-794542f1d893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40736
34147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.4073634147
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.2951305125
Short name T435
Test name
Test status
Simulation time 15816343855 ps
CPU time 1436.74 seconds
Started Feb 18 12:39:12 PM PST 24
Finished Feb 18 01:03:16 PM PST 24
Peak memory 288592 kb
Host smart-1acac24b-e393-4a27-98bb-4bebca63f956
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951305125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.2951305125
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.2644345647
Short name T676
Test name
Test status
Simulation time 4919769708 ps
CPU time 113.83 seconds
Started Feb 18 12:38:59 PM PST 24
Finished Feb 18 12:40:56 PM PST 24
Peak memory 246052 kb
Host smart-3c8f3714-7372-4dbb-8ae2-761e774567c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644345647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.2644345647
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.247194721
Short name T679
Test name
Test status
Simulation time 179778208 ps
CPU time 5.65 seconds
Started Feb 18 12:39:10 PM PST 24
Finished Feb 18 12:39:23 PM PST 24
Peak memory 248332 kb
Host smart-24e70166-18bd-443b-a571-f7bd8b7c7b07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24719
4721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.247194721
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.2066772318
Short name T689
Test name
Test status
Simulation time 177445311 ps
CPU time 4.84 seconds
Started Feb 18 12:38:58 PM PST 24
Finished Feb 18 12:39:06 PM PST 24
Peak memory 238364 kb
Host smart-7ecd0c54-71a6-42c4-807a-948f8b9507de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20667
72318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.2066772318
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.307493291
Short name T334
Test name
Test status
Simulation time 388589087 ps
CPU time 21.54 seconds
Started Feb 18 12:39:10 PM PST 24
Finished Feb 18 12:39:39 PM PST 24
Peak memory 254204 kb
Host smart-d79e6fd0-4c93-4812-af4e-125419c7113a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30749
3291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.307493291
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.318585137
Short name T527
Test name
Test status
Simulation time 1015338597 ps
CPU time 37.23 seconds
Started Feb 18 12:39:02 PM PST 24
Finished Feb 18 12:39:42 PM PST 24
Peak memory 255012 kb
Host smart-42a5817a-ac0b-4dd1-9837-efd3bdcbf5dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31858
5137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.318585137
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.236136196
Short name T93
Test name
Test status
Simulation time 79627930292 ps
CPU time 880.08 seconds
Started Feb 18 12:38:58 PM PST 24
Finished Feb 18 12:53:42 PM PST 24
Peak memory 272968 kb
Host smart-76815488-b58a-417c-a15d-30c2b610f5f0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236136196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_han
dler_stress_all.236136196
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.1714403331
Short name T111
Test name
Test status
Simulation time 81019753383 ps
CPU time 7908.79 seconds
Started Feb 18 12:39:01 PM PST 24
Finished Feb 18 02:50:53 PM PST 24
Peak memory 353464 kb
Host smart-f1f06303-0020-47d9-8c36-d6d88bcc545b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714403331 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.1714403331
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.2174705872
Short name T200
Test name
Test status
Simulation time 101506793305 ps
CPU time 1451.82 seconds
Started Feb 18 12:39:00 PM PST 24
Finished Feb 18 01:03:15 PM PST 24
Peak memory 272864 kb
Host smart-f3ff48f0-fe85-45a3-b8f0-f7cf8bd7b395
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174705872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.2174705872
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.2729062200
Short name T372
Test name
Test status
Simulation time 16314176325 ps
CPU time 33.27 seconds
Started Feb 18 12:38:56 PM PST 24
Finished Feb 18 12:39:33 PM PST 24
Peak memory 240208 kb
Host smart-b6016c90-3d89-445c-8acc-527a4c365c81
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2729062200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.2729062200
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.1068704282
Short name T60
Test name
Test status
Simulation time 5744563369 ps
CPU time 121.77 seconds
Started Feb 18 12:39:04 PM PST 24
Finished Feb 18 12:41:11 PM PST 24
Peak memory 256640 kb
Host smart-cd553598-2a45-4662-b343-5c867975d729
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10687
04282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.1068704282
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.2183341846
Short name T466
Test name
Test status
Simulation time 179769729 ps
CPU time 9.1 seconds
Started Feb 18 12:38:59 PM PST 24
Finished Feb 18 12:39:12 PM PST 24
Peak memory 252840 kb
Host smart-a5f6c676-bd33-427e-b673-c611e4297fe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21833
41846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.2183341846
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.3812483714
Short name T244
Test name
Test status
Simulation time 10952339998 ps
CPU time 815.77 seconds
Started Feb 18 12:38:58 PM PST 24
Finished Feb 18 12:52:37 PM PST 24
Peak memory 272356 kb
Host smart-05b4ab00-1fdb-4c8d-a53b-52de62f86225
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812483714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.3812483714
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.2993028565
Short name T382
Test name
Test status
Simulation time 36516751497 ps
CPU time 2171.52 seconds
Started Feb 18 12:38:53 PM PST 24
Finished Feb 18 01:15:08 PM PST 24
Peak memory 287264 kb
Host smart-222e4d0d-f9af-47a0-aa2d-2c619bb2b971
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993028565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.2993028565
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.896543747
Short name T522
Test name
Test status
Simulation time 166419077 ps
CPU time 12.3 seconds
Started Feb 18 12:38:46 PM PST 24
Finished Feb 18 12:39:02 PM PST 24
Peak memory 252044 kb
Host smart-ae560ee8-17e9-4666-8e2a-9040b83a6698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89654
3747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.896543747
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.299809177
Short name T57
Test name
Test status
Simulation time 1262399758 ps
CPU time 33.37 seconds
Started Feb 18 12:39:00 PM PST 24
Finished Feb 18 12:39:37 PM PST 24
Peak memory 247648 kb
Host smart-8f742b45-55a7-4ab0-ae45-f7b674ee50be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29980
9177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.299809177
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.4118778431
Short name T119
Test name
Test status
Simulation time 377712466 ps
CPU time 23.78 seconds
Started Feb 18 12:39:01 PM PST 24
Finished Feb 18 12:39:27 PM PST 24
Peak memory 246408 kb
Host smart-9466db60-16bd-4eff-acec-b8ea4af7de8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41187
78431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.4118778431
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.2975042974
Short name T401
Test name
Test status
Simulation time 1850339069 ps
CPU time 65.06 seconds
Started Feb 18 12:38:52 PM PST 24
Finished Feb 18 12:40:00 PM PST 24
Peak memory 256380 kb
Host smart-4304f80a-09b1-4a9a-8371-702953f13062
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29750
42974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.2975042974
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.1384926500
Short name T131
Test name
Test status
Simulation time 5069651846 ps
CPU time 369.16 seconds
Started Feb 18 12:39:04 PM PST 24
Finished Feb 18 12:45:19 PM PST 24
Peak memory 264880 kb
Host smart-af2d0774-1030-4502-9d49-7629630fd52d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384926500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.1384926500
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.3272911870
Short name T650
Test name
Test status
Simulation time 40548733526 ps
CPU time 3937.92 seconds
Started Feb 18 12:39:09 PM PST 24
Finished Feb 18 01:44:54 PM PST 24
Peak memory 337556 kb
Host smart-dec9010b-5c63-4547-9718-02d091a94f54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272911870 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.3272911870
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.1202569811
Short name T101
Test name
Test status
Simulation time 12788258 ps
CPU time 2.3 seconds
Started Feb 18 12:38:54 PM PST 24
Finished Feb 18 12:38:59 PM PST 24
Peak memory 248520 kb
Host smart-d889deba-92d0-4b81-a09c-e71f44dba591
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1202569811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.1202569811
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.3595925915
Short name T529
Test name
Test status
Simulation time 57941438789 ps
CPU time 1126.34 seconds
Started Feb 18 12:39:10 PM PST 24
Finished Feb 18 12:58:04 PM PST 24
Peak memory 285080 kb
Host smart-654781bd-e04b-48c3-ab70-9be85fed84e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595925915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.3595925915
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.635454351
Short name T481
Test name
Test status
Simulation time 272512765 ps
CPU time 12.68 seconds
Started Feb 18 12:39:11 PM PST 24
Finished Feb 18 12:39:31 PM PST 24
Peak memory 240124 kb
Host smart-ae1a9594-7a6c-4c9f-8350-3a3f6d2a9cec
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=635454351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.635454351
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.1367929343
Short name T590
Test name
Test status
Simulation time 598713977 ps
CPU time 19.08 seconds
Started Feb 18 12:39:06 PM PST 24
Finished Feb 18 12:39:33 PM PST 24
Peak memory 256016 kb
Host smart-e8519c22-f27d-46b7-9721-c583a273224f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13679
29343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.1367929343
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.1617143575
Short name T7
Test name
Test status
Simulation time 1221759220 ps
CPU time 33.83 seconds
Started Feb 18 12:39:13 PM PST 24
Finished Feb 18 12:39:53 PM PST 24
Peak memory 254604 kb
Host smart-fe7c7d01-0f1c-4ad6-a214-5d88d36fe287
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16171
43575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.1617143575
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.3404786686
Short name T597
Test name
Test status
Simulation time 111335442666 ps
CPU time 1588.63 seconds
Started Feb 18 12:38:57 PM PST 24
Finished Feb 18 01:05:29 PM PST 24
Peak memory 272084 kb
Host smart-21f58e42-47d3-41f0-82a8-fd1c96fe8964
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404786686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.3404786686
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.576669170
Short name T258
Test name
Test status
Simulation time 128805682392 ps
CPU time 1910.84 seconds
Started Feb 18 12:39:13 PM PST 24
Finished Feb 18 01:11:10 PM PST 24
Peak memory 272052 kb
Host smart-c432d490-18b7-4076-bd22-065f107b37c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576669170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.576669170
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.1239149997
Short name T305
Test name
Test status
Simulation time 9796813513 ps
CPU time 380.93 seconds
Started Feb 18 12:39:10 PM PST 24
Finished Feb 18 12:45:38 PM PST 24
Peak memory 254532 kb
Host smart-a45afdfb-3a4a-4a54-8b3c-246cbb3d5883
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239149997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.1239149997
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.1517854036
Short name T100
Test name
Test status
Simulation time 828256670 ps
CPU time 12.89 seconds
Started Feb 18 12:39:04 PM PST 24
Finished Feb 18 12:39:23 PM PST 24
Peak memory 256500 kb
Host smart-00dc0d58-cb0f-4ee7-9a98-cc7557ab921e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15178
54036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.1517854036
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.1080833627
Short name T65
Test name
Test status
Simulation time 330911307 ps
CPU time 19.17 seconds
Started Feb 18 12:39:00 PM PST 24
Finished Feb 18 12:39:22 PM PST 24
Peak memory 252588 kb
Host smart-eef38119-ca8f-4c24-95b1-d896d4a1cb1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10808
33627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.1080833627
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.1674144089
Short name T91
Test name
Test status
Simulation time 129365419 ps
CPU time 11 seconds
Started Feb 18 12:39:03 PM PST 24
Finished Feb 18 12:39:19 PM PST 24
Peak memory 248320 kb
Host smart-1eebd057-1927-4a59-a456-90d23bbf727c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16741
44089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.1674144089
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.3297516458
Short name T445
Test name
Test status
Simulation time 1893686321 ps
CPU time 30.35 seconds
Started Feb 18 12:38:54 PM PST 24
Finished Feb 18 12:39:28 PM PST 24
Peak memory 248224 kb
Host smart-7ed93d92-a159-4185-bd76-89352d704f1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32975
16458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.3297516458
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.2243046912
Short name T512
Test name
Test status
Simulation time 17518431329 ps
CPU time 1848.91 seconds
Started Feb 18 12:39:04 PM PST 24
Finished Feb 18 01:09:59 PM PST 24
Peak memory 298024 kb
Host smart-05149e9c-1fea-43ef-9d89-d214a99338c9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243046912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.2243046912
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.3530332104
Short name T219
Test name
Test status
Simulation time 106353897 ps
CPU time 3.11 seconds
Started Feb 18 12:38:19 PM PST 24
Finished Feb 18 12:38:29 PM PST 24
Peak memory 248564 kb
Host smart-33c04028-bbb3-4693-b29a-104d2e93350a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3530332104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.3530332104
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.3695612290
Short name T4
Test name
Test status
Simulation time 522047801496 ps
CPU time 2011.56 seconds
Started Feb 18 12:38:35 PM PST 24
Finished Feb 18 01:12:09 PM PST 24
Peak memory 272960 kb
Host smart-92efec83-e3c4-4c2c-beb4-1e2058238960
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695612290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.3695612290
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.2718986474
Short name T478
Test name
Test status
Simulation time 1807792474 ps
CPU time 20.64 seconds
Started Feb 18 12:38:35 PM PST 24
Finished Feb 18 12:38:58 PM PST 24
Peak memory 248184 kb
Host smart-aaa2f2e8-ff93-48f2-970a-2ec01bd97639
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2718986474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.2718986474
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.1827643697
Short name T603
Test name
Test status
Simulation time 5177028020 ps
CPU time 45.61 seconds
Started Feb 18 12:38:36 PM PST 24
Finished Feb 18 12:39:24 PM PST 24
Peak memory 254364 kb
Host smart-1762e520-3cae-4fe8-92e6-e0aa8747900e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18276
43697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.1827643697
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.2012318397
Short name T81
Test name
Test status
Simulation time 199127952 ps
CPU time 14.86 seconds
Started Feb 18 12:38:47 PM PST 24
Finished Feb 18 12:39:06 PM PST 24
Peak memory 247896 kb
Host smart-c60601b2-8986-4a72-9614-b761944e5e61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20123
18397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.2012318397
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.1743750354
Short name T614
Test name
Test status
Simulation time 73784592670 ps
CPU time 1665.55 seconds
Started Feb 18 12:38:33 PM PST 24
Finished Feb 18 01:06:21 PM PST 24
Peak memory 288776 kb
Host smart-231cdfaa-b9e2-4b64-8cb0-2670ffbb8e08
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743750354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.1743750354
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.1200631930
Short name T304
Test name
Test status
Simulation time 8052651328 ps
CPU time 325.55 seconds
Started Feb 18 12:38:39 PM PST 24
Finished Feb 18 12:44:07 PM PST 24
Peak memory 247052 kb
Host smart-84e9c5b9-5de5-4692-8c41-403cac3215a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200631930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.1200631930
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.353413378
Short name T511
Test name
Test status
Simulation time 1228808379 ps
CPU time 18.07 seconds
Started Feb 18 12:38:52 PM PST 24
Finished Feb 18 12:39:13 PM PST 24
Peak memory 248388 kb
Host smart-b5234db4-5348-4088-9fba-cb91c2e94a6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35341
3378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.353413378
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.237219795
Short name T506
Test name
Test status
Simulation time 610085780 ps
CPU time 14.86 seconds
Started Feb 18 12:38:41 PM PST 24
Finished Feb 18 12:38:58 PM PST 24
Peak memory 254552 kb
Host smart-41759f80-d56d-45a8-8be9-eca5d8cfbf9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23721
9795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.237219795
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.3321379661
Short name T30
Test name
Test status
Simulation time 719816690 ps
CPU time 22.22 seconds
Started Feb 18 12:38:38 PM PST 24
Finished Feb 18 12:39:01 PM PST 24
Peak memory 269156 kb
Host smart-add5fbfe-90c9-484c-8fe7-a348372a9d83
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3321379661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.3321379661
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.1112364649
Short name T92
Test name
Test status
Simulation time 681948048 ps
CPU time 37.25 seconds
Started Feb 18 12:38:24 PM PST 24
Finished Feb 18 12:39:04 PM PST 24
Peak memory 255364 kb
Host smart-2aa41509-9d9f-42a1-815d-16b91312bbbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11123
64649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.1112364649
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.3035268537
Short name T694
Test name
Test status
Simulation time 110183884 ps
CPU time 12.44 seconds
Started Feb 18 12:38:28 PM PST 24
Finished Feb 18 12:38:43 PM PST 24
Peak memory 248384 kb
Host smart-fb07319f-a30d-4bb5-9e15-736469bf0b13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30352
68537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.3035268537
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.54653309
Short name T649
Test name
Test status
Simulation time 147691223634 ps
CPU time 2290.99 seconds
Started Feb 18 12:39:08 PM PST 24
Finished Feb 18 01:17:27 PM PST 24
Peak memory 282820 kb
Host smart-895cc71c-cf24-46d4-ad1a-bf60be9b099f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54653309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.54653309
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.695818351
Short name T208
Test name
Test status
Simulation time 615724184 ps
CPU time 18.43 seconds
Started Feb 18 12:39:03 PM PST 24
Finished Feb 18 12:39:25 PM PST 24
Peak memory 254076 kb
Host smart-79617081-9495-4d97-906e-90e7cd52f690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69581
8351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.695818351
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.3802834943
Short name T476
Test name
Test status
Simulation time 1116775100 ps
CPU time 25.73 seconds
Started Feb 18 12:39:05 PM PST 24
Finished Feb 18 12:39:39 PM PST 24
Peak memory 254912 kb
Host smart-53593e09-1e68-4456-b449-625e40f5704d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38028
34943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.3802834943
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.3091245411
Short name T595
Test name
Test status
Simulation time 95261722373 ps
CPU time 2667.22 seconds
Started Feb 18 12:39:04 PM PST 24
Finished Feb 18 01:23:37 PM PST 24
Peak memory 288536 kb
Host smart-bb1b7e18-cccb-475e-984e-d9725062446d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091245411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.3091245411
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.803587480
Short name T656
Test name
Test status
Simulation time 312056815 ps
CPU time 35.27 seconds
Started Feb 18 12:39:06 PM PST 24
Finished Feb 18 12:39:49 PM PST 24
Peak memory 248308 kb
Host smart-fb754f21-8f6f-4a9d-8c2e-aca56927dec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80358
7480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.803587480
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.2902123480
Short name T122
Test name
Test status
Simulation time 1676708219 ps
CPU time 24.69 seconds
Started Feb 18 12:39:04 PM PST 24
Finished Feb 18 12:39:34 PM PST 24
Peak memory 247800 kb
Host smart-0b4660c6-a3ee-4995-a8c9-5613913be8f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29021
23480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.2902123480
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.3082086572
Short name T366
Test name
Test status
Simulation time 3196184395 ps
CPU time 18.81 seconds
Started Feb 18 12:39:14 PM PST 24
Finished Feb 18 12:39:38 PM PST 24
Peak memory 254808 kb
Host smart-056f4152-a385-4e61-a7b1-f1128a00d4bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30820
86572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.3082086572
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.2610743034
Short name T462
Test name
Test status
Simulation time 482011302 ps
CPU time 24.82 seconds
Started Feb 18 12:39:08 PM PST 24
Finished Feb 18 12:39:40 PM PST 24
Peak memory 248412 kb
Host smart-d8ea4a64-6dc0-444d-8612-b6778d2ab94d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26107
43034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.2610743034
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.2673449054
Short name T64
Test name
Test status
Simulation time 842074773 ps
CPU time 37.27 seconds
Started Feb 18 12:38:53 PM PST 24
Finished Feb 18 12:39:33 PM PST 24
Peak memory 256512 kb
Host smart-6f87c18e-4e6b-49da-b55c-317c389ba793
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673449054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.2673449054
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.3544404197
Short name T657
Test name
Test status
Simulation time 22189061326 ps
CPU time 1452.51 seconds
Started Feb 18 12:39:09 PM PST 24
Finished Feb 18 01:03:30 PM PST 24
Peak memory 272932 kb
Host smart-3b177975-34a4-4cca-a65a-bf172f651244
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544404197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.3544404197
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.1536921704
Short name T363
Test name
Test status
Simulation time 26326998564 ps
CPU time 206.21 seconds
Started Feb 18 12:39:15 PM PST 24
Finished Feb 18 12:42:46 PM PST 24
Peak memory 249408 kb
Host smart-1eeda45a-4ee5-4adc-b356-15487207c90e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15369
21704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.1536921704
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.4061979426
Short name T336
Test name
Test status
Simulation time 171742535859 ps
CPU time 2516.11 seconds
Started Feb 18 12:39:09 PM PST 24
Finished Feb 18 01:21:13 PM PST 24
Peak memory 281984 kb
Host smart-c9d27a65-c009-4cc6-91d8-22d6237ee419
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061979426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.4061979426
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.366286557
Short name T574
Test name
Test status
Simulation time 17601272204 ps
CPU time 930.3 seconds
Started Feb 18 12:39:10 PM PST 24
Finished Feb 18 12:54:48 PM PST 24
Peak memory 271828 kb
Host smart-7a1b0ae3-1095-4227-a2a4-a7939bdff5d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366286557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.366286557
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.2116195488
Short name T668
Test name
Test status
Simulation time 6965076128 ps
CPU time 279.07 seconds
Started Feb 18 12:39:15 PM PST 24
Finished Feb 18 12:43:59 PM PST 24
Peak memory 247076 kb
Host smart-c765a972-4756-4500-a3a3-cd377fc9ef79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116195488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.2116195488
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.2329065461
Short name T380
Test name
Test status
Simulation time 100439611 ps
CPU time 9.87 seconds
Started Feb 18 12:39:14 PM PST 24
Finished Feb 18 12:39:29 PM PST 24
Peak memory 254080 kb
Host smart-275ce21f-bd96-4bf4-be69-3e1a11a282d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23290
65461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.2329065461
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.1934447417
Short name T268
Test name
Test status
Simulation time 614205232 ps
CPU time 35.49 seconds
Started Feb 18 12:39:03 PM PST 24
Finished Feb 18 12:39:43 PM PST 24
Peak memory 253136 kb
Host smart-54280fb8-ee88-4142-83e3-c8b846072070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19344
47417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.1934447417
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.3285455813
Short name T474
Test name
Test status
Simulation time 1084639335 ps
CPU time 19.67 seconds
Started Feb 18 12:38:59 PM PST 24
Finished Feb 18 12:39:23 PM PST 24
Peak memory 255000 kb
Host smart-aba93b40-6d64-43b6-8c50-706cbf28ee77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32854
55813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.3285455813
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.1615275862
Short name T479
Test name
Test status
Simulation time 201127646170 ps
CPU time 2934.29 seconds
Started Feb 18 12:39:10 PM PST 24
Finished Feb 18 01:28:12 PM PST 24
Peak memory 305552 kb
Host smart-6f2fa233-091c-41a8-b524-7ea1edfc2474
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615275862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.1615275862
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.554472943
Short name T598
Test name
Test status
Simulation time 119906114632 ps
CPU time 2105.26 seconds
Started Feb 18 12:39:10 PM PST 24
Finished Feb 18 01:14:22 PM PST 24
Peak memory 288412 kb
Host smart-e097c65a-6438-471d-8831-41014040f30c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554472943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.554472943
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.3683799257
Short name T430
Test name
Test status
Simulation time 731256902 ps
CPU time 61.36 seconds
Started Feb 18 12:38:56 PM PST 24
Finished Feb 18 12:40:00 PM PST 24
Peak memory 247768 kb
Host smart-0e830f47-4c8e-4a64-a328-1c1682f4fa4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36837
99257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.3683799257
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.711748178
Short name T69
Test name
Test status
Simulation time 828005419 ps
CPU time 19.53 seconds
Started Feb 18 12:39:14 PM PST 24
Finished Feb 18 12:39:39 PM PST 24
Peak memory 254056 kb
Host smart-642572a1-3fdb-419d-92de-54d9885b7dfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71174
8178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.711748178
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.717880323
Short name T612
Test name
Test status
Simulation time 11397203864 ps
CPU time 1020.05 seconds
Started Feb 18 12:39:00 PM PST 24
Finished Feb 18 12:56:03 PM PST 24
Peak memory 272808 kb
Host smart-e836c78e-72ee-4aa2-a87a-cd3031bfe9d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717880323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.717880323
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.3439780240
Short name T483
Test name
Test status
Simulation time 141909461917 ps
CPU time 1924.67 seconds
Started Feb 18 12:39:11 PM PST 24
Finished Feb 18 01:11:24 PM PST 24
Peak memory 285892 kb
Host smart-aaaf696c-3c22-49d9-9151-9ea302e78f6b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439780240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.3439780240
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.1998255450
Short name T635
Test name
Test status
Simulation time 854215061 ps
CPU time 22.38 seconds
Started Feb 18 12:39:12 PM PST 24
Finished Feb 18 12:39:41 PM PST 24
Peak memory 248360 kb
Host smart-8006b6cf-322e-46c0-b4b7-ef5b182c660d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19982
55450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.1998255450
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.3474077207
Short name T35
Test name
Test status
Simulation time 4493664731 ps
CPU time 59.07 seconds
Started Feb 18 12:39:11 PM PST 24
Finished Feb 18 12:40:18 PM PST 24
Peak memory 254668 kb
Host smart-e4fce897-3c04-4dd9-9a1b-d930dea3ea8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34740
77207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.3474077207
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.1994803429
Short name T589
Test name
Test status
Simulation time 1584214003 ps
CPU time 25.95 seconds
Started Feb 18 12:39:03 PM PST 24
Finished Feb 18 12:39:32 PM PST 24
Peak memory 252920 kb
Host smart-ce1dd93a-b46d-404c-ad19-9698c47c40a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19948
03429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.1994803429
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.1347705813
Short name T398
Test name
Test status
Simulation time 158332395 ps
CPU time 19.31 seconds
Started Feb 18 12:39:10 PM PST 24
Finished Feb 18 12:39:37 PM PST 24
Peak memory 254940 kb
Host smart-97ad9bbf-f76f-4e6d-ba6b-8c7fec92a3c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13477
05813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.1347705813
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.157091537
Short name T367
Test name
Test status
Simulation time 7272703646 ps
CPU time 363.9 seconds
Started Feb 18 12:39:02 PM PST 24
Finished Feb 18 12:45:09 PM PST 24
Peak memory 256492 kb
Host smart-5737bd6e-06a7-423d-9456-0356a0947d13
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157091537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_han
dler_stress_all.157091537
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.1491227443
Short name T117
Test name
Test status
Simulation time 39281526840 ps
CPU time 1229.55 seconds
Started Feb 18 12:39:10 PM PST 24
Finished Feb 18 12:59:47 PM PST 24
Peak memory 286552 kb
Host smart-fa557232-8069-4543-8dc6-5d00f5ba9a71
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491227443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.1491227443
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.61432058
Short name T369
Test name
Test status
Simulation time 1291613150 ps
CPU time 124.37 seconds
Started Feb 18 12:39:04 PM PST 24
Finished Feb 18 12:41:14 PM PST 24
Peak memory 249348 kb
Host smart-2f20383b-e3fc-4980-811c-b1c9ed25b1b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61432
058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.61432058
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.3447996882
Short name T685
Test name
Test status
Simulation time 341739837 ps
CPU time 20.53 seconds
Started Feb 18 12:39:06 PM PST 24
Finished Feb 18 12:39:34 PM PST 24
Peak memory 252920 kb
Host smart-6343bbf2-eb79-41f0-a6ff-269e851fef3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34479
96882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.3447996882
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.634887396
Short name T344
Test name
Test status
Simulation time 65293376559 ps
CPU time 1835.08 seconds
Started Feb 18 12:39:10 PM PST 24
Finished Feb 18 01:09:52 PM PST 24
Peak memory 272912 kb
Host smart-9a642c04-e437-4a0e-af28-79bfd56601fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634887396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.634887396
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.3716314354
Short name T424
Test name
Test status
Simulation time 71489106783 ps
CPU time 1172.69 seconds
Started Feb 18 12:39:23 PM PST 24
Finished Feb 18 12:58:58 PM PST 24
Peak memory 288656 kb
Host smart-21f6fb6e-c142-4b70-8a7a-3ed1f9e3e5bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716314354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.3716314354
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.1794898532
Short name T475
Test name
Test status
Simulation time 740541892 ps
CPU time 4.36 seconds
Started Feb 18 12:39:13 PM PST 24
Finished Feb 18 12:39:23 PM PST 24
Peak memory 240224 kb
Host smart-330a139f-a355-4dfd-b992-a730b5346f2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17948
98532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.1794898532
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.3276736018
Short name T532
Test name
Test status
Simulation time 110333956 ps
CPU time 7.04 seconds
Started Feb 18 12:39:09 PM PST 24
Finished Feb 18 12:39:24 PM PST 24
Peak memory 250848 kb
Host smart-d66a6f13-436c-48ce-95ce-31b0031f4704
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32767
36018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.3276736018
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.913661511
Short name T585
Test name
Test status
Simulation time 547639341 ps
CPU time 29 seconds
Started Feb 18 12:39:06 PM PST 24
Finished Feb 18 12:39:43 PM PST 24
Peak memory 254772 kb
Host smart-1b27b078-5ebe-4f7f-9975-f5931d11b2dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91366
1511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.913661511
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.723823069
Short name T565
Test name
Test status
Simulation time 3068962229 ps
CPU time 48.34 seconds
Started Feb 18 12:39:26 PM PST 24
Finished Feb 18 12:40:18 PM PST 24
Peak memory 248396 kb
Host smart-7fb49afc-b29b-4e53-b294-f074c050e63e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72382
3069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.723823069
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.3302480468
Short name T439
Test name
Test status
Simulation time 168189323586 ps
CPU time 2654.45 seconds
Started Feb 18 12:39:13 PM PST 24
Finished Feb 18 01:23:34 PM PST 24
Peak memory 288192 kb
Host smart-4c1f4dcf-8b69-42f9-ae88-53cb2913f21b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302480468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.3302480468
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.3603979445
Short name T408
Test name
Test status
Simulation time 1141957323 ps
CPU time 87.8 seconds
Started Feb 18 12:39:15 PM PST 24
Finished Feb 18 12:40:48 PM PST 24
Peak memory 255932 kb
Host smart-b80844e8-bbfe-45e8-89bf-4bc619af247a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36039
79445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.3603979445
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.1011915796
Short name T433
Test name
Test status
Simulation time 342177759 ps
CPU time 10.06 seconds
Started Feb 18 12:39:08 PM PST 24
Finished Feb 18 12:39:25 PM PST 24
Peak memory 253068 kb
Host smart-e4c94fab-d053-4022-a5d7-c196b1e6ed3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10119
15796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.1011915796
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.4267863803
Short name T315
Test name
Test status
Simulation time 47804551350 ps
CPU time 2567.43 seconds
Started Feb 18 12:39:13 PM PST 24
Finished Feb 18 01:22:07 PM PST 24
Peak memory 288984 kb
Host smart-dd3e44d5-9bda-4eb3-b241-9c4d014a8ad2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267863803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.4267863803
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.3572942126
Short name T451
Test name
Test status
Simulation time 35932413469 ps
CPU time 2018.94 seconds
Started Feb 18 12:39:04 PM PST 24
Finished Feb 18 01:12:49 PM PST 24
Peak memory 272032 kb
Host smart-dc1332b3-c528-44a4-a743-cea87a7b83b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572942126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.3572942126
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.4293635769
Short name T316
Test name
Test status
Simulation time 22563296722 ps
CPU time 245.68 seconds
Started Feb 18 12:39:10 PM PST 24
Finished Feb 18 12:43:23 PM PST 24
Peak memory 246476 kb
Host smart-c9731bbb-17ad-463e-8883-33300b2f34da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293635769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.4293635769
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.313508942
Short name T526
Test name
Test status
Simulation time 333081229 ps
CPU time 30.24 seconds
Started Feb 18 12:39:11 PM PST 24
Finished Feb 18 12:39:49 PM PST 24
Peak memory 255112 kb
Host smart-9ac810b4-ff97-41de-a9ce-d06fe0a08c75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31350
8942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.313508942
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.3496114704
Short name T416
Test name
Test status
Simulation time 888183876 ps
CPU time 25.61 seconds
Started Feb 18 12:39:06 PM PST 24
Finished Feb 18 12:39:39 PM PST 24
Peak memory 254472 kb
Host smart-5e4cfe47-2a2c-4115-9bc4-303fd037c7b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34961
14704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.3496114704
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.6669048
Short name T658
Test name
Test status
Simulation time 168863393 ps
CPU time 6.26 seconds
Started Feb 18 12:39:10 PM PST 24
Finished Feb 18 12:39:23 PM PST 24
Peak memory 240236 kb
Host smart-bbc12294-a124-4b63-8ec3-33c3ba726bab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66690
48 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.6669048
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.2041506541
Short name T236
Test name
Test status
Simulation time 18811405995 ps
CPU time 593.7 seconds
Started Feb 18 12:39:04 PM PST 24
Finished Feb 18 12:49:03 PM PST 24
Peak memory 264776 kb
Host smart-33b161b3-1ac6-4617-861c-f210ac7dd413
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041506541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.2041506541
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.996715978
Short name T536
Test name
Test status
Simulation time 3112409285 ps
CPU time 93.01 seconds
Started Feb 18 12:39:06 PM PST 24
Finished Feb 18 12:40:47 PM PST 24
Peak memory 255668 kb
Host smart-9b550462-fce0-40f1-a715-e21d1bff9273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99671
5978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.996715978
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.940445651
Short name T281
Test name
Test status
Simulation time 4640919386 ps
CPU time 75.3 seconds
Started Feb 18 12:39:06 PM PST 24
Finished Feb 18 12:40:29 PM PST 24
Peak memory 248264 kb
Host smart-73e5574b-e0ce-4de6-bcd4-f6bd1d83f382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94044
5651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.940445651
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.1043311691
Short name T26
Test name
Test status
Simulation time 14544319500 ps
CPU time 1092.86 seconds
Started Feb 18 12:39:23 PM PST 24
Finished Feb 18 12:57:38 PM PST 24
Peak memory 272280 kb
Host smart-292e42bd-1722-4d81-b106-a03336d49bd2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043311691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.1043311691
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.1782042953
Short name T556
Test name
Test status
Simulation time 5074444734 ps
CPU time 667.14 seconds
Started Feb 18 12:39:02 PM PST 24
Finished Feb 18 12:50:12 PM PST 24
Peak memory 271940 kb
Host smart-a1706d97-668d-470d-9e20-61a277f691b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782042953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.1782042953
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.2236965272
Short name T331
Test name
Test status
Simulation time 7449993545 ps
CPU time 279.33 seconds
Started Feb 18 12:39:10 PM PST 24
Finished Feb 18 12:43:57 PM PST 24
Peak memory 246996 kb
Host smart-19554b7c-abc1-4a9b-8855-34e4df7cb2c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236965272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.2236965272
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.458381500
Short name T509
Test name
Test status
Simulation time 885812386 ps
CPU time 51.13 seconds
Started Feb 18 12:39:06 PM PST 24
Finished Feb 18 12:40:05 PM PST 24
Peak memory 248316 kb
Host smart-bf96d73a-9698-404d-9202-690a16746db1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45838
1500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.458381500
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.1349902868
Short name T105
Test name
Test status
Simulation time 807515266 ps
CPU time 25.01 seconds
Started Feb 18 12:39:12 PM PST 24
Finished Feb 18 12:39:44 PM PST 24
Peak memory 254724 kb
Host smart-baa19c14-7584-4048-8281-ccc1f6b59591
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13499
02868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.1349902868
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.260838100
Short name T98
Test name
Test status
Simulation time 4737269449 ps
CPU time 58.51 seconds
Started Feb 18 12:39:10 PM PST 24
Finished Feb 18 12:40:16 PM PST 24
Peak memory 256436 kb
Host smart-17ee34c4-9e3c-4f4b-8057-0645a74338aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26083
8100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.260838100
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.2789599656
Short name T97
Test name
Test status
Simulation time 130243988 ps
CPU time 4.49 seconds
Started Feb 18 12:39:07 PM PST 24
Finished Feb 18 12:39:19 PM PST 24
Peak memory 240180 kb
Host smart-3a579602-a285-4318-b867-0ddc64e05380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27895
99656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.2789599656
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.188904548
Short name T397
Test name
Test status
Simulation time 7094341236 ps
CPU time 840.99 seconds
Started Feb 18 12:39:09 PM PST 24
Finished Feb 18 12:53:18 PM PST 24
Peak memory 272612 kb
Host smart-fc065670-1459-4daa-ba3f-1c20e8c71731
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188904548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_han
dler_stress_all.188904548
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.3077971975
Short name T463
Test name
Test status
Simulation time 13399901400 ps
CPU time 963.6 seconds
Started Feb 18 12:39:08 PM PST 24
Finished Feb 18 12:55:19 PM PST 24
Peak memory 289248 kb
Host smart-a360eaed-1569-48bd-867a-34d06d14a404
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077971975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.3077971975
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.1200561553
Short name T379
Test name
Test status
Simulation time 2316431789 ps
CPU time 37.98 seconds
Started Feb 18 12:39:04 PM PST 24
Finished Feb 18 12:39:48 PM PST 24
Peak memory 255356 kb
Host smart-1f30ee02-6a40-4d2e-bdd7-5901cfcb2ba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12005
61553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.1200561553
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.3607920943
Short name T126
Test name
Test status
Simulation time 371832331 ps
CPU time 22.96 seconds
Started Feb 18 12:39:22 PM PST 24
Finished Feb 18 12:39:47 PM PST 24
Peak memory 254096 kb
Host smart-5ae605bd-cd5a-48c4-bb9e-d10125ed5db7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36079
20943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.3607920943
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.1233556573
Short name T557
Test name
Test status
Simulation time 78046433098 ps
CPU time 1669.09 seconds
Started Feb 18 12:39:25 PM PST 24
Finished Feb 18 01:07:18 PM PST 24
Peak memory 288712 kb
Host smart-0eb5ddf6-7538-4ee1-ad94-6719e82d126c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233556573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.1233556573
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.2796390510
Short name T469
Test name
Test status
Simulation time 37481401880 ps
CPU time 2539.43 seconds
Started Feb 18 12:39:22 PM PST 24
Finished Feb 18 01:21:44 PM PST 24
Peak memory 288512 kb
Host smart-85988ff3-de48-4797-b0b3-4a8345919acb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796390510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.2796390510
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.4174352529
Short name T313
Test name
Test status
Simulation time 86126691798 ps
CPU time 157.8 seconds
Started Feb 18 12:39:09 PM PST 24
Finished Feb 18 12:41:55 PM PST 24
Peak memory 246324 kb
Host smart-45329967-d271-4bb6-b3eb-876375ce8679
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174352529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.4174352529
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.2983648916
Short name T383
Test name
Test status
Simulation time 3259933274 ps
CPU time 67.05 seconds
Started Feb 18 12:39:17 PM PST 24
Finished Feb 18 12:40:28 PM PST 24
Peak memory 248380 kb
Host smart-48dca94e-05c8-486b-97bd-91998bef5c2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29836
48916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.2983648916
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.3189349612
Short name T540
Test name
Test status
Simulation time 235829237 ps
CPU time 14.27 seconds
Started Feb 18 12:39:17 PM PST 24
Finished Feb 18 12:39:35 PM PST 24
Peak memory 251004 kb
Host smart-79b3210b-2a21-468e-bd82-0713a2d93e41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31893
49612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.3189349612
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.1249183210
Short name T284
Test name
Test status
Simulation time 435174700 ps
CPU time 28.99 seconds
Started Feb 18 12:39:10 PM PST 24
Finished Feb 18 12:39:47 PM PST 24
Peak memory 255088 kb
Host smart-af8b7b72-2ed2-4925-8cf6-4f38d96ab96a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12491
83210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.1249183210
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.810165485
Short name T431
Test name
Test status
Simulation time 70494098 ps
CPU time 3.44 seconds
Started Feb 18 12:39:13 PM PST 24
Finished Feb 18 12:39:23 PM PST 24
Peak memory 240132 kb
Host smart-14129180-ceb2-467b-9421-931b17b6faaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81016
5485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.810165485
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.2172509813
Short name T108
Test name
Test status
Simulation time 237397077360 ps
CPU time 5958.62 seconds
Started Feb 18 12:39:11 PM PST 24
Finished Feb 18 02:18:37 PM PST 24
Peak memory 362664 kb
Host smart-2e72406c-4ed3-484f-97ae-6326da8e5ca6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172509813 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.2172509813
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.2322571164
Short name T128
Test name
Test status
Simulation time 101403942020 ps
CPU time 2904.16 seconds
Started Feb 18 12:39:22 PM PST 24
Finished Feb 18 01:27:49 PM PST 24
Peak memory 285612 kb
Host smart-3f13aa2a-7c2a-4bd9-9b00-6a1e448946d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322571164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.2322571164
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.534264192
Short name T490
Test name
Test status
Simulation time 6966567075 ps
CPU time 176.86 seconds
Started Feb 18 12:39:28 PM PST 24
Finished Feb 18 12:42:27 PM PST 24
Peak memory 255732 kb
Host smart-38e2c46f-b671-421e-a1e3-1471c9b15e3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53426
4192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.534264192
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.2799702167
Short name T665
Test name
Test status
Simulation time 395496978 ps
CPU time 22.11 seconds
Started Feb 18 12:39:03 PM PST 24
Finished Feb 18 12:39:29 PM PST 24
Peak memory 254656 kb
Host smart-842adc7d-55f8-456c-83b4-9f05422f4e83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27997
02167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2799702167
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.3894159411
Short name T322
Test name
Test status
Simulation time 23267739972 ps
CPU time 1698.75 seconds
Started Feb 18 12:39:04 PM PST 24
Finished Feb 18 01:07:28 PM PST 24
Peak memory 288492 kb
Host smart-b51ba57e-e5fc-4fdb-901c-cac656adec55
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894159411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.3894159411
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.334470129
Short name T386
Test name
Test status
Simulation time 32938156590 ps
CPU time 1362.43 seconds
Started Feb 18 12:39:05 PM PST 24
Finished Feb 18 01:01:56 PM PST 24
Peak memory 288520 kb
Host smart-413e29d3-cdeb-4c34-99b9-a9a20175fdca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334470129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.334470129
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.2028021658
Short name T587
Test name
Test status
Simulation time 209965731 ps
CPU time 23.2 seconds
Started Feb 18 12:39:26 PM PST 24
Finished Feb 18 12:39:53 PM PST 24
Peak memory 255124 kb
Host smart-75bb8f62-22c7-460c-8364-cb6ace1ad56b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20280
21658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.2028021658
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.2904392141
Short name T631
Test name
Test status
Simulation time 36899792 ps
CPU time 5.17 seconds
Started Feb 18 12:39:20 PM PST 24
Finished Feb 18 12:39:28 PM PST 24
Peak memory 250364 kb
Host smart-9eb58913-784c-4eac-9d06-2068f68f8c56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29043
92141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.2904392141
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.2552745030
Short name T362
Test name
Test status
Simulation time 356977750 ps
CPU time 18.79 seconds
Started Feb 18 12:39:07 PM PST 24
Finished Feb 18 12:39:34 PM PST 24
Peak memory 248308 kb
Host smart-0b596999-7b51-4a44-b829-839f06b3c359
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25527
45030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.2552745030
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.1733439795
Short name T621
Test name
Test status
Simulation time 16087385166 ps
CPU time 238.2 seconds
Started Feb 18 12:39:15 PM PST 24
Finished Feb 18 12:43:18 PM PST 24
Peak memory 250712 kb
Host smart-5a303751-4e07-4028-b467-e3ccf23d1066
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733439795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.1733439795
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.663784254
Short name T24
Test name
Test status
Simulation time 16149551758 ps
CPU time 1328.16 seconds
Started Feb 18 12:39:03 PM PST 24
Finished Feb 18 01:01:15 PM PST 24
Peak memory 288612 kb
Host smart-c4894b5a-3ff7-4b69-be2b-1dda9c81973c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663784254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.663784254
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.3733962845
Short name T232
Test name
Test status
Simulation time 20410715063 ps
CPU time 166.05 seconds
Started Feb 18 12:39:20 PM PST 24
Finished Feb 18 12:42:09 PM PST 24
Peak memory 256552 kb
Host smart-c10e5fa0-c1d9-46d1-8bcd-9f81cb8f42c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37339
62845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.3733962845
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.2953615752
Short name T80
Test name
Test status
Simulation time 81413983 ps
CPU time 8.46 seconds
Started Feb 18 12:39:10 PM PST 24
Finished Feb 18 12:39:26 PM PST 24
Peak memory 251228 kb
Host smart-879bc647-66ce-4201-bff3-275846409521
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29536
15752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.2953615752
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.888593634
Short name T348
Test name
Test status
Simulation time 39715976475 ps
CPU time 2289.06 seconds
Started Feb 18 12:39:05 PM PST 24
Finished Feb 18 01:17:22 PM PST 24
Peak memory 281592 kb
Host smart-65c17f33-1476-4c3b-a460-4b454b1b0512
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888593634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.888593634
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.3980035439
Short name T627
Test name
Test status
Simulation time 64322744924 ps
CPU time 1687.64 seconds
Started Feb 18 12:39:10 PM PST 24
Finished Feb 18 01:07:25 PM PST 24
Peak memory 271992 kb
Host smart-a27d1927-a671-484b-aecb-3e46f4c9fc3f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980035439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.3980035439
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.551793982
Short name T674
Test name
Test status
Simulation time 3532733257 ps
CPU time 149.18 seconds
Started Feb 18 12:39:13 PM PST 24
Finished Feb 18 12:41:48 PM PST 24
Peak memory 247024 kb
Host smart-d9a01425-bf9e-4289-b345-2f1c03b9cfe8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551793982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.551793982
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2291705354
Short name T634
Test name
Test status
Simulation time 2092728628 ps
CPU time 60.13 seconds
Started Feb 18 12:39:16 PM PST 24
Finished Feb 18 12:40:21 PM PST 24
Peak memory 256544 kb
Host smart-333fb738-8c81-4237-9c75-96e7c96a8f05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22917
05354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2291705354
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.4175200539
Short name T75
Test name
Test status
Simulation time 142645564 ps
CPU time 5.35 seconds
Started Feb 18 12:39:11 PM PST 24
Finished Feb 18 12:39:24 PM PST 24
Peak memory 251444 kb
Host smart-8448b61c-e5a3-41df-b186-7b947dcff9f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41752
00539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.4175200539
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.3071504106
Short name T644
Test name
Test status
Simulation time 763586300 ps
CPU time 49.93 seconds
Started Feb 18 12:39:17 PM PST 24
Finished Feb 18 12:40:11 PM PST 24
Peak memory 254696 kb
Host smart-469695cc-0b41-48fe-8ae9-2747888bda23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30715
04106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.3071504106
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.1949564438
Short name T688
Test name
Test status
Simulation time 2618358870 ps
CPU time 35.98 seconds
Started Feb 18 12:39:12 PM PST 24
Finished Feb 18 12:39:55 PM PST 24
Peak memory 248388 kb
Host smart-ce1cacbe-df9d-4e4f-9c37-ec82ce744ff3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19495
64438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.1949564438
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.170984637
Short name T695
Test name
Test status
Simulation time 295939992 ps
CPU time 8.56 seconds
Started Feb 18 12:39:07 PM PST 24
Finished Feb 18 12:39:23 PM PST 24
Peak memory 252312 kb
Host smart-fd49fa2a-5cc1-4e35-9e61-318e29423566
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170984637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_han
dler_stress_all.170984637
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.2300865427
Short name T390
Test name
Test status
Simulation time 192452100891 ps
CPU time 1272.94 seconds
Started Feb 18 12:39:06 PM PST 24
Finished Feb 18 01:00:27 PM PST 24
Peak memory 272552 kb
Host smart-75a4bd92-f2cf-4b95-9fed-0ab767642774
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300865427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.2300865427
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.2678554037
Short name T586
Test name
Test status
Simulation time 490458661 ps
CPU time 28.73 seconds
Started Feb 18 12:39:10 PM PST 24
Finished Feb 18 12:39:46 PM PST 24
Peak memory 254128 kb
Host smart-9a5f26bf-e669-4ba1-ab3e-f58f8a955ca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26785
54037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.2678554037
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.3301579028
Short name T615
Test name
Test status
Simulation time 532985536 ps
CPU time 15.5 seconds
Started Feb 18 12:39:08 PM PST 24
Finished Feb 18 12:39:31 PM PST 24
Peak memory 252052 kb
Host smart-23ed7fbf-c370-417d-ab5a-6f246822d79e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33015
79028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.3301579028
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.3713257934
Short name T677
Test name
Test status
Simulation time 119415895582 ps
CPU time 1953.46 seconds
Started Feb 18 12:39:19 PM PST 24
Finished Feb 18 01:11:55 PM PST 24
Peak memory 283112 kb
Host smart-26e4e714-07ec-4c93-ab6a-99eea0fcadc9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713257934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.3713257934
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.3536443136
Short name T594
Test name
Test status
Simulation time 47856552591 ps
CPU time 2486.72 seconds
Started Feb 18 12:39:19 PM PST 24
Finished Feb 18 01:20:49 PM PST 24
Peak memory 288872 kb
Host smart-b50bbc5b-9bb0-42e2-82b5-f3266d173d46
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536443136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.3536443136
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.3727905776
Short name T333
Test name
Test status
Simulation time 11105796227 ps
CPU time 415.87 seconds
Started Feb 18 12:39:16 PM PST 24
Finished Feb 18 12:46:16 PM PST 24
Peak memory 247212 kb
Host smart-870c7c4d-97eb-49a1-9487-9fa988ffdb5c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727905776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.3727905776
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.1436343213
Short name T620
Test name
Test status
Simulation time 119949170 ps
CPU time 10.09 seconds
Started Feb 18 12:39:08 PM PST 24
Finished Feb 18 12:39:26 PM PST 24
Peak memory 253076 kb
Host smart-2beecea4-c0ad-4922-bcd8-485200b45716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14363
43213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.1436343213
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.3559582683
Short name T494
Test name
Test status
Simulation time 385665147 ps
CPU time 45.45 seconds
Started Feb 18 12:39:10 PM PST 24
Finished Feb 18 12:40:03 PM PST 24
Peak memory 246532 kb
Host smart-058e6be2-b0e4-472d-8ebf-536792e2aa44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35595
82683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.3559582683
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.2683662596
Short name T72
Test name
Test status
Simulation time 298684559 ps
CPU time 18.64 seconds
Started Feb 18 12:38:58 PM PST 24
Finished Feb 18 12:39:20 PM PST 24
Peak memory 253308 kb
Host smart-a3d99be4-4ddb-41cb-8f68-6f0cd3f6f983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26836
62596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.2683662596
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.1870978808
Short name T373
Test name
Test status
Simulation time 1441222470 ps
CPU time 43.79 seconds
Started Feb 18 12:39:05 PM PST 24
Finished Feb 18 12:39:56 PM PST 24
Peak memory 255096 kb
Host smart-a50d4e15-b467-434f-8f76-f48c1f80b132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18709
78808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.1870978808
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.4017848811
Short name T294
Test name
Test status
Simulation time 3362734524 ps
CPU time 308.85 seconds
Started Feb 18 12:39:16 PM PST 24
Finished Feb 18 12:44:30 PM PST 24
Peak memory 256588 kb
Host smart-aa5d8386-5e3c-45f5-8c47-c3a38caf2e4f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017848811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.4017848811
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.1911702910
Short name T220
Test name
Test status
Simulation time 33447219 ps
CPU time 3.1 seconds
Started Feb 18 12:38:31 PM PST 24
Finished Feb 18 12:38:36 PM PST 24
Peak memory 248552 kb
Host smart-cb4b506b-a139-407c-bfb4-41c4ab7cbd19
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1911702910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1911702910
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.2242251816
Short name T452
Test name
Test status
Simulation time 35157821773 ps
CPU time 2062.17 seconds
Started Feb 18 12:38:46 PM PST 24
Finished Feb 18 01:13:12 PM PST 24
Peak memory 272012 kb
Host smart-0adb39fb-4775-4bb9-a978-38c52adfd1a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242251816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.2242251816
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.2699389131
Short name T385
Test name
Test status
Simulation time 498428990 ps
CPU time 8.03 seconds
Started Feb 18 12:38:34 PM PST 24
Finished Feb 18 12:38:44 PM PST 24
Peak memory 240136 kb
Host smart-25e370d2-152c-4b8f-ac47-c1cd75a09ec7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2699389131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.2699389131
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.2988873046
Short name T412
Test name
Test status
Simulation time 5061036542 ps
CPU time 150.25 seconds
Started Feb 18 12:38:43 PM PST 24
Finished Feb 18 12:41:17 PM PST 24
Peak memory 256124 kb
Host smart-b11b325f-e907-46cb-8404-dba90dd2b70c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29888
73046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.2988873046
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.1230891723
Short name T437
Test name
Test status
Simulation time 562941985 ps
CPU time 23.32 seconds
Started Feb 18 12:38:51 PM PST 24
Finished Feb 18 12:39:17 PM PST 24
Peak memory 254804 kb
Host smart-508ade2a-1735-4316-a311-554f940df765
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12308
91723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.1230891723
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.1284716678
Short name T243
Test name
Test status
Simulation time 87224648790 ps
CPU time 1405.36 seconds
Started Feb 18 12:38:37 PM PST 24
Finished Feb 18 01:02:04 PM PST 24
Peak memory 272936 kb
Host smart-ee628a4e-5d7c-4bfe-8802-e2d5a14bc021
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284716678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.1284716678
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.3830200510
Short name T5
Test name
Test status
Simulation time 47310287761 ps
CPU time 1477.43 seconds
Started Feb 18 12:38:32 PM PST 24
Finished Feb 18 01:03:12 PM PST 24
Peak memory 272956 kb
Host smart-c8875eb7-d567-41cd-b4ec-7bda38f6e672
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830200510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.3830200510
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.465720948
Short name T325
Test name
Test status
Simulation time 13167962063 ps
CPU time 283.33 seconds
Started Feb 18 12:38:34 PM PST 24
Finished Feb 18 12:43:20 PM PST 24
Peak memory 254392 kb
Host smart-05c3b0e5-cf76-4833-b5ac-4930b2c5d5eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465720948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.465720948
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.4020196055
Short name T370
Test name
Test status
Simulation time 6152500840 ps
CPU time 54.44 seconds
Started Feb 18 12:38:47 PM PST 24
Finished Feb 18 12:39:45 PM PST 24
Peak memory 248444 kb
Host smart-4ee01a2d-fcea-40a2-b369-6c54fe27c961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40201
96055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.4020196055
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.808345413
Short name T655
Test name
Test status
Simulation time 1293388389 ps
CPU time 54.16 seconds
Started Feb 18 12:38:35 PM PST 24
Finished Feb 18 12:39:32 PM PST 24
Peak memory 248264 kb
Host smart-7f04aa20-0561-40f8-bf3e-848756451ef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80834
5413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.808345413
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.4106460250
Short name T562
Test name
Test status
Simulation time 33410681139 ps
CPU time 2031.37 seconds
Started Feb 18 12:38:20 PM PST 24
Finished Feb 18 01:12:16 PM PST 24
Peak memory 288976 kb
Host smart-9549616a-09ef-4f6c-8671-f8803d632046
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106460250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.4106460250
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.2509732174
Short name T428
Test name
Test status
Simulation time 145991101843 ps
CPU time 2444.83 seconds
Started Feb 18 12:39:10 PM PST 24
Finished Feb 18 01:20:02 PM PST 24
Peak memory 288492 kb
Host smart-a7942d42-a9eb-4427-a5a9-ae48f31f1850
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509732174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.2509732174
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.3339009502
Short name T387
Test name
Test status
Simulation time 7412519212 ps
CPU time 166.9 seconds
Started Feb 18 12:39:10 PM PST 24
Finished Feb 18 12:42:04 PM PST 24
Peak memory 255212 kb
Host smart-d572224c-2c78-46a1-adf8-c0fc029cb3bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33390
09502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.3339009502
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.911442165
Short name T681
Test name
Test status
Simulation time 913525138 ps
CPU time 15.01 seconds
Started Feb 18 12:39:02 PM PST 24
Finished Feb 18 12:39:20 PM PST 24
Peak memory 248352 kb
Host smart-866ef23b-a667-40ff-a283-ac8fc80a82d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91144
2165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.911442165
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.2525007235
Short name T310
Test name
Test status
Simulation time 21404182980 ps
CPU time 1627.55 seconds
Started Feb 18 12:39:20 PM PST 24
Finished Feb 18 01:06:30 PM PST 24
Peak memory 289196 kb
Host smart-64d27d1d-9234-42a5-bd79-5a7ab6026d66
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525007235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.2525007235
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.1839963991
Short name T531
Test name
Test status
Simulation time 28180182179 ps
CPU time 1634.02 seconds
Started Feb 18 12:39:03 PM PST 24
Finished Feb 18 01:06:21 PM PST 24
Peak memory 272068 kb
Host smart-bb86e4ee-0be8-49c4-81e2-188eb566b30d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839963991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.1839963991
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.4244924281
Short name T234
Test name
Test status
Simulation time 59705593599 ps
CPU time 477.41 seconds
Started Feb 18 12:39:25 PM PST 24
Finished Feb 18 12:47:26 PM PST 24
Peak memory 247044 kb
Host smart-97a5b405-0d22-4dc4-aaa2-5621ca6d68a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244924281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.4244924281
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.3854359223
Short name T632
Test name
Test status
Simulation time 1097128663 ps
CPU time 67.51 seconds
Started Feb 18 12:39:05 PM PST 24
Finished Feb 18 12:40:19 PM PST 24
Peak memory 255172 kb
Host smart-eca349b2-1863-4791-886a-c64dc1be11ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38543
59223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.3854359223
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.3608749177
Short name T74
Test name
Test status
Simulation time 5239765061 ps
CPU time 65.86 seconds
Started Feb 18 12:39:01 PM PST 24
Finished Feb 18 12:40:10 PM PST 24
Peak memory 254280 kb
Host smart-49a81ab2-23f1-4d0b-981e-590d8ad54d86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36087
49177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.3608749177
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.3096108825
Short name T393
Test name
Test status
Simulation time 751595291 ps
CPU time 33.48 seconds
Started Feb 18 12:39:28 PM PST 24
Finished Feb 18 12:40:04 PM PST 24
Peak memory 246772 kb
Host smart-b63ff205-10d1-4f33-bfff-f4124495d23c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30961
08825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.3096108825
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.1000635844
Short name T411
Test name
Test status
Simulation time 53908351 ps
CPU time 4.14 seconds
Started Feb 18 12:39:10 PM PST 24
Finished Feb 18 12:39:22 PM PST 24
Peak memory 248264 kb
Host smart-4fbbbd7b-5e6f-4e56-8031-867c9d6869eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10006
35844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.1000635844
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.1563088219
Short name T270
Test name
Test status
Simulation time 80399706337 ps
CPU time 1469.85 seconds
Started Feb 18 12:39:08 PM PST 24
Finished Feb 18 01:03:45 PM PST 24
Peak memory 289156 kb
Host smart-d5133389-69f2-458a-a4d6-5f9eb297b9df
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563088219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.1563088219
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.1687820159
Short name T134
Test name
Test status
Simulation time 126443180284 ps
CPU time 3409.3 seconds
Started Feb 18 12:39:23 PM PST 24
Finished Feb 18 01:36:16 PM PST 24
Peak memory 314776 kb
Host smart-de286f49-1159-4a44-8513-fcfa51ea48a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687820159 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.1687820159
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.2321834068
Short name T242
Test name
Test status
Simulation time 27287877452 ps
CPU time 1781.54 seconds
Started Feb 18 12:39:28 PM PST 24
Finished Feb 18 01:09:12 PM PST 24
Peak memory 272420 kb
Host smart-f331025c-0f0a-4715-bdc6-e1b983ea133a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321834068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.2321834068
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.2769078089
Short name T646
Test name
Test status
Simulation time 5181618275 ps
CPU time 105.34 seconds
Started Feb 18 12:39:25 PM PST 24
Finished Feb 18 12:41:13 PM PST 24
Peak memory 256556 kb
Host smart-7b00bbf9-bd7f-4ee1-8cf8-a568c8e5bf1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27690
78089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.2769078089
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.2722685183
Short name T480
Test name
Test status
Simulation time 513594407 ps
CPU time 38.31 seconds
Started Feb 18 12:40:50 PM PST 24
Finished Feb 18 12:41:30 PM PST 24
Peak memory 254780 kb
Host smart-34741edc-43ad-448e-b285-9a9568a0f6b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27226
85183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.2722685183
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.1407888339
Short name T617
Test name
Test status
Simulation time 10497051516 ps
CPU time 740.04 seconds
Started Feb 18 12:39:04 PM PST 24
Finished Feb 18 12:51:30 PM PST 24
Peak memory 272796 kb
Host smart-76e35847-e272-437c-9c9e-0b4eca25bd5d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407888339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.1407888339
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.4055060184
Short name T350
Test name
Test status
Simulation time 28404003358 ps
CPU time 1361.34 seconds
Started Feb 18 12:39:24 PM PST 24
Finished Feb 18 01:02:09 PM PST 24
Peak memory 287564 kb
Host smart-0aa1624e-6a20-4d4e-9213-da3c9fe944ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055060184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.4055060184
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.3037989232
Short name T302
Test name
Test status
Simulation time 11336023980 ps
CPU time 440.19 seconds
Started Feb 18 12:39:03 PM PST 24
Finished Feb 18 12:46:27 PM PST 24
Peak memory 247232 kb
Host smart-08f09d39-36ad-4cf3-b8fb-622182833089
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037989232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.3037989232
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.4094710595
Short name T520
Test name
Test status
Simulation time 3696907356 ps
CPU time 56.08 seconds
Started Feb 18 12:39:19 PM PST 24
Finished Feb 18 12:40:18 PM PST 24
Peak memory 248508 kb
Host smart-8efb5db5-f230-43e7-b2df-0cb50d35e7d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40947
10595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.4094710595
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.1442487899
Short name T368
Test name
Test status
Simulation time 1897558485 ps
CPU time 54.9 seconds
Started Feb 18 12:39:15 PM PST 24
Finished Feb 18 12:40:15 PM PST 24
Peak memory 246920 kb
Host smart-2cbfc9a9-90eb-4b92-bbbb-a8a73fe07325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14424
87899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.1442487899
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.642248859
Short name T660
Test name
Test status
Simulation time 776216366 ps
CPU time 22.34 seconds
Started Feb 18 12:39:16 PM PST 24
Finished Feb 18 12:39:43 PM PST 24
Peak memory 255332 kb
Host smart-1747acc1-4f82-4b4a-96a8-46fd47fd792f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64224
8859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.642248859
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.1273223338
Short name T521
Test name
Test status
Simulation time 1091620571 ps
CPU time 57.82 seconds
Started Feb 18 12:40:41 PM PST 24
Finished Feb 18 12:41:41 PM PST 24
Peak memory 255140 kb
Host smart-05ca025f-8316-4c5a-aad8-6cd4a5f09d0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12732
23338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.1273223338
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.1818631171
Short name T44
Test name
Test status
Simulation time 62635194484 ps
CPU time 3956.19 seconds
Started Feb 18 12:39:24 PM PST 24
Finished Feb 18 01:45:25 PM PST 24
Peak memory 321688 kb
Host smart-4d2448fc-529f-47c4-9307-1a4b461cbc71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818631171 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.1818631171
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.509675833
Short name T551
Test name
Test status
Simulation time 8268035424 ps
CPU time 106.42 seconds
Started Feb 18 12:39:15 PM PST 24
Finished Feb 18 12:41:06 PM PST 24
Peak memory 255800 kb
Host smart-0f525d38-de79-4e0f-8e11-117d90f2eb6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50967
5833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.509675833
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.164256498
Short name T596
Test name
Test status
Simulation time 350786808 ps
CPU time 22.93 seconds
Started Feb 18 12:39:17 PM PST 24
Finished Feb 18 12:39:44 PM PST 24
Peak memory 254496 kb
Host smart-5ba427d2-2650-4a91-93d2-7d6a4445997f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16425
6498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.164256498
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.2246264218
Short name T560
Test name
Test status
Simulation time 411179111661 ps
CPU time 1842.21 seconds
Started Feb 18 12:39:23 PM PST 24
Finished Feb 18 01:10:09 PM PST 24
Peak memory 272272 kb
Host smart-f7e73b5c-ea39-42a6-8cff-270409648edd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246264218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.2246264218
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.3397597360
Short name T317
Test name
Test status
Simulation time 11030856351 ps
CPU time 439.23 seconds
Started Feb 18 12:39:10 PM PST 24
Finished Feb 18 12:46:37 PM PST 24
Peak memory 247152 kb
Host smart-0fcd14d3-6184-4e95-a5da-7177a07a2ade
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397597360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.3397597360
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.2378900931
Short name T543
Test name
Test status
Simulation time 102075846 ps
CPU time 12.57 seconds
Started Feb 18 12:39:10 PM PST 24
Finished Feb 18 12:39:30 PM PST 24
Peak memory 248296 kb
Host smart-13a70738-339e-436c-a8b9-639b4eb8a36c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23789
00931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.2378900931
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.2048932696
Short name T491
Test name
Test status
Simulation time 246806709 ps
CPU time 25.25 seconds
Started Feb 18 12:39:09 PM PST 24
Finished Feb 18 12:39:42 PM PST 24
Peak memory 247096 kb
Host smart-9b685858-9aae-43d8-9707-5a0b0a693165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20489
32696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.2048932696
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.75352494
Short name T693
Test name
Test status
Simulation time 447096932 ps
CPU time 33.7 seconds
Started Feb 18 12:39:19 PM PST 24
Finished Feb 18 12:39:55 PM PST 24
Peak memory 246592 kb
Host smart-a40c3f78-2e15-4528-9c4b-78c78aef98c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75352
494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.75352494
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.2358659792
Short name T116
Test name
Test status
Simulation time 212499066 ps
CPU time 5.66 seconds
Started Feb 18 12:39:25 PM PST 24
Finished Feb 18 12:39:34 PM PST 24
Peak memory 248200 kb
Host smart-170c935d-4af1-419d-9331-205d0ea935bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23586
59792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.2358659792
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.840828689
Short name T85
Test name
Test status
Simulation time 52989591837 ps
CPU time 3140.32 seconds
Started Feb 18 12:39:13 PM PST 24
Finished Feb 18 01:31:40 PM PST 24
Peak memory 288704 kb
Host smart-05d30fe6-be9f-478e-94d6-a02aad279990
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840828689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_han
dler_stress_all.840828689
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.3274583889
Short name T28
Test name
Test status
Simulation time 26044513331 ps
CPU time 2177.67 seconds
Started Feb 18 12:39:07 PM PST 24
Finished Feb 18 01:15:33 PM PST 24
Peak memory 297692 kb
Host smart-7fbd413e-2344-46b6-b753-d195e9587d57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274583889 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.3274583889
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.2868917888
Short name T303
Test name
Test status
Simulation time 24124127943 ps
CPU time 1439.32 seconds
Started Feb 18 12:39:10 PM PST 24
Finished Feb 18 01:03:17 PM PST 24
Peak memory 272244 kb
Host smart-6c1c562e-a427-4fdf-89b4-a275dfc66c5d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868917888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.2868917888
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.1987386120
Short name T364
Test name
Test status
Simulation time 37723200940 ps
CPU time 111.14 seconds
Started Feb 18 12:40:50 PM PST 24
Finished Feb 18 12:42:42 PM PST 24
Peak memory 255328 kb
Host smart-bb25130c-1684-4d8c-84b7-174636942656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19873
86120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.1987386120
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.2416074724
Short name T453
Test name
Test status
Simulation time 344872124 ps
CPU time 10.13 seconds
Started Feb 18 12:39:06 PM PST 24
Finished Feb 18 12:39:24 PM PST 24
Peak memory 254800 kb
Host smart-032e9fab-95f4-4b3b-beef-6fc03ed59df2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24160
74724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.2416074724
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.3379083490
Short name T554
Test name
Test status
Simulation time 21139964305 ps
CPU time 1079.37 seconds
Started Feb 18 12:39:19 PM PST 24
Finished Feb 18 12:57:21 PM PST 24
Peak memory 283792 kb
Host smart-bd5e8548-418a-4c13-8a58-f7730c18024c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379083490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.3379083490
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.3751814154
Short name T510
Test name
Test status
Simulation time 54164931138 ps
CPU time 814.69 seconds
Started Feb 18 12:39:11 PM PST 24
Finished Feb 18 12:52:53 PM PST 24
Peak memory 267836 kb
Host smart-bbc49759-2594-4f19-ba1b-a17692083e11
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751814154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.3751814154
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.3210549943
Short name T318
Test name
Test status
Simulation time 6794521359 ps
CPU time 276.88 seconds
Started Feb 18 12:39:11 PM PST 24
Finished Feb 18 12:43:55 PM PST 24
Peak memory 246192 kb
Host smart-bc57cae7-9422-4ccb-b7d9-106b69a955af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210549943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3210549943
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.1057542537
Short name T606
Test name
Test status
Simulation time 1768886602 ps
CPU time 39.63 seconds
Started Feb 18 12:39:06 PM PST 24
Finished Feb 18 12:39:54 PM PST 24
Peak memory 248384 kb
Host smart-bac70e36-409b-4a32-8dd4-91173a91ab7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10575
42537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1057542537
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.1602602240
Short name T436
Test name
Test status
Simulation time 263883082 ps
CPU time 11.42 seconds
Started Feb 18 12:40:41 PM PST 24
Finished Feb 18 12:40:54 PM PST 24
Peak memory 251920 kb
Host smart-daade64f-3f2f-4a8b-bab6-50e8a2ab9c9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16026
02240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.1602602240
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.509555709
Short name T533
Test name
Test status
Simulation time 221058938 ps
CPU time 15.08 seconds
Started Feb 18 12:39:09 PM PST 24
Finished Feb 18 12:39:32 PM PST 24
Peak memory 248292 kb
Host smart-c4604e5b-2a21-4c78-8280-0612b5feb2ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50955
5709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.509555709
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.3059595367
Short name T457
Test name
Test status
Simulation time 1783508012 ps
CPU time 43.07 seconds
Started Feb 18 12:39:23 PM PST 24
Finished Feb 18 12:40:10 PM PST 24
Peak memory 248456 kb
Host smart-a19b8f2c-ab5f-4478-8c73-8fd68304824f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059595367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.3059595367
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.2155301185
Short name T539
Test name
Test status
Simulation time 27930573292 ps
CPU time 2853.18 seconds
Started Feb 18 12:39:15 PM PST 24
Finished Feb 18 01:26:53 PM PST 24
Peak memory 305616 kb
Host smart-85e840e6-3b1a-423a-844b-d92c175d239c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155301185 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.2155301185
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.2927209192
Short name T78
Test name
Test status
Simulation time 53764705918 ps
CPU time 1045.01 seconds
Started Feb 18 12:39:26 PM PST 24
Finished Feb 18 12:56:55 PM PST 24
Peak memory 272696 kb
Host smart-b6539491-8a5b-4659-95f2-ef3843c43f7d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927209192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.2927209192
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.1648084567
Short name T568
Test name
Test status
Simulation time 1204681470 ps
CPU time 39.19 seconds
Started Feb 18 12:40:50 PM PST 24
Finished Feb 18 12:41:30 PM PST 24
Peak memory 246732 kb
Host smart-742169e9-75ac-40f8-b6c7-7bb7171dbe8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16480
84567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1648084567
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.1710171748
Short name T567
Test name
Test status
Simulation time 557456119 ps
CPU time 38.71 seconds
Started Feb 18 12:39:13 PM PST 24
Finished Feb 18 12:39:58 PM PST 24
Peak memory 253828 kb
Host smart-1408481a-3fb6-4bda-9c91-a17495bc79cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17101
71748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.1710171748
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.562758712
Short name T450
Test name
Test status
Simulation time 37598923152 ps
CPU time 1113.97 seconds
Started Feb 18 12:40:51 PM PST 24
Finished Feb 18 12:59:26 PM PST 24
Peak memory 271668 kb
Host smart-4674b4bb-bc3e-4f18-965d-20e27a330f81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562758712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.562758712
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.4142299369
Short name T15
Test name
Test status
Simulation time 621948689 ps
CPU time 42.75 seconds
Started Feb 18 12:39:27 PM PST 24
Finished Feb 18 12:40:13 PM PST 24
Peak memory 248200 kb
Host smart-59e28e8d-36b7-40e0-81f8-66a5c877fb3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41422
99369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.4142299369
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.2953938506
Short name T636
Test name
Test status
Simulation time 581016504 ps
CPU time 37.79 seconds
Started Feb 18 12:39:26 PM PST 24
Finished Feb 18 12:40:07 PM PST 24
Peak memory 254620 kb
Host smart-f872df18-7e30-4913-b209-8c01fbcf915b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29539
38506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.2953938506
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.2776599821
Short name T403
Test name
Test status
Simulation time 9518543560 ps
CPU time 62.17 seconds
Started Feb 18 12:39:08 PM PST 24
Finished Feb 18 12:40:17 PM PST 24
Peak memory 255012 kb
Host smart-a413d014-f3db-4a5f-adc7-251658438efa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27765
99821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.2776599821
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.1242185838
Short name T578
Test name
Test status
Simulation time 694385783 ps
CPU time 11.3 seconds
Started Feb 18 12:39:10 PM PST 24
Finished Feb 18 12:39:32 PM PST 24
Peak memory 248292 kb
Host smart-4892e7f0-8f2a-4fca-8063-09bee85b2060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12421
85838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.1242185838
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.3183259361
Short name T88
Test name
Test status
Simulation time 253943981426 ps
CPU time 2878.41 seconds
Started Feb 18 12:40:51 PM PST 24
Finished Feb 18 01:28:51 PM PST 24
Peak memory 298736 kb
Host smart-1d7fa0b6-4cfd-47d9-afa8-86191c17d2cc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183259361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.3183259361
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.2045173690
Short name T55
Test name
Test status
Simulation time 43989645698 ps
CPU time 1144.93 seconds
Started Feb 18 12:39:22 PM PST 24
Finished Feb 18 12:58:30 PM PST 24
Peak memory 288564 kb
Host smart-9ce27e23-248f-4000-a9ae-157d0278fb47
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045173690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.2045173690
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.2578227521
Short name T229
Test name
Test status
Simulation time 2667523661 ps
CPU time 48.65 seconds
Started Feb 18 12:39:06 PM PST 24
Finished Feb 18 12:40:03 PM PST 24
Peak memory 247968 kb
Host smart-c086f4a9-f4dc-4b67-84d6-5311af3a3019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25782
27521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.2578227521
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.1579569378
Short name T292
Test name
Test status
Simulation time 421571224 ps
CPU time 28.46 seconds
Started Feb 18 12:39:22 PM PST 24
Finished Feb 18 12:39:54 PM PST 24
Peak memory 254672 kb
Host smart-23016d43-6f70-4dbd-8e77-2e1825a47f81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15795
69378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.1579569378
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.1661053972
Short name T569
Test name
Test status
Simulation time 69386054808 ps
CPU time 1823.31 seconds
Started Feb 18 12:39:09 PM PST 24
Finished Feb 18 01:09:40 PM PST 24
Peak memory 272340 kb
Host smart-1ea1ef3e-6388-4b5e-b872-4becd46c6008
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661053972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.1661053972
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.182749833
Short name T267
Test name
Test status
Simulation time 77563605701 ps
CPU time 1191.4 seconds
Started Feb 18 12:39:05 PM PST 24
Finished Feb 18 12:59:04 PM PST 24
Peak memory 287340 kb
Host smart-575a235d-99ec-428c-8847-831fc8751357
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182749833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.182749833
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.4064466147
Short name T327
Test name
Test status
Simulation time 31112430591 ps
CPU time 325.56 seconds
Started Feb 18 12:39:08 PM PST 24
Finished Feb 18 12:44:41 PM PST 24
Peak memory 246008 kb
Host smart-30699253-94a6-4c56-88bc-d799bf6d53da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064466147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.4064466147
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.3677617895
Short name T41
Test name
Test status
Simulation time 296489173 ps
CPU time 19.97 seconds
Started Feb 18 12:39:27 PM PST 24
Finished Feb 18 12:39:50 PM PST 24
Peak memory 248328 kb
Host smart-d8cd7786-13cf-4a5b-a77a-9e171e1dfc3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36776
17895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.3677617895
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.2801864255
Short name T46
Test name
Test status
Simulation time 343783989 ps
CPU time 28.34 seconds
Started Feb 18 12:39:10 PM PST 24
Finished Feb 18 12:39:46 PM PST 24
Peak memory 254508 kb
Host smart-c4d78e95-85a4-468f-a983-5dc358257ac7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28018
64255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.2801864255
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.126241283
Short name T484
Test name
Test status
Simulation time 455261776 ps
CPU time 14.81 seconds
Started Feb 18 12:39:22 PM PST 24
Finished Feb 18 12:39:40 PM PST 24
Peak memory 253892 kb
Host smart-800591ee-2165-4a25-a27b-061aa1efc3a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12624
1283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.126241283
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.60585670
Short name T62
Test name
Test status
Simulation time 326307666 ps
CPU time 19.35 seconds
Started Feb 18 12:39:27 PM PST 24
Finished Feb 18 12:39:49 PM PST 24
Peak memory 254968 kb
Host smart-91d1c8e1-c4ff-484f-a544-f2f99ded19ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60585
670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.60585670
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.379594381
Short name T114
Test name
Test status
Simulation time 16123271255 ps
CPU time 1373.03 seconds
Started Feb 18 12:39:10 PM PST 24
Finished Feb 18 01:02:10 PM PST 24
Peak memory 289300 kb
Host smart-0255bc3d-818b-4279-923f-dd5bae354a8b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379594381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_han
dler_stress_all.379594381
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.2762025300
Short name T112
Test name
Test status
Simulation time 31996710630 ps
CPU time 2107.96 seconds
Started Feb 18 12:39:22 PM PST 24
Finished Feb 18 01:14:33 PM PST 24
Peak memory 272936 kb
Host smart-1ed0a2ef-1cfc-4679-a593-fab5e1ff9a00
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762025300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2762025300
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.2448933283
Short name T686
Test name
Test status
Simulation time 1290699567 ps
CPU time 92.79 seconds
Started Feb 18 12:39:33 PM PST 24
Finished Feb 18 12:41:09 PM PST 24
Peak memory 255800 kb
Host smart-a6762b03-52e8-4a99-8fb5-1e9f162f9ab9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24489
33283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.2448933283
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.267481011
Short name T609
Test name
Test status
Simulation time 595000753 ps
CPU time 15.71 seconds
Started Feb 18 12:39:20 PM PST 24
Finished Feb 18 12:39:38 PM PST 24
Peak memory 253952 kb
Host smart-dbaa2787-f60b-4a99-9ec2-1153aac04981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26748
1011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.267481011
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.2244801388
Short name T346
Test name
Test status
Simulation time 36371953817 ps
CPU time 1378.99 seconds
Started Feb 18 12:39:11 PM PST 24
Finished Feb 18 01:02:17 PM PST 24
Peak memory 288748 kb
Host smart-f3f35f8e-409d-4c73-9158-ac02dee6813b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244801388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.2244801388
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.695491078
Short name T639
Test name
Test status
Simulation time 5241049764 ps
CPU time 185.99 seconds
Started Feb 18 12:39:06 PM PST 24
Finished Feb 18 12:42:20 PM PST 24
Peak memory 247276 kb
Host smart-c3868264-73fa-4403-bfeb-c382065bb13a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695491078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.695491078
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.1830634084
Short name T553
Test name
Test status
Simulation time 491787811 ps
CPU time 20.22 seconds
Started Feb 18 12:39:17 PM PST 24
Finished Feb 18 12:39:41 PM PST 24
Peak memory 248300 kb
Host smart-9acf850c-a957-4541-bf59-1e445d717829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18306
34084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.1830634084
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.3767846564
Short name T400
Test name
Test status
Simulation time 3801967529 ps
CPU time 54.26 seconds
Started Feb 18 12:39:10 PM PST 24
Finished Feb 18 12:40:11 PM PST 24
Peak memory 255756 kb
Host smart-25f392fb-6f3e-4c33-81c2-24e05169870d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37678
46564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3767846564
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.3746387897
Short name T558
Test name
Test status
Simulation time 1106772233 ps
CPU time 27.6 seconds
Started Feb 18 12:39:19 PM PST 24
Finished Feb 18 12:39:49 PM PST 24
Peak memory 248496 kb
Host smart-41ecb91e-9334-4c02-92be-868a6797579b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37463
87897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.3746387897
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.3631358977
Short name T104
Test name
Test status
Simulation time 35902775670 ps
CPU time 2135.3 seconds
Started Feb 18 12:39:20 PM PST 24
Finished Feb 18 01:14:58 PM PST 24
Peak memory 288700 kb
Host smart-f90648c0-c16c-4665-9408-3bb4c7f2cff7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631358977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.3631358977
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.716488158
Short name T517
Test name
Test status
Simulation time 47792935818 ps
CPU time 1131.12 seconds
Started Feb 18 12:39:27 PM PST 24
Finished Feb 18 12:58:21 PM PST 24
Peak memory 272840 kb
Host smart-80eadfa9-89fd-4e2d-bdd9-6d94a563e294
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716488158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.716488158
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.497825159
Short name T399
Test name
Test status
Simulation time 9388407752 ps
CPU time 138.91 seconds
Started Feb 18 12:39:23 PM PST 24
Finished Feb 18 12:41:44 PM PST 24
Peak memory 255544 kb
Host smart-6064430b-0489-4dc4-a358-2274b6b3ee9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49782
5159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.497825159
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.2635318404
Short name T461
Test name
Test status
Simulation time 638711360 ps
CPU time 34.33 seconds
Started Feb 18 12:39:15 PM PST 24
Finished Feb 18 12:39:55 PM PST 24
Peak memory 254760 kb
Host smart-f1313940-0caf-4f58-a797-4e33e9a5ba9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26353
18404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.2635318404
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.660722525
Short name T275
Test name
Test status
Simulation time 34667510428 ps
CPU time 1513.3 seconds
Started Feb 18 12:39:25 PM PST 24
Finished Feb 18 01:04:42 PM PST 24
Peak memory 289128 kb
Host smart-5e5a5581-c0f6-4faa-9bc2-5bafdc256d62
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660722525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.660722525
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.1835356086
Short name T320
Test name
Test status
Simulation time 58590247960 ps
CPU time 604.17 seconds
Started Feb 18 12:39:24 PM PST 24
Finished Feb 18 12:49:32 PM PST 24
Peak memory 247264 kb
Host smart-b4b9ac33-4c33-4ec6-9488-4d4f306a1a95
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835356086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.1835356086
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.2453827737
Short name T241
Test name
Test status
Simulation time 342428409 ps
CPU time 29.05 seconds
Started Feb 18 12:39:27 PM PST 24
Finished Feb 18 12:39:59 PM PST 24
Peak memory 248316 kb
Host smart-d5cecb06-5b33-46cd-92b1-69816233a6a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24538
27737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.2453827737
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.1081134483
Short name T680
Test name
Test status
Simulation time 257051786 ps
CPU time 24.97 seconds
Started Feb 18 12:39:08 PM PST 24
Finished Feb 18 12:39:40 PM PST 24
Peak memory 253212 kb
Host smart-7699c392-4ce4-4543-9731-bb2aafbd54b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10811
34483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.1081134483
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.3063398623
Short name T440
Test name
Test status
Simulation time 4966219724 ps
CPU time 28.93 seconds
Started Feb 18 12:39:09 PM PST 24
Finished Feb 18 12:39:46 PM PST 24
Peak memory 253404 kb
Host smart-deb843ba-224b-4e8c-8fa7-4c7a0afe4750
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30633
98623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.3063398623
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.1637174833
Short name T79
Test name
Test status
Simulation time 1353170922 ps
CPU time 17.57 seconds
Started Feb 18 12:39:23 PM PST 24
Finished Feb 18 12:39:44 PM PST 24
Peak memory 253160 kb
Host smart-38ecfdeb-278f-48cf-8a0e-315af38f3e8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16371
74833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.1637174833
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.2030485948
Short name T420
Test name
Test status
Simulation time 134004230412 ps
CPU time 2092.6 seconds
Started Feb 18 12:39:24 PM PST 24
Finished Feb 18 01:14:20 PM PST 24
Peak memory 271940 kb
Host smart-da6b2edb-4fdb-4d49-991a-1701c9c77b05
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030485948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.2030485948
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.3185340517
Short name T391
Test name
Test status
Simulation time 120434402544 ps
CPU time 2026.63 seconds
Started Feb 18 12:39:20 PM PST 24
Finished Feb 18 01:13:09 PM PST 24
Peak memory 282840 kb
Host smart-786f06cd-9cc9-4759-8419-590d0ea6b2d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185340517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.3185340517
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.3190819054
Short name T361
Test name
Test status
Simulation time 1928166582 ps
CPU time 138.84 seconds
Started Feb 18 12:39:31 PM PST 24
Finished Feb 18 12:41:54 PM PST 24
Peak memory 256160 kb
Host smart-8b450a55-64d7-4b01-985d-75b98e1d5bd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31908
19054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.3190819054
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.2774094698
Short name T133
Test name
Test status
Simulation time 1144897540 ps
CPU time 44.68 seconds
Started Feb 18 12:39:29 PM PST 24
Finished Feb 18 12:40:16 PM PST 24
Peak memory 253956 kb
Host smart-6244117d-2345-4405-81e7-f3797d6ad7e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27740
94698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.2774094698
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.4017224048
Short name T308
Test name
Test status
Simulation time 7100866302 ps
CPU time 163.78 seconds
Started Feb 18 12:39:27 PM PST 24
Finished Feb 18 12:42:14 PM PST 24
Peak memory 248228 kb
Host smart-8c704149-0635-4739-a2a0-1defe108c3aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017224048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.4017224048
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.562573862
Short name T653
Test name
Test status
Simulation time 1599061071 ps
CPU time 52.34 seconds
Started Feb 18 12:39:32 PM PST 24
Finished Feb 18 12:40:27 PM PST 24
Peak memory 248320 kb
Host smart-a28195eb-9eec-4c3d-95aa-d3a97fe71f73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56257
3862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.562573862
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.1781318107
Short name T118
Test name
Test status
Simulation time 442467351 ps
CPU time 25.78 seconds
Started Feb 18 12:39:34 PM PST 24
Finished Feb 18 12:40:03 PM PST 24
Peak memory 253484 kb
Host smart-45989cec-77e5-430f-ad00-0950e0faad5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17813
18107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.1781318107
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.1944608668
Short name T417
Test name
Test status
Simulation time 454297547 ps
CPU time 28.59 seconds
Started Feb 18 12:39:26 PM PST 24
Finished Feb 18 12:39:58 PM PST 24
Peak memory 246600 kb
Host smart-84926e49-15af-4fd3-9272-e65b4a64765d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19446
08668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.1944608668
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.466598521
Short name T404
Test name
Test status
Simulation time 154203389 ps
CPU time 4.66 seconds
Started Feb 18 12:39:23 PM PST 24
Finished Feb 18 12:39:31 PM PST 24
Peak memory 240220 kb
Host smart-e31f462b-c7bc-44e5-b859-fd1e97ea4d38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46659
8521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.466598521
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.2540360242
Short name T441
Test name
Test status
Simulation time 1030625187 ps
CPU time 29.52 seconds
Started Feb 18 12:39:12 PM PST 24
Finished Feb 18 12:39:48 PM PST 24
Peak memory 254996 kb
Host smart-3fe345d3-e75c-48de-9b7e-0b27b9989e0e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540360242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.2540360242
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.3293581376
Short name T592
Test name
Test status
Simulation time 7211746737 ps
CPU time 690.66 seconds
Started Feb 18 12:39:26 PM PST 24
Finished Feb 18 12:51:00 PM PST 24
Peak memory 272588 kb
Host smart-13b54d3a-b6c8-439a-a5b0-a2eb81c26424
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293581376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.3293581376
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.928266958
Short name T528
Test name
Test status
Simulation time 4659358135 ps
CPU time 235.05 seconds
Started Feb 18 12:39:23 PM PST 24
Finished Feb 18 12:43:21 PM PST 24
Peak memory 255812 kb
Host smart-a1a39029-07d2-4f9e-8892-6a0dbbd5f99f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92826
6958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.928266958
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.220690703
Short name T94
Test name
Test status
Simulation time 385431075 ps
CPU time 25.16 seconds
Started Feb 18 12:39:16 PM PST 24
Finished Feb 18 12:39:46 PM PST 24
Peak memory 254540 kb
Host smart-cc8d30cb-a61e-4ade-b2c5-416fa0a50ad9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22069
0703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.220690703
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.1008006516
Short name T335
Test name
Test status
Simulation time 38999623025 ps
CPU time 2278.84 seconds
Started Feb 18 12:39:26 PM PST 24
Finished Feb 18 01:17:29 PM PST 24
Peak memory 281144 kb
Host smart-a4236c00-dcae-45fe-aa03-8696f6a2001e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008006516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.1008006516
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.3182709518
Short name T274
Test name
Test status
Simulation time 111668798541 ps
CPU time 2684.37 seconds
Started Feb 18 12:39:27 PM PST 24
Finished Feb 18 01:24:15 PM PST 24
Peak memory 288500 kb
Host smart-0dee9048-26bd-4287-8e27-6b5725dc7005
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182709518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.3182709518
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.3289071570
Short name T684
Test name
Test status
Simulation time 7181026653 ps
CPU time 281.18 seconds
Started Feb 18 12:39:26 PM PST 24
Finished Feb 18 12:44:11 PM PST 24
Peak memory 247036 kb
Host smart-7ad19179-afeb-42d8-9641-9c9f8cfab92f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289071570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.3289071570
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.139185366
Short name T633
Test name
Test status
Simulation time 319774403 ps
CPU time 5.98 seconds
Started Feb 18 12:39:35 PM PST 24
Finished Feb 18 12:39:43 PM PST 24
Peak memory 240016 kb
Host smart-1ba2c8c4-5e24-4b53-a799-29d3953686b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13918
5366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.139185366
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.88654047
Short name T264
Test name
Test status
Simulation time 798022605 ps
CPU time 7.94 seconds
Started Feb 18 12:39:31 PM PST 24
Finished Feb 18 12:39:43 PM PST 24
Peak memory 253352 kb
Host smart-4b3df0cd-07f3-4399-bf8f-c712791e11cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88654
047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.88654047
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.3568494240
Short name T619
Test name
Test status
Simulation time 1155076028 ps
CPU time 19 seconds
Started Feb 18 12:39:28 PM PST 24
Finished Feb 18 12:39:49 PM PST 24
Peak memory 253820 kb
Host smart-4c2fc3a5-8d17-4674-9280-f574f89a72f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35684
94240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.3568494240
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.958446994
Short name T423
Test name
Test status
Simulation time 967856030 ps
CPU time 54.35 seconds
Started Feb 18 12:39:31 PM PST 24
Finished Feb 18 12:40:29 PM PST 24
Peak memory 248200 kb
Host smart-0709967a-190c-4295-b987-9133d8d8e671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95844
6994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.958446994
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.885728068
Short name T624
Test name
Test status
Simulation time 35980435939 ps
CPU time 1857.7 seconds
Started Feb 18 12:39:26 PM PST 24
Finished Feb 18 01:10:27 PM PST 24
Peak memory 301160 kb
Host smart-7fae8775-9649-4e85-9069-734ca51f3f34
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885728068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_han
dler_stress_all.885728068
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.2420314918
Short name T217
Test name
Test status
Simulation time 30570147 ps
CPU time 2.53 seconds
Started Feb 18 12:38:37 PM PST 24
Finished Feb 18 12:38:41 PM PST 24
Peak memory 248536 kb
Host smart-acd59993-25fe-43c2-a4f7-ecad31869c7d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2420314918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.2420314918
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.1227385699
Short name T662
Test name
Test status
Simulation time 87809184048 ps
CPU time 1668.77 seconds
Started Feb 18 12:38:31 PM PST 24
Finished Feb 18 01:06:22 PM PST 24
Peak memory 272792 kb
Host smart-416bb8a0-e7aa-485e-8af0-7b776cfccd92
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227385699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.1227385699
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.322225389
Short name T409
Test name
Test status
Simulation time 673214901 ps
CPU time 9.7 seconds
Started Feb 18 12:38:36 PM PST 24
Finished Feb 18 12:38:48 PM PST 24
Peak memory 240020 kb
Host smart-92e85e82-aec9-413b-ba42-e0883e6da066
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=322225389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.322225389
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.3965850157
Short name T110
Test name
Test status
Simulation time 3355415740 ps
CPU time 42.67 seconds
Started Feb 18 12:38:34 PM PST 24
Finished Feb 18 12:39:19 PM PST 24
Peak memory 255164 kb
Host smart-ddd3fa53-c6fb-41a8-a909-37854d9cb68c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39658
50157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.3965850157
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.3051645770
Short name T507
Test name
Test status
Simulation time 1589600732 ps
CPU time 43.58 seconds
Started Feb 18 12:38:35 PM PST 24
Finished Feb 18 12:39:21 PM PST 24
Peak memory 253948 kb
Host smart-87461ebd-cf0c-4276-b10f-fe309fff74d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30516
45770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.3051645770
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.3435202393
Short name T672
Test name
Test status
Simulation time 52705484468 ps
CPU time 1160.42 seconds
Started Feb 18 12:38:38 PM PST 24
Finished Feb 18 12:58:00 PM PST 24
Peak memory 271164 kb
Host smart-581c7ca5-5f5e-4e19-bfdf-1cd0615cc99b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435202393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.3435202393
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.1280614743
Short name T442
Test name
Test status
Simulation time 37105831312 ps
CPU time 2296.14 seconds
Started Feb 18 12:38:41 PM PST 24
Finished Feb 18 01:17:00 PM PST 24
Peak memory 288336 kb
Host smart-4eec623f-112f-4b5b-a1dd-de1d046f0cf4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280614743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.1280614743
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.2344862753
Short name T321
Test name
Test status
Simulation time 13479990245 ps
CPU time 393.24 seconds
Started Feb 18 12:38:44 PM PST 24
Finished Feb 18 12:45:21 PM PST 24
Peak memory 254400 kb
Host smart-91cf1398-cdd5-43a2-8c05-9bf03273475e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344862753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.2344862753
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.4005787769
Short name T73
Test name
Test status
Simulation time 97251099 ps
CPU time 7.16 seconds
Started Feb 18 12:38:36 PM PST 24
Finished Feb 18 12:38:46 PM PST 24
Peak memory 248296 kb
Host smart-8a8bcec7-5d47-497b-a078-9ead9dc5e7d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40057
87769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.4005787769
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.1355364368
Short name T9
Test name
Test status
Simulation time 1345026117 ps
CPU time 33.42 seconds
Started Feb 18 12:38:53 PM PST 24
Finished Feb 18 12:39:29 PM PST 24
Peak memory 246912 kb
Host smart-586607a7-bf06-4ad9-ae30-964a30ee7bda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13553
64368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.1355364368
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.1633079284
Short name T12
Test name
Test status
Simulation time 795788004 ps
CPU time 12.36 seconds
Started Feb 18 12:38:34 PM PST 24
Finished Feb 18 12:38:49 PM PST 24
Peak memory 276776 kb
Host smart-7ce9a139-27e8-4f66-92c7-17fb5a0c19b8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1633079284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.1633079284
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.269167960
Short name T89
Test name
Test status
Simulation time 1225416519 ps
CPU time 32.52 seconds
Started Feb 18 12:38:33 PM PST 24
Finished Feb 18 12:39:07 PM PST 24
Peak memory 247668 kb
Host smart-c9b8ce19-c7b5-4286-99ed-e55058061f45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26916
7960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.269167960
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.923551004
Short name T422
Test name
Test status
Simulation time 790601672 ps
CPU time 46.22 seconds
Started Feb 18 12:38:32 PM PST 24
Finished Feb 18 12:39:20 PM PST 24
Peak memory 256500 kb
Host smart-32986177-7f81-4bfd-a2df-f914fef0f321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92355
1004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.923551004
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.1340882061
Short name T663
Test name
Test status
Simulation time 28771109041 ps
CPU time 399.02 seconds
Started Feb 18 12:38:55 PM PST 24
Finished Feb 18 12:45:37 PM PST 24
Peak memory 256536 kb
Host smart-a92d10fb-44ef-441f-880b-63cbf5520642
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340882061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.1340882061
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.3319297522
Short name T102
Test name
Test status
Simulation time 8681498697 ps
CPU time 127.84 seconds
Started Feb 18 12:39:30 PM PST 24
Finished Feb 18 12:41:41 PM PST 24
Peak memory 256076 kb
Host smart-1f094015-467d-4d1b-95d9-76b4b1e5879e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33192
97522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.3319297522
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.2856937778
Short name T83
Test name
Test status
Simulation time 644968241 ps
CPU time 23.2 seconds
Started Feb 18 12:39:34 PM PST 24
Finished Feb 18 12:40:00 PM PST 24
Peak memory 254180 kb
Host smart-fcea3dc2-a160-4cd2-bbe3-5ef3404d66d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28569
37778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.2856937778
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.2591224710
Short name T448
Test name
Test status
Simulation time 49836502988 ps
CPU time 1180.72 seconds
Started Feb 18 12:39:26 PM PST 24
Finished Feb 18 12:59:10 PM PST 24
Peak memory 281160 kb
Host smart-fceccd6d-7ed8-484e-a227-7d0b5be94219
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591224710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.2591224710
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.3106981195
Short name T580
Test name
Test status
Simulation time 13271270012 ps
CPU time 273.81 seconds
Started Feb 18 12:39:34 PM PST 24
Finished Feb 18 12:44:11 PM PST 24
Peak memory 246940 kb
Host smart-7b8093c7-d840-4d96-b601-bbe70c7adc24
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106981195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.3106981195
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.3944943376
Short name T377
Test name
Test status
Simulation time 927098463 ps
CPU time 53.81 seconds
Started Feb 18 12:39:28 PM PST 24
Finished Feb 18 12:40:24 PM PST 24
Peak memory 248416 kb
Host smart-d302fcce-c43d-4568-a5e8-c3ac13817cf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39449
43376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.3944943376
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.2263359017
Short name T54
Test name
Test status
Simulation time 1882650794 ps
CPU time 55.67 seconds
Started Feb 18 12:39:30 PM PST 24
Finished Feb 18 12:40:28 PM PST 24
Peak memory 254932 kb
Host smart-1c1e9885-ed20-4f6a-a898-6ca6195c213e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22633
59017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.2263359017
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.2169590948
Short name T202
Test name
Test status
Simulation time 36520626 ps
CPU time 5.78 seconds
Started Feb 18 12:39:23 PM PST 24
Finished Feb 18 12:39:31 PM PST 24
Peak memory 238400 kb
Host smart-b564dd60-314c-4395-a0d9-e99a181646d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21695
90948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.2169590948
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.1603582477
Short name T504
Test name
Test status
Simulation time 346293576 ps
CPU time 14.99 seconds
Started Feb 18 12:39:26 PM PST 24
Finished Feb 18 12:39:45 PM PST 24
Peak memory 256484 kb
Host smart-a0f8ce3b-4804-4efa-b252-bec4259d2af5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16035
82477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.1603582477
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.3387776271
Short name T602
Test name
Test status
Simulation time 29358916166 ps
CPU time 1627.68 seconds
Started Feb 18 12:39:32 PM PST 24
Finished Feb 18 01:06:43 PM PST 24
Peak memory 272768 kb
Host smart-10d062de-1aca-4d39-ac1b-b56ea9a3563a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387776271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.3387776271
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.2169614401
Short name T10
Test name
Test status
Simulation time 10064397151 ps
CPU time 154.04 seconds
Started Feb 18 12:39:32 PM PST 24
Finished Feb 18 12:42:09 PM PST 24
Peak memory 256144 kb
Host smart-1071c954-94ab-4667-bff4-70410e234e3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21696
14401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.2169614401
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.3391368533
Short name T282
Test name
Test status
Simulation time 707220785 ps
CPU time 43.37 seconds
Started Feb 18 12:39:32 PM PST 24
Finished Feb 18 12:40:19 PM PST 24
Peak memory 254872 kb
Host smart-2a17c0a5-2ab8-49ca-8e37-61adaf70c673
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33913
68533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.3391368533
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.3806840187
Short name T579
Test name
Test status
Simulation time 66820402390 ps
CPU time 2155.62 seconds
Started Feb 18 12:39:38 PM PST 24
Finished Feb 18 01:15:36 PM PST 24
Peak memory 281696 kb
Host smart-5f3c42b6-012e-4649-a6f8-094f056b8b66
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806840187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.3806840187
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.3696116579
Short name T545
Test name
Test status
Simulation time 43951228644 ps
CPU time 905.05 seconds
Started Feb 18 12:39:43 PM PST 24
Finished Feb 18 12:54:50 PM PST 24
Peak memory 267732 kb
Host smart-7de4410c-f865-4614-85aa-64af17659dcc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696116579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.3696116579
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.272280699
Short name T326
Test name
Test status
Simulation time 25778608856 ps
CPU time 278.18 seconds
Started Feb 18 12:39:33 PM PST 24
Finished Feb 18 12:44:14 PM PST 24
Peak memory 247040 kb
Host smart-42077c5c-f390-41e6-840e-2f8798f0577b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272280699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.272280699
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.2700369442
Short name T443
Test name
Test status
Simulation time 397083367 ps
CPU time 28.19 seconds
Started Feb 18 12:39:35 PM PST 24
Finished Feb 18 12:40:05 PM PST 24
Peak memory 248520 kb
Host smart-1d00e0b3-11a3-4045-9c06-ece4e1f9e4db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27003
69442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.2700369442
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.4245567868
Short name T389
Test name
Test status
Simulation time 390776296 ps
CPU time 6.35 seconds
Started Feb 18 12:39:28 PM PST 24
Finished Feb 18 12:39:37 PM PST 24
Peak memory 252016 kb
Host smart-9ef2ff08-6f57-4895-9131-dbb87236aec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42455
67868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.4245567868
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.1238351828
Short name T405
Test name
Test status
Simulation time 78321550 ps
CPU time 8.7 seconds
Started Feb 18 12:39:39 PM PST 24
Finished Feb 18 12:39:49 PM PST 24
Peak memory 248320 kb
Host smart-726ef7a6-c8e1-46f5-aa4d-f7aa98bc004e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12383
51828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.1238351828
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.2944854102
Short name T584
Test name
Test status
Simulation time 81960600 ps
CPU time 11.24 seconds
Started Feb 18 12:39:35 PM PST 24
Finished Feb 18 12:39:49 PM PST 24
Peak memory 248296 kb
Host smart-7a10ceee-e4e0-42dd-8371-1d7e6d9dcad6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29448
54102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.2944854102
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.67592640
Short name T95
Test name
Test status
Simulation time 83978378193 ps
CPU time 377.07 seconds
Started Feb 18 12:39:31 PM PST 24
Finished Feb 18 12:45:52 PM PST 24
Peak memory 256608 kb
Host smart-3078ab59-ede3-45b2-9d52-9505e11dbb8e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67592640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_hand
ler_stress_all.67592640
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.933734986
Short name T427
Test name
Test status
Simulation time 43656971145 ps
CPU time 2215.04 seconds
Started Feb 18 12:39:43 PM PST 24
Finished Feb 18 01:16:40 PM PST 24
Peak memory 289272 kb
Host smart-51d34efb-e547-467c-b8d8-11de716a100f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933734986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.933734986
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.3756526762
Short name T269
Test name
Test status
Simulation time 1473749356 ps
CPU time 104.41 seconds
Started Feb 18 12:39:31 PM PST 24
Finished Feb 18 12:41:18 PM PST 24
Peak memory 256156 kb
Host smart-d1059a8c-7ef2-4e5a-a5b2-f2b7eab9d33b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37565
26762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.3756526762
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.4271519136
Short name T388
Test name
Test status
Simulation time 708692752 ps
CPU time 48.28 seconds
Started Feb 18 12:39:38 PM PST 24
Finished Feb 18 12:40:29 PM PST 24
Peak memory 254804 kb
Host smart-f797bd50-d180-459e-9c22-6c8df4ed07b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42715
19136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.4271519136
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.3985352722
Short name T297
Test name
Test status
Simulation time 19767125402 ps
CPU time 1238.7 seconds
Started Feb 18 12:39:43 PM PST 24
Finished Feb 18 01:00:24 PM PST 24
Peak memory 272412 kb
Host smart-9c9b84f2-ff3f-412c-8e90-c5554d2617b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985352722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.3985352722
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.1582301696
Short name T566
Test name
Test status
Simulation time 187194937149 ps
CPU time 3200.21 seconds
Started Feb 18 12:39:36 PM PST 24
Finished Feb 18 01:33:00 PM PST 24
Peak memory 288800 kb
Host smart-b8f0fc77-f7f0-4f75-ac7a-ba27be5ec5cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582301696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.1582301696
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.3204736565
Short name T538
Test name
Test status
Simulation time 684412231 ps
CPU time 44.69 seconds
Started Feb 18 12:39:37 PM PST 24
Finished Feb 18 12:40:24 PM PST 24
Peak memory 248316 kb
Host smart-17763930-b80f-42ef-b484-0c78d765aba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32047
36565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.3204736565
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.2274259702
Short name T682
Test name
Test status
Simulation time 1606827653 ps
CPU time 15.77 seconds
Started Feb 18 12:39:35 PM PST 24
Finished Feb 18 12:39:53 PM PST 24
Peak memory 252436 kb
Host smart-d2653ec4-6636-4a98-be67-d4e29e9e121c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22742
59702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.2274259702
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.3368639014
Short name T235
Test name
Test status
Simulation time 954349415 ps
CPU time 17.77 seconds
Started Feb 18 12:39:34 PM PST 24
Finished Feb 18 12:39:54 PM PST 24
Peak memory 253748 kb
Host smart-c2c58919-d873-47da-9391-73550f152b0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33686
39014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.3368639014
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.4145035924
Short name T34
Test name
Test status
Simulation time 815304571 ps
CPU time 14.46 seconds
Started Feb 18 12:39:29 PM PST 24
Finished Feb 18 12:39:46 PM PST 24
Peak memory 248332 kb
Host smart-2c39db46-71d4-481e-b6ff-d66a89fc4f4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41450
35924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.4145035924
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.2264041388
Short name T447
Test name
Test status
Simulation time 3446694054 ps
CPU time 255.24 seconds
Started Feb 18 12:39:41 PM PST 24
Finished Feb 18 12:43:59 PM PST 24
Peak memory 256024 kb
Host smart-8b8add52-9879-462d-bc36-1a9f4416e2d0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264041388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.2264041388
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.2797017976
Short name T42
Test name
Test status
Simulation time 50808478668 ps
CPU time 955.66 seconds
Started Feb 18 12:39:41 PM PST 24
Finished Feb 18 12:55:39 PM PST 24
Peak memory 272852 kb
Host smart-83a6febb-4a9e-43e6-b2dc-9c6191d75c54
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797017976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.2797017976
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.926986663
Short name T456
Test name
Test status
Simulation time 15893368599 ps
CPU time 228.17 seconds
Started Feb 18 12:39:40 PM PST 24
Finished Feb 18 12:43:30 PM PST 24
Peak memory 255892 kb
Host smart-2fc95ca6-3c10-4692-9130-1938519d9f11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92698
6663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.926986663
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.3846037026
Short name T692
Test name
Test status
Simulation time 67951770 ps
CPU time 6.45 seconds
Started Feb 18 12:39:41 PM PST 24
Finished Feb 18 12:39:50 PM PST 24
Peak memory 251896 kb
Host smart-cecca2cc-1eb0-4522-a84b-f992e89f5bab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38460
37026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.3846037026
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.3435265157
Short name T696
Test name
Test status
Simulation time 33862110330 ps
CPU time 1869.46 seconds
Started Feb 18 12:39:41 PM PST 24
Finished Feb 18 01:10:53 PM PST 24
Peak memory 288408 kb
Host smart-b58e265c-6ae9-4791-810b-cf5935868889
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435265157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.3435265157
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.4156329453
Short name T561
Test name
Test status
Simulation time 43912250198 ps
CPU time 1471.25 seconds
Started Feb 18 12:39:41 PM PST 24
Finished Feb 18 01:04:14 PM PST 24
Peak memory 288112 kb
Host smart-fbfa1de2-8cf1-4e2c-b5ea-82c9ac94eeda
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156329453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.4156329453
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.10318864
Short name T66
Test name
Test status
Simulation time 212887678900 ps
CPU time 514.73 seconds
Started Feb 18 12:39:43 PM PST 24
Finished Feb 18 12:48:20 PM PST 24
Peak memory 248232 kb
Host smart-6ce9a87e-6877-4d2f-af11-d6e63aacea82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10318864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.10318864
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.1993183676
Short name T608
Test name
Test status
Simulation time 232830732 ps
CPU time 29.84 seconds
Started Feb 18 12:39:40 PM PST 24
Finished Feb 18 12:40:12 PM PST 24
Peak memory 248336 kb
Host smart-457af23f-1be0-496b-b7cb-1209c0f3fae9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19931
83676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.1993183676
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.1372007384
Short name T374
Test name
Test status
Simulation time 75667963 ps
CPU time 3.78 seconds
Started Feb 18 12:39:38 PM PST 24
Finished Feb 18 12:39:44 PM PST 24
Peak memory 238364 kb
Host smart-3358439f-cd8a-4a49-99a8-725f79589425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13720
07384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.1372007384
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.572157647
Short name T381
Test name
Test status
Simulation time 164730937 ps
CPU time 17.83 seconds
Started Feb 18 12:39:38 PM PST 24
Finished Feb 18 12:39:59 PM PST 24
Peak memory 248432 kb
Host smart-a91aeb0f-2180-4f73-81cf-42c170f00025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57215
7647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.572157647
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.469243155
Short name T33
Test name
Test status
Simulation time 1375086325 ps
CPU time 34.24 seconds
Started Feb 18 12:39:40 PM PST 24
Finished Feb 18 12:40:16 PM PST 24
Peak memory 254920 kb
Host smart-963cc690-7a9c-4f88-9d99-f2809527a2f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46924
3155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.469243155
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.1977370131
Short name T661
Test name
Test status
Simulation time 67347647712 ps
CPU time 3854.94 seconds
Started Feb 18 12:39:39 PM PST 24
Finished Feb 18 01:43:56 PM PST 24
Peak memory 297632 kb
Host smart-a008b241-2b58-4c6c-828e-fa8504ec6651
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977370131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.1977370131
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.380228435
Short name T207
Test name
Test status
Simulation time 241231057783 ps
CPU time 6823.83 seconds
Started Feb 18 12:39:37 PM PST 24
Finished Feb 18 02:33:24 PM PST 24
Peak memory 338452 kb
Host smart-6e691f77-3aa1-4d19-9455-ed1888ae24b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380228435 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.380228435
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.3184764869
Short name T132
Test name
Test status
Simulation time 10236755027 ps
CPU time 535.59 seconds
Started Feb 18 12:39:50 PM PST 24
Finished Feb 18 12:48:48 PM PST 24
Peak memory 264768 kb
Host smart-0f109edc-cbd9-419d-a325-9b50445f1c8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184764869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.3184764869
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.3579473680
Short name T425
Test name
Test status
Simulation time 1720359291 ps
CPU time 41.85 seconds
Started Feb 18 12:39:48 PM PST 24
Finished Feb 18 12:40:32 PM PST 24
Peak memory 247892 kb
Host smart-7bc18fff-5bd8-44aa-9138-d83f54162116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35794
73680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.3579473680
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.300116071
Short name T84
Test name
Test status
Simulation time 2258013606 ps
CPU time 31.86 seconds
Started Feb 18 12:39:45 PM PST 24
Finished Feb 18 12:40:18 PM PST 24
Peak memory 254776 kb
Host smart-7468ce9f-9437-483a-854a-3ae603488b35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30011
6071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.300116071
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.2183536918
Short name T342
Test name
Test status
Simulation time 49707560864 ps
CPU time 2717.88 seconds
Started Feb 18 12:39:46 PM PST 24
Finished Feb 18 01:25:06 PM PST 24
Peak memory 288824 kb
Host smart-85b14697-3224-4235-96c9-f8cce34ea124
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183536918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.2183536918
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.878570979
Short name T486
Test name
Test status
Simulation time 49816315364 ps
CPU time 707.26 seconds
Started Feb 18 12:39:46 PM PST 24
Finished Feb 18 12:51:35 PM PST 24
Peak memory 271848 kb
Host smart-009e1953-a2d7-430e-be12-64cb16cdb6fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878570979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.878570979
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.2213777142
Short name T444
Test name
Test status
Simulation time 1875333682 ps
CPU time 54.1 seconds
Started Feb 18 12:39:45 PM PST 24
Finished Feb 18 12:40:41 PM PST 24
Peak memory 248332 kb
Host smart-3d8af4b4-1ccd-4a2c-a908-cab893cbfd76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22137
77142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.2213777142
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.3373691785
Short name T50
Test name
Test status
Simulation time 111190635 ps
CPU time 11.74 seconds
Started Feb 18 12:39:50 PM PST 24
Finished Feb 18 12:40:04 PM PST 24
Peak memory 254336 kb
Host smart-88882bda-11fa-4314-85d1-fb77c6e064c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33736
91785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.3373691785
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.4167690462
Short name T285
Test name
Test status
Simulation time 433714053 ps
CPU time 29.73 seconds
Started Feb 18 12:39:45 PM PST 24
Finished Feb 18 12:40:17 PM PST 24
Peak memory 247616 kb
Host smart-e42b3c24-4cfb-40be-aeb4-9cf5a7629f6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41676
90462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.4167690462
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.57864289
Short name T360
Test name
Test status
Simulation time 369879357 ps
CPU time 11.83 seconds
Started Feb 18 12:39:43 PM PST 24
Finished Feb 18 12:39:57 PM PST 24
Peak memory 248200 kb
Host smart-43630f2d-ced9-49bf-a117-d95d5a1a62a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57864
289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.57864289
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.1397174902
Short name T130
Test name
Test status
Simulation time 347097346094 ps
CPU time 5218.94 seconds
Started Feb 18 12:39:48 PM PST 24
Finished Feb 18 02:06:50 PM PST 24
Peak memory 338452 kb
Host smart-e897ca86-aa12-4e22-91be-14c7877e4615
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397174902 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.1397174902
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.1866038815
Short name T125
Test name
Test status
Simulation time 99636068863 ps
CPU time 1340.56 seconds
Started Feb 18 12:39:44 PM PST 24
Finished Feb 18 01:02:07 PM PST 24
Peak memory 264896 kb
Host smart-d8b9d2cf-04a9-4ce2-bda8-3c4386eb0cc4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866038815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.1866038815
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.1012034059
Short name T687
Test name
Test status
Simulation time 3437770767 ps
CPU time 185.7 seconds
Started Feb 18 12:39:48 PM PST 24
Finished Feb 18 12:42:56 PM PST 24
Peak memory 256256 kb
Host smart-241c76af-bb1e-41dd-914b-690dad989507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10120
34059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.1012034059
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.3033653731
Short name T582
Test name
Test status
Simulation time 105898000 ps
CPU time 9.35 seconds
Started Feb 18 12:39:45 PM PST 24
Finished Feb 18 12:39:56 PM PST 24
Peak memory 252184 kb
Host smart-e3585253-6e6f-48cc-947e-199ca25139c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30336
53731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.3033653731
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.1385173102
Short name T347
Test name
Test status
Simulation time 108809732204 ps
CPU time 3151.32 seconds
Started Feb 18 12:39:50 PM PST 24
Finished Feb 18 01:32:24 PM PST 24
Peak memory 288332 kb
Host smart-95af25c6-e2a9-4234-9987-9d34c26ef81d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385173102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.1385173102
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.1598487711
Short name T120
Test name
Test status
Simulation time 32831871268 ps
CPU time 1478.23 seconds
Started Feb 18 12:39:57 PM PST 24
Finished Feb 18 01:04:36 PM PST 24
Peak memory 289212 kb
Host smart-cd6d7469-2644-41dc-bf7b-d5106c7fff6c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598487711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1598487711
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.1422253093
Short name T487
Test name
Test status
Simulation time 1812459685 ps
CPU time 79.78 seconds
Started Feb 18 12:39:50 PM PST 24
Finished Feb 18 12:41:11 PM PST 24
Peak memory 246952 kb
Host smart-8b47471c-064c-48ed-ae80-b87ee55c4d84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422253093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.1422253093
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.237876333
Short name T1
Test name
Test status
Simulation time 747206370 ps
CPU time 12.71 seconds
Started Feb 18 12:39:51 PM PST 24
Finished Feb 18 12:40:07 PM PST 24
Peak memory 253176 kb
Host smart-fe1a7daa-668e-44b4-947a-e4225b93514a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23787
6333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.237876333
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.3260059219
Short name T376
Test name
Test status
Simulation time 352993439 ps
CPU time 6.03 seconds
Started Feb 18 12:39:48 PM PST 24
Finished Feb 18 12:39:57 PM PST 24
Peak memory 239600 kb
Host smart-e71317fb-edb8-4038-b045-d445d632a2c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32600
59219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.3260059219
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.2622516208
Short name T86
Test name
Test status
Simulation time 2428450608 ps
CPU time 69.81 seconds
Started Feb 18 12:39:48 PM PST 24
Finished Feb 18 12:40:59 PM PST 24
Peak memory 254600 kb
Host smart-b4a7e96d-8c6b-4fdc-8546-1d4dd8c4df38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26225
16208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.2622516208
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.927876244
Short name T623
Test name
Test status
Simulation time 695503141 ps
CPU time 12.3 seconds
Started Feb 18 12:39:45 PM PST 24
Finished Feb 18 12:39:59 PM PST 24
Peak memory 248308 kb
Host smart-a988fddc-2d08-40a9-8a86-ea614519b5bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92787
6244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.927876244
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.438295536
Short name T493
Test name
Test status
Simulation time 105266668568 ps
CPU time 1954.3 seconds
Started Feb 18 12:39:51 PM PST 24
Finished Feb 18 01:12:28 PM PST 24
Peak memory 272200 kb
Host smart-038f8a4e-044e-4669-ba95-114731182ca3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438295536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.438295536
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.3044974406
Short name T669
Test name
Test status
Simulation time 11055044248 ps
CPU time 160.7 seconds
Started Feb 18 12:39:50 PM PST 24
Finished Feb 18 12:42:33 PM PST 24
Peak memory 256524 kb
Host smart-b8aa39b5-8263-4f7a-943c-770d505db6b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30449
74406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.3044974406
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.4003645789
Short name T470
Test name
Test status
Simulation time 65076251 ps
CPU time 6.08 seconds
Started Feb 18 12:39:50 PM PST 24
Finished Feb 18 12:39:58 PM PST 24
Peak memory 238484 kb
Host smart-d4b2a493-acb7-4ca3-af6e-8c83cba71909
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40036
45789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.4003645789
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.1559837244
Short name T519
Test name
Test status
Simulation time 57331611829 ps
CPU time 1627.33 seconds
Started Feb 18 12:39:54 PM PST 24
Finished Feb 18 01:07:04 PM PST 24
Peak memory 264560 kb
Host smart-4f3e2074-9cd5-4eec-9b9c-82b57759964e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559837244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.1559837244
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.3980307684
Short name T610
Test name
Test status
Simulation time 8682903701 ps
CPU time 752.46 seconds
Started Feb 18 12:39:53 PM PST 24
Finished Feb 18 12:52:27 PM PST 24
Peak memory 265164 kb
Host smart-923c32c8-9e60-4bc5-a724-ac8c5e752d3e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980307684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.3980307684
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.2832427292
Short name T330
Test name
Test status
Simulation time 30498918357 ps
CPU time 336.75 seconds
Started Feb 18 12:39:55 PM PST 24
Finished Feb 18 12:45:33 PM PST 24
Peak memory 247040 kb
Host smart-c80301bc-ed8a-4364-b16a-18c5d3c77206
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832427292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.2832427292
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.1248245124
Short name T622
Test name
Test status
Simulation time 1013763606 ps
CPU time 64.57 seconds
Started Feb 18 12:39:52 PM PST 24
Finished Feb 18 12:40:59 PM PST 24
Peak memory 248316 kb
Host smart-c4dd448d-111f-46d4-970b-7f1c7dec484e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12482
45124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.1248245124
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.3462676152
Short name T121
Test name
Test status
Simulation time 646320306 ps
CPU time 15.14 seconds
Started Feb 18 12:39:51 PM PST 24
Finished Feb 18 12:40:08 PM PST 24
Peak memory 254176 kb
Host smart-bca77f42-2105-4891-a018-442be5604f82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34626
76152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.3462676152
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.1844651487
Short name T564
Test name
Test status
Simulation time 1497326766 ps
CPU time 46.51 seconds
Started Feb 18 12:39:51 PM PST 24
Finished Feb 18 12:40:41 PM PST 24
Peak memory 248324 kb
Host smart-a9b8f401-3afd-4b99-80ec-adc74f6739e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18446
51487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.1844651487
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.2338158374
Short name T394
Test name
Test status
Simulation time 380183322 ps
CPU time 13.55 seconds
Started Feb 18 12:39:55 PM PST 24
Finished Feb 18 12:40:10 PM PST 24
Peak memory 253824 kb
Host smart-38ab420c-40d2-4f6c-ab2c-2d175e1a080a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23381
58374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.2338158374
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.1689579837
Short name T68
Test name
Test status
Simulation time 24580505685 ps
CPU time 1571.82 seconds
Started Feb 18 12:40:00 PM PST 24
Finished Feb 18 01:06:14 PM PST 24
Peak memory 289144 kb
Host smart-712f5f4c-ebeb-4b0a-a3b4-35a854b827b5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689579837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.1689579837
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.2059790613
Short name T43
Test name
Test status
Simulation time 46296033419 ps
CPU time 2695.72 seconds
Started Feb 18 12:39:56 PM PST 24
Finished Feb 18 01:24:54 PM PST 24
Peak memory 318008 kb
Host smart-752fba7c-93a6-4e31-8738-0029a731d828
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059790613 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.2059790613
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.4017465993
Short name T459
Test name
Test status
Simulation time 229803186871 ps
CPU time 2236.87 seconds
Started Feb 18 12:39:56 PM PST 24
Finished Feb 18 01:17:14 PM PST 24
Peak memory 282612 kb
Host smart-074bc509-8e75-4dff-bc45-08b763031ea0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017465993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.4017465993
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.565591527
Short name T63
Test name
Test status
Simulation time 9439923237 ps
CPU time 257.24 seconds
Started Feb 18 12:39:54 PM PST 24
Finished Feb 18 12:44:12 PM PST 24
Peak memory 255968 kb
Host smart-daacbc6f-2481-43ff-bc5d-cd78b444ec63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56559
1527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.565591527
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.2093462574
Short name T454
Test name
Test status
Simulation time 2002887415 ps
CPU time 31.26 seconds
Started Feb 18 12:39:52 PM PST 24
Finished Feb 18 12:40:26 PM PST 24
Peak memory 254680 kb
Host smart-3d4b7a03-16cc-4aca-8094-c9fa381f5ec8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20934
62574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.2093462574
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.1296854833
Short name T550
Test name
Test status
Simulation time 41473538164 ps
CPU time 1753.76 seconds
Started Feb 18 12:39:53 PM PST 24
Finished Feb 18 01:09:09 PM PST 24
Peak memory 272476 kb
Host smart-a1cd624d-99cc-4e66-b1aa-9aae82073e38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296854833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.1296854833
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.52514329
Short name T38
Test name
Test status
Simulation time 26799615747 ps
CPU time 486.74 seconds
Started Feb 18 12:39:59 PM PST 24
Finished Feb 18 12:48:08 PM PST 24
Peak memory 247372 kb
Host smart-aebbb3ff-991a-41bf-bf08-834412ad4a26
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52514329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.52514329
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.1337554160
Short name T468
Test name
Test status
Simulation time 137140594 ps
CPU time 3.6 seconds
Started Feb 18 12:39:56 PM PST 24
Finished Feb 18 12:40:01 PM PST 24
Peak memory 240120 kb
Host smart-11605f86-3a52-4b0d-a9fc-6dbc04f051d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13375
54160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.1337554160
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.824026090
Short name T109
Test name
Test status
Simulation time 289910512 ps
CPU time 37.03 seconds
Started Feb 18 12:39:53 PM PST 24
Finished Feb 18 12:40:32 PM PST 24
Peak memory 255096 kb
Host smart-660ee5c1-f4b6-4cc3-aa35-846750f5c507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82402
6090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.824026090
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.1285189751
Short name T283
Test name
Test status
Simulation time 285980461 ps
CPU time 35.06 seconds
Started Feb 18 12:39:55 PM PST 24
Finished Feb 18 12:40:32 PM PST 24
Peak memory 256020 kb
Host smart-e7275b4f-f67f-4591-aaac-e29ad30f7956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12851
89751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.1285189751
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.1762762122
Short name T549
Test name
Test status
Simulation time 709192410 ps
CPU time 44.13 seconds
Started Feb 18 12:39:55 PM PST 24
Finished Feb 18 12:40:41 PM PST 24
Peak memory 248320 kb
Host smart-2765c7b2-5d5e-4e83-a2d0-bd18dbf1a0f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17627
62122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.1762762122
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.2829578495
Short name T495
Test name
Test status
Simulation time 6798761751 ps
CPU time 355.47 seconds
Started Feb 18 12:39:56 PM PST 24
Finished Feb 18 12:45:52 PM PST 24
Peak memory 256560 kb
Host smart-791e9b9b-28c7-43a2-ae8a-dd8ee6da301a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829578495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.2829578495
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.3616789754
Short name T197
Test name
Test status
Simulation time 247895200842 ps
CPU time 5915.92 seconds
Started Feb 18 12:39:55 PM PST 24
Finished Feb 18 02:18:33 PM PST 24
Peak memory 354320 kb
Host smart-b3b69ac1-86d0-4ac7-82a8-13eda4253b4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616789754 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.3616789754
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.3960058043
Short name T616
Test name
Test status
Simulation time 25800632785 ps
CPU time 1828.34 seconds
Started Feb 18 12:40:04 PM PST 24
Finished Feb 18 01:10:35 PM PST 24
Peak memory 272696 kb
Host smart-a420622f-ab67-4ab5-9ada-a7a513eea397
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960058043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.3960058043
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.1380700978
Short name T99
Test name
Test status
Simulation time 6231737839 ps
CPU time 92.95 seconds
Started Feb 18 12:40:03 PM PST 24
Finished Feb 18 12:41:37 PM PST 24
Peak memory 256136 kb
Host smart-96bc07ae-d6ec-43e2-a066-300c8ce7997b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13807
00978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.1380700978
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.806532015
Short name T645
Test name
Test status
Simulation time 2111708415 ps
CPU time 65.05 seconds
Started Feb 18 12:39:57 PM PST 24
Finished Feb 18 12:41:03 PM PST 24
Peak memory 255184 kb
Host smart-98c414f5-7098-4eb5-bb3b-0e6dde342455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80653
2015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.806532015
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.4179019291
Short name T37
Test name
Test status
Simulation time 287091798137 ps
CPU time 2571.24 seconds
Started Feb 18 12:40:00 PM PST 24
Finished Feb 18 01:22:53 PM PST 24
Peak memory 283796 kb
Host smart-7ea680c5-ebe1-4ecf-87ff-5d6e72264228
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179019291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.4179019291
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.2008737313
Short name T328
Test name
Test status
Simulation time 95849547128 ps
CPU time 574.39 seconds
Started Feb 18 12:40:05 PM PST 24
Finished Feb 18 12:49:42 PM PST 24
Peak memory 247260 kb
Host smart-97596b2f-361d-4b6e-8b17-4a6392f1e4cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008737313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.2008737313
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.1857337716
Short name T455
Test name
Test status
Simulation time 358783588 ps
CPU time 24.15 seconds
Started Feb 18 12:40:00 PM PST 24
Finished Feb 18 12:40:26 PM PST 24
Peak memory 248204 kb
Host smart-05329ae4-24fb-4185-84df-5db3c04d7451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18573
37716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.1857337716
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.3155818715
Short name T438
Test name
Test status
Simulation time 416399554 ps
CPU time 19 seconds
Started Feb 18 12:39:53 PM PST 24
Finished Feb 18 12:40:14 PM PST 24
Peak memory 247168 kb
Host smart-ca37a72e-2554-45a9-a636-067e6dc4d241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31558
18715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.3155818715
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.1161692723
Short name T287
Test name
Test status
Simulation time 2325720380 ps
CPU time 46.9 seconds
Started Feb 18 12:40:03 PM PST 24
Finished Feb 18 12:40:51 PM PST 24
Peak memory 254716 kb
Host smart-7bddbb54-6971-4bae-812e-8cc79c6c285f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11616
92723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.1161692723
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.338435297
Short name T395
Test name
Test status
Simulation time 2304176879 ps
CPU time 34.52 seconds
Started Feb 18 12:39:54 PM PST 24
Finished Feb 18 12:40:30 PM PST 24
Peak memory 248300 kb
Host smart-c24da99c-0e7b-4afd-bd23-18e9098cac5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33843
5297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.338435297
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.738317385
Short name T27
Test name
Test status
Simulation time 63369565568 ps
CPU time 1146.19 seconds
Started Feb 18 12:40:01 PM PST 24
Finished Feb 18 12:59:09 PM PST 24
Peak memory 272204 kb
Host smart-33f3cae6-53ce-40ea-ba4e-532bae164e51
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738317385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.738317385
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.4225729402
Short name T36
Test name
Test status
Simulation time 1855609752 ps
CPU time 156.42 seconds
Started Feb 18 12:40:09 PM PST 24
Finished Feb 18 12:42:48 PM PST 24
Peak memory 255984 kb
Host smart-f5c4899c-4b95-4501-a6a8-ac9554481680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42257
29402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.4225729402
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.1929448307
Short name T3
Test name
Test status
Simulation time 174753018 ps
CPU time 15.84 seconds
Started Feb 18 12:40:00 PM PST 24
Finished Feb 18 12:40:17 PM PST 24
Peak memory 254496 kb
Host smart-8353edff-6952-43b0-90ac-8dd97dfdf587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19294
48307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.1929448307
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.4121238411
Short name T345
Test name
Test status
Simulation time 157301050341 ps
CPU time 1257.24 seconds
Started Feb 18 12:40:01 PM PST 24
Finished Feb 18 01:01:00 PM PST 24
Peak memory 272336 kb
Host smart-50b64b6b-3ee1-418e-a863-a269c785dbd2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121238411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.4121238411
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.1521036439
Short name T523
Test name
Test status
Simulation time 23151517146 ps
CPU time 1461.96 seconds
Started Feb 18 12:40:03 PM PST 24
Finished Feb 18 01:04:27 PM PST 24
Peak memory 273060 kb
Host smart-14972691-7b84-4dc1-b66a-79c616bc59d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521036439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.1521036439
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.2460711558
Short name T324
Test name
Test status
Simulation time 5239904101 ps
CPU time 183.97 seconds
Started Feb 18 12:40:02 PM PST 24
Finished Feb 18 12:43:08 PM PST 24
Peak memory 247272 kb
Host smart-89df03d9-275d-43a6-b034-9e67b66d1bd8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460711558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.2460711558
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.2962845355
Short name T467
Test name
Test status
Simulation time 3207791311 ps
CPU time 47.71 seconds
Started Feb 18 12:39:59 PM PST 24
Finished Feb 18 12:40:49 PM PST 24
Peak memory 248424 kb
Host smart-36b038e3-dacc-41ac-a463-bf5d4767230a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29628
45355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.2962845355
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.168469221
Short name T518
Test name
Test status
Simulation time 1032469738 ps
CPU time 30.26 seconds
Started Feb 18 12:40:04 PM PST 24
Finished Feb 18 12:40:35 PM PST 24
Peak memory 246756 kb
Host smart-d60df4c7-50bc-46cc-b74e-d835e25cf3d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16846
9221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.168469221
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.919697569
Short name T482
Test name
Test status
Simulation time 325748065 ps
CPU time 20.23 seconds
Started Feb 18 12:40:04 PM PST 24
Finished Feb 18 12:40:27 PM PST 24
Peak memory 248152 kb
Host smart-3183be27-9811-408d-b7ea-c8074674f1a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91969
7569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.919697569
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.863010670
Short name T434
Test name
Test status
Simulation time 241541983 ps
CPU time 14.68 seconds
Started Feb 18 12:40:09 PM PST 24
Finished Feb 18 12:40:26 PM PST 24
Peak memory 256496 kb
Host smart-cde54e20-2031-4892-beeb-8dedee2f7aaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86301
0670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.863010670
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.1019669098
Short name T477
Test name
Test status
Simulation time 7398148880 ps
CPU time 442.33 seconds
Started Feb 18 12:40:15 PM PST 24
Finished Feb 18 12:47:47 PM PST 24
Peak memory 256592 kb
Host smart-3ce86fb6-ff9c-4ec9-9bcf-1118874df8eb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019669098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.1019669098
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.3240761791
Short name T223
Test name
Test status
Simulation time 38946944 ps
CPU time 2.22 seconds
Started Feb 18 12:38:31 PM PST 24
Finished Feb 18 12:38:35 PM PST 24
Peak memory 248556 kb
Host smart-d1075b55-5a16-48ce-b190-97ad26737754
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3240761791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.3240761791
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.1414224696
Short name T49
Test name
Test status
Simulation time 602593477169 ps
CPU time 1922.42 seconds
Started Feb 18 12:38:57 PM PST 24
Finished Feb 18 01:11:04 PM PST 24
Peak memory 271820 kb
Host smart-24014814-47ae-4009-9dc1-f7ed4376f856
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414224696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.1414224696
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.2121598944
Short name T514
Test name
Test status
Simulation time 810103574 ps
CPU time 36.37 seconds
Started Feb 18 12:38:41 PM PST 24
Finished Feb 18 12:39:20 PM PST 24
Peak memory 240116 kb
Host smart-ec24e213-1662-4c8f-b1b0-10716aa07058
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2121598944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.2121598944
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.368907757
Short name T273
Test name
Test status
Simulation time 4206104086 ps
CPU time 216.27 seconds
Started Feb 18 12:38:33 PM PST 24
Finished Feb 18 12:42:11 PM PST 24
Peak memory 249284 kb
Host smart-41fdf285-ba1a-42ab-bddd-eacb8e722306
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36890
7757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.368907757
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.3764930737
Short name T535
Test name
Test status
Simulation time 7129932026 ps
CPU time 42.77 seconds
Started Feb 18 12:38:38 PM PST 24
Finished Feb 18 12:39:22 PM PST 24
Peak memory 247820 kb
Host smart-7eaf8b49-8532-41cb-8568-e6823d0adf75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37649
30737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.3764930737
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.572240613
Short name T502
Test name
Test status
Simulation time 41277884328 ps
CPU time 2363.53 seconds
Started Feb 18 12:38:39 PM PST 24
Finished Feb 18 01:18:05 PM PST 24
Peak memory 285940 kb
Host smart-19d1e1c7-6563-4f8d-97e3-321a4552a15c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572240613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.572240613
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.1688283103
Short name T698
Test name
Test status
Simulation time 175543978653 ps
CPU time 2587.46 seconds
Started Feb 18 12:38:41 PM PST 24
Finished Feb 18 01:21:52 PM PST 24
Peak memory 288808 kb
Host smart-07755e2c-f1d3-4bdf-8da7-a21f917a57fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688283103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.1688283103
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.4033132312
Short name T319
Test name
Test status
Simulation time 13895251925 ps
CPU time 580.26 seconds
Started Feb 18 12:38:44 PM PST 24
Finished Feb 18 12:48:29 PM PST 24
Peak memory 247184 kb
Host smart-98e9de0c-d528-48c7-bfc1-f16c52175f90
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033132312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.4033132312
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.3590068406
Short name T16
Test name
Test status
Simulation time 4594864454 ps
CPU time 66.24 seconds
Started Feb 18 12:38:34 PM PST 24
Finished Feb 18 12:39:43 PM PST 24
Peak memory 248380 kb
Host smart-150597ab-e726-4d32-a53f-fdaa63f10700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35900
68406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3590068406
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.2963587258
Short name T261
Test name
Test status
Simulation time 681270468 ps
CPU time 45.07 seconds
Started Feb 18 12:38:51 PM PST 24
Finished Feb 18 12:39:39 PM PST 24
Peak memory 254832 kb
Host smart-29964302-a8ee-419a-bbb2-32452188a588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29635
87258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.2963587258
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.2852705621
Short name T465
Test name
Test status
Simulation time 238072614 ps
CPU time 12.81 seconds
Started Feb 18 12:38:31 PM PST 24
Finished Feb 18 12:38:46 PM PST 24
Peak memory 248320 kb
Host smart-276ebb83-88a7-4811-a743-27195de15ddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28527
05621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.2852705621
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.2756378321
Short name T212
Test name
Test status
Simulation time 200922330 ps
CPU time 3.34 seconds
Started Feb 18 12:38:26 PM PST 24
Finished Feb 18 12:38:31 PM PST 24
Peak memory 248564 kb
Host smart-77abbeec-8067-4cf3-a9f9-a77669960575
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2756378321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.2756378321
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.3052938458
Short name T20
Test name
Test status
Simulation time 7946234524 ps
CPU time 917.07 seconds
Started Feb 18 12:38:48 PM PST 24
Finished Feb 18 12:54:09 PM PST 24
Peak memory 272976 kb
Host smart-dc44046b-3e0d-4150-97df-e168dca04e38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052938458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.3052938458
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.337325895
Short name T61
Test name
Test status
Simulation time 580408603 ps
CPU time 15.5 seconds
Started Feb 18 12:38:28 PM PST 24
Finished Feb 18 12:38:46 PM PST 24
Peak memory 240104 kb
Host smart-a87a6358-1df5-4ba5-bf03-9859a96706b3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=337325895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.337325895
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.4104575858
Short name T570
Test name
Test status
Simulation time 1717789762 ps
CPU time 48.99 seconds
Started Feb 18 12:38:46 PM PST 24
Finished Feb 18 12:39:39 PM PST 24
Peak memory 255468 kb
Host smart-4076a892-be8e-4a66-a666-ab35a3b473f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41045
75858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.4104575858
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.1538965212
Short name T524
Test name
Test status
Simulation time 1061512665 ps
CPU time 57.35 seconds
Started Feb 18 12:38:41 PM PST 24
Finished Feb 18 12:39:40 PM PST 24
Peak memory 254852 kb
Host smart-122b54d2-51a5-4f9d-b134-23540549fe3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15389
65212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.1538965212
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.389007344
Short name T534
Test name
Test status
Simulation time 58429400603 ps
CPU time 1408.38 seconds
Started Feb 18 12:38:36 PM PST 24
Finished Feb 18 01:02:07 PM PST 24
Peak memory 281004 kb
Host smart-94a9ca6b-96ff-49b1-96fa-38a787ecc55a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389007344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.389007344
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.1145263055
Short name T583
Test name
Test status
Simulation time 12019838553 ps
CPU time 1070.14 seconds
Started Feb 18 12:38:32 PM PST 24
Finished Feb 18 12:56:24 PM PST 24
Peak memory 272764 kb
Host smart-972fa953-bc97-4526-81b8-75714d78f67a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145263055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.1145263055
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.3059868485
Short name T311
Test name
Test status
Simulation time 12655732337 ps
CPU time 261.86 seconds
Started Feb 18 12:38:36 PM PST 24
Finished Feb 18 12:43:00 PM PST 24
Peak memory 248356 kb
Host smart-0537628f-37bd-4e19-b69e-b7a8a91d1f0b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059868485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.3059868485
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.3509438709
Short name T392
Test name
Test status
Simulation time 448493720 ps
CPU time 27.32 seconds
Started Feb 18 12:38:37 PM PST 24
Finished Feb 18 12:39:06 PM PST 24
Peak memory 255184 kb
Host smart-23f52675-d8a3-44c1-a086-6702a755d089
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35094
38709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3509438709
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.2376643514
Short name T654
Test name
Test status
Simulation time 151079012 ps
CPU time 4 seconds
Started Feb 18 12:38:44 PM PST 24
Finished Feb 18 12:38:56 PM PST 24
Peak memory 248796 kb
Host smart-07ec7274-f8e0-445a-845f-878f19108517
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23766
43514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.2376643514
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.1888017402
Short name T572
Test name
Test status
Simulation time 387386971 ps
CPU time 27.99 seconds
Started Feb 18 12:38:55 PM PST 24
Finished Feb 18 12:39:26 PM PST 24
Peak memory 254828 kb
Host smart-b78bc988-1a8f-415d-a9c6-7734b558dcef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18880
17402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.1888017402
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.209636868
Short name T233
Test name
Test status
Simulation time 140179432 ps
CPU time 14.21 seconds
Started Feb 18 12:38:32 PM PST 24
Finished Feb 18 12:38:48 PM PST 24
Peak memory 248336 kb
Host smart-cd72dfdf-edf7-47a4-ac48-3930f69a1859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20963
6868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.209636868
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.1118145293
Short name T113
Test name
Test status
Simulation time 122311883476 ps
CPU time 3570.7 seconds
Started Feb 18 12:38:38 PM PST 24
Finished Feb 18 01:38:10 PM PST 24
Peak memory 288752 kb
Host smart-aa06090a-c098-4059-a375-f378efd29c7f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118145293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.1118145293
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.1603936548
Short name T211
Test name
Test status
Simulation time 20391605 ps
CPU time 2.78 seconds
Started Feb 18 12:38:48 PM PST 24
Finished Feb 18 12:38:54 PM PST 24
Peak memory 248564 kb
Host smart-68e32d21-ec03-489b-a91a-9e282ff2d90f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1603936548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.1603936548
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.1389642759
Short name T601
Test name
Test status
Simulation time 49137360463 ps
CPU time 2557.26 seconds
Started Feb 18 12:38:28 PM PST 24
Finished Feb 18 01:21:08 PM PST 24
Peak memory 282996 kb
Host smart-d82db679-41c6-4e23-b3df-ac952246b05a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389642759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.1389642759
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.475540109
Short name T571
Test name
Test status
Simulation time 484005796 ps
CPU time 23.24 seconds
Started Feb 18 12:38:54 PM PST 24
Finished Feb 18 12:39:20 PM PST 24
Peak memory 240168 kb
Host smart-624ccf9b-c1cb-498b-aef2-44378c051069
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=475540109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.475540109
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.2606447508
Short name T365
Test name
Test status
Simulation time 3169190612 ps
CPU time 49.38 seconds
Started Feb 18 12:38:40 PM PST 24
Finished Feb 18 12:39:31 PM PST 24
Peak memory 255732 kb
Host smart-4aa866b8-871f-4ca4-aa80-3c6347d304a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26064
47508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.2606447508
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.448062587
Short name T525
Test name
Test status
Simulation time 504549804 ps
CPU time 12.35 seconds
Started Feb 18 12:38:43 PM PST 24
Finished Feb 18 12:38:59 PM PST 24
Peak memory 247904 kb
Host smart-0d0b1fef-9a45-4db6-8c5f-a09fbb358947
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44806
2587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.448062587
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.2228686558
Short name T651
Test name
Test status
Simulation time 111401933526 ps
CPU time 3204.4 seconds
Started Feb 18 12:38:37 PM PST 24
Finished Feb 18 01:32:04 PM PST 24
Peak memory 288800 kb
Host smart-244ab033-ae11-436c-b1bf-94464b67dc18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228686558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.2228686558
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.1566021628
Short name T499
Test name
Test status
Simulation time 29925313130 ps
CPU time 836.34 seconds
Started Feb 18 12:38:51 PM PST 24
Finished Feb 18 12:52:51 PM PST 24
Peak memory 272772 kb
Host smart-e87c1d2a-e2ca-4b95-a6a4-7dcedc1421d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566021628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.1566021628
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.958608394
Short name T312
Test name
Test status
Simulation time 17469188132 ps
CPU time 727.19 seconds
Started Feb 18 12:38:41 PM PST 24
Finished Feb 18 12:50:50 PM PST 24
Peak memory 247008 kb
Host smart-57e518fe-a2c5-4912-9038-5e8b7637f3d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958608394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.958608394
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.2360093253
Short name T637
Test name
Test status
Simulation time 2369542630 ps
CPU time 20.09 seconds
Started Feb 18 12:38:50 PM PST 24
Finished Feb 18 12:39:13 PM PST 24
Peak memory 248340 kb
Host smart-0d292caf-5afa-410d-a95f-1612ce41286b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23600
93253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.2360093253
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.3675721983
Short name T497
Test name
Test status
Simulation time 801369059 ps
CPU time 17.27 seconds
Started Feb 18 12:38:35 PM PST 24
Finished Feb 18 12:39:01 PM PST 24
Peak memory 247560 kb
Host smart-8b7bee6b-91d2-45bd-bb4f-9be53e90a14a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36757
21983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.3675721983
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.3487251496
Short name T683
Test name
Test status
Simulation time 20459517939 ps
CPU time 62.36 seconds
Started Feb 18 12:38:46 PM PST 24
Finished Feb 18 12:39:52 PM PST 24
Peak memory 255768 kb
Host smart-373d89c8-1ac1-442a-84bd-2d8135ae0a95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34872
51496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.3487251496
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.3351289093
Short name T414
Test name
Test status
Simulation time 221673371 ps
CPU time 12.98 seconds
Started Feb 18 12:38:35 PM PST 24
Finished Feb 18 12:38:50 PM PST 24
Peak memory 248552 kb
Host smart-48c2eaa8-7abb-4db2-a8b2-1745f514ee55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33512
89093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.3351289093
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.4138036491
Short name T56
Test name
Test status
Simulation time 4369664626 ps
CPU time 121.61 seconds
Started Feb 18 12:38:31 PM PST 24
Finished Feb 18 12:40:35 PM PST 24
Peak memory 256496 kb
Host smart-fe93569c-1f2b-4395-9914-caa813b02df3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138036491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.4138036491
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.3600231648
Short name T216
Test name
Test status
Simulation time 16826813 ps
CPU time 2.6 seconds
Started Feb 18 12:38:50 PM PST 24
Finished Feb 18 12:38:55 PM PST 24
Peak memory 248540 kb
Host smart-067bc679-a086-4ff5-bed9-4519bb0aec71
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3600231648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.3600231648
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.2539099860
Short name T124
Test name
Test status
Simulation time 28935727988 ps
CPU time 1926.99 seconds
Started Feb 18 12:38:39 PM PST 24
Finished Feb 18 01:10:48 PM PST 24
Peak memory 281704 kb
Host smart-b003f0e0-2114-4ef6-93be-b7eb034af75f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539099860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.2539099860
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.3446797459
Short name T618
Test name
Test status
Simulation time 409045438 ps
CPU time 8.55 seconds
Started Feb 18 12:38:39 PM PST 24
Finished Feb 18 12:38:50 PM PST 24
Peak memory 240212 kb
Host smart-dee0a2c9-41fa-4b6b-8d18-bc729deeabae
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3446797459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.3446797459
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.1403159544
Short name T599
Test name
Test status
Simulation time 376262622 ps
CPU time 31.77 seconds
Started Feb 18 12:38:53 PM PST 24
Finished Feb 18 12:39:27 PM PST 24
Peak memory 247924 kb
Host smart-543b6aaf-eca8-4771-9433-8a2d5c50fcd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14031
59544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.1403159544
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.1202036310
Short name T341
Test name
Test status
Simulation time 192141275171 ps
CPU time 1988.45 seconds
Started Feb 18 12:38:33 PM PST 24
Finished Feb 18 01:11:43 PM PST 24
Peak memory 272468 kb
Host smart-8c22bec9-67e8-4df4-8a4e-32ece4182d2e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202036310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.1202036310
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.3233679208
Short name T559
Test name
Test status
Simulation time 9848645411 ps
CPU time 1063.43 seconds
Started Feb 18 12:38:38 PM PST 24
Finished Feb 18 12:56:23 PM PST 24
Peak memory 287320 kb
Host smart-d48d9b0e-ceb6-4a11-8383-8df371c02ce6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233679208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.3233679208
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.2996667326
Short name T485
Test name
Test status
Simulation time 5293247330 ps
CPU time 203.67 seconds
Started Feb 18 12:39:11 PM PST 24
Finished Feb 18 12:42:42 PM PST 24
Peak memory 247116 kb
Host smart-d1656e3e-b137-4aa5-9ff9-1627b5a68fb2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996667326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.2996667326
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.3096952980
Short name T691
Test name
Test status
Simulation time 378821923 ps
CPU time 33.93 seconds
Started Feb 18 12:38:48 PM PST 24
Finished Feb 18 12:39:26 PM PST 24
Peak memory 248364 kb
Host smart-a1a52495-9256-474b-a8fa-95235ad6aabb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30969
52980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.3096952980
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.764683465
Short name T115
Test name
Test status
Simulation time 1320891383 ps
CPU time 24.86 seconds
Started Feb 18 12:38:47 PM PST 24
Finished Feb 18 12:39:16 PM PST 24
Peak memory 247812 kb
Host smart-fa4bb513-dad4-468b-b6d5-27e1b2190518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76468
3465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.764683465
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.3382804668
Short name T67
Test name
Test status
Simulation time 290049441 ps
CPU time 29.33 seconds
Started Feb 18 12:39:04 PM PST 24
Finished Feb 18 12:39:38 PM PST 24
Peak memory 248328 kb
Host smart-faac7e58-f651-4297-8fbe-3fc67f6e1e78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33828
04668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.3382804668
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.3692194644
Short name T664
Test name
Test status
Simulation time 114767584 ps
CPU time 11.1 seconds
Started Feb 18 12:39:04 PM PST 24
Finished Feb 18 12:39:20 PM PST 24
Peak memory 248404 kb
Host smart-8b78b0a3-b353-44c3-a9ed-057986d72813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36921
94644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.3692194644
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.2504349179
Short name T563
Test name
Test status
Simulation time 8818575568 ps
CPU time 446.22 seconds
Started Feb 18 12:38:47 PM PST 24
Finished Feb 18 12:46:17 PM PST 24
Peak memory 256584 kb
Host smart-1be508fd-980d-44cc-a47d-bc1adbe09456
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504349179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.2504349179
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.2402476091
Short name T260
Test name
Test status
Simulation time 183336469248 ps
CPU time 5261.91 seconds
Started Feb 18 12:38:38 PM PST 24
Finished Feb 18 02:06:22 PM PST 24
Peak memory 353904 kb
Host smart-4d942344-09f8-431d-9e89-5922e143fb38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402476091 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.2402476091
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.2825129947
Short name T224
Test name
Test status
Simulation time 34816525 ps
CPU time 3.1 seconds
Started Feb 18 12:38:41 PM PST 24
Finished Feb 18 12:38:45 PM PST 24
Peak memory 248628 kb
Host smart-f0a77ada-74a0-4beb-af7e-b19cfbb80d2a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2825129947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.2825129947
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.1609513399
Short name T48
Test name
Test status
Simulation time 16310408317 ps
CPU time 1294.36 seconds
Started Feb 18 12:38:47 PM PST 24
Finished Feb 18 01:00:25 PM PST 24
Peak memory 288228 kb
Host smart-99ff8680-ab00-4c92-b14d-c014e9af69de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609513399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.1609513399
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.1180329493
Short name T384
Test name
Test status
Simulation time 1853360524 ps
CPU time 13.02 seconds
Started Feb 18 12:38:43 PM PST 24
Finished Feb 18 12:39:00 PM PST 24
Peak memory 240084 kb
Host smart-57d8b98e-53f6-43c7-8795-f3e9e3baa1fc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1180329493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.1180329493
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.3585490642
Short name T492
Test name
Test status
Simulation time 8254176607 ps
CPU time 233.72 seconds
Started Feb 18 12:38:44 PM PST 24
Finished Feb 18 12:42:41 PM PST 24
Peak memory 250296 kb
Host smart-27684bfe-a346-470e-9e9c-37bba7f18ec9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35854
90642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.3585490642
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.3404313774
Short name T406
Test name
Test status
Simulation time 892983544 ps
CPU time 49.63 seconds
Started Feb 18 12:38:34 PM PST 24
Finished Feb 18 12:39:26 PM PST 24
Peak memory 254084 kb
Host smart-47a35f5b-d062-44b3-8877-c055f04c1282
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34043
13774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.3404313774
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.2502794379
Short name T337
Test name
Test status
Simulation time 54026944463 ps
CPU time 1007.38 seconds
Started Feb 18 12:38:50 PM PST 24
Finished Feb 18 12:55:41 PM PST 24
Peak memory 268260 kb
Host smart-98234f2f-a2cf-4fee-89b5-b6d3422d9708
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502794379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.2502794379
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.3695660393
Short name T605
Test name
Test status
Simulation time 92696812178 ps
CPU time 1506.27 seconds
Started Feb 18 12:38:46 PM PST 24
Finished Feb 18 01:03:56 PM PST 24
Peak memory 272336 kb
Host smart-b6d0b5d0-c808-44e8-9bd3-32781275573d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695660393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.3695660393
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.2465877604
Short name T547
Test name
Test status
Simulation time 7104056294 ps
CPU time 278.93 seconds
Started Feb 18 12:38:57 PM PST 24
Finished Feb 18 12:43:39 PM PST 24
Peak memory 247364 kb
Host smart-13038559-bad1-486c-b654-96bea41bb975
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465877604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.2465877604
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.2101960191
Short name T546
Test name
Test status
Simulation time 1634481222 ps
CPU time 25.78 seconds
Started Feb 18 12:38:53 PM PST 24
Finished Feb 18 12:39:21 PM PST 24
Peak memory 256548 kb
Host smart-cf828e2a-591f-423a-9542-e094fcc45a12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21019
60191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.2101960191
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.1406418000
Short name T378
Test name
Test status
Simulation time 227433680 ps
CPU time 15.92 seconds
Started Feb 18 12:38:46 PM PST 24
Finished Feb 18 12:39:06 PM PST 24
Peak memory 253972 kb
Host smart-f7f56500-2ff1-4a6a-b6a9-43df8a222336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14064
18000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.1406418000
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.2952329176
Short name T288
Test name
Test status
Simulation time 2855015657 ps
CPU time 39.41 seconds
Started Feb 18 12:39:03 PM PST 24
Finished Feb 18 12:39:45 PM PST 24
Peak memory 254736 kb
Host smart-e4e1bea0-5947-425b-bd5d-7ea007f1224f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29523
29176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.2952329176
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.126977630
Short name T410
Test name
Test status
Simulation time 206782087 ps
CPU time 7.36 seconds
Started Feb 18 12:38:53 PM PST 24
Finished Feb 18 12:39:03 PM PST 24
Peak memory 248316 kb
Host smart-14b09a77-37ef-405a-83e2-cffe879de773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12697
7630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.126977630
Directory /workspace/9.alert_handler_smoke/latest
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