Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	98531	1			T1	2		T3	5		T18	239
class_i[0x1]	56923	1			T1	3		T24	124		T30	3135
class_i[0x2]	50007	1			T1	1		T3	10		T6	2
class_i[0x3]	76223	1			T18	4		T39	5		T7	3

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	70454	1			T1	3		T3	10		T18	2
alert[0x1]	73013	1			T1	2		T3	4		T18	129
alert[0x2]	68049	1			T1	1		T3	1		T18	4
alert[0x3]	70168	1			T18	108		T39	271		T7	4

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

281410

1

T1

1

T3

15

T18

243

esc_ping_fail

274

1

T1

5

T6

2

T7

3

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	70372	1			T1	1		T3	10		T18	2
esc_integrity_fail	alert[0x1]	72949	1			T3	4		T18	129		T39	1
esc_integrity_fail	alert[0x2]	67983	1			T3	1		T18	4		T6	2
esc_integrity_fail	alert[0x3]	70106	1			T18	108		T39	271		T7	3
esc_ping_fail	alert[0x0]	82	1			T1	2		T6	1		T7	1
esc_ping_fail	alert[0x1]	64	1			T1	2		T295	1		T291	2
esc_ping_fail	alert[0x2]	66	1			T1	1		T6	1		T7	1
esc_ping_fail	alert[0x3]	62	1			T7	1		T295	3		T288	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	98458	1			T3	5		T18	239		T6	4
esc_integrity_fail	class_i[0x1]	56875	1			T1	1		T24	124		T30	3135
esc_integrity_fail	class_i[0x2]	49954	1			T3	10		T7	8		T24	40
esc_integrity_fail	class_i[0x3]	76123	1			T18	4		T39	5		T30	1
esc_ping_fail	class_i[0x0]	73	1			T1	2		T289	8		T87	1
esc_ping_fail	class_i[0x1]	48	1			T1	2		T87	2		T226	3
esc_ping_fail	class_i[0x2]	53	1			T1	1		T6	2		T295	8
esc_ping_fail	class_i[0x3]	100	1			T7	3		T291	5		T227	1