Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.74	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	5	35	87.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	5	35	87.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	43	1			T23	3		T42	1		T76	1
class_index[0x1]	54	1			T21	1		T22	2		T23	1
class_index[0x2]	61	1			T23	4		T70	2		T73	1
class_index[0x3]	83	1			T18	1		T22	1		T23	2

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	90	1			T21	1		T22	2		T23	4
intr_timeout_cnt[1]	65	1			T23	4		T43	1		T71	1
intr_timeout_cnt[2]	16	1			T22	1		T76	1		T48	1
intr_timeout_cnt[3]	16	1			T23	1		T73	1		T77	2
intr_timeout_cnt[4]	15	1			T44	1		T78	1		T83	1
intr_timeout_cnt[5]	8	1			T70	1		T102	2		T104	1
intr_timeout_cnt[6]	12	1			T18	1		T48	3		T81	1
intr_timeout_cnt[7]	14	1			T23	1		T49	1		T246	1
intr_timeout_cnt[8]	3	1			T49	1		T247	1		T248	1
intr_timeout_cnt[9]	2	1			T249	1		T250	1		-	-

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	5	35	87.50	5

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[5]]	0	1	1
[class_index[0x0]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[8]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	15	1			T23	2		T42	1		T73	3
class_index[0x0]	intr_timeout_cnt[1]	9	1			T251	1		T252	2		T253	5
class_index[0x0]	intr_timeout_cnt[2]	4	1			T76	1		T49	1		T254	1
class_index[0x0]	intr_timeout_cnt[3]	3	1			T80	1		T255	1		T192	1
class_index[0x0]	intr_timeout_cnt[4]	4	1			T44	1		T83	1		T57	1
class_index[0x0]	intr_timeout_cnt[6]	2	1			T85	1		T256	1		-	-
class_index[0x0]	intr_timeout_cnt[7]	5	1			T23	1		T49	1		T257	1
class_index[0x0]	intr_timeout_cnt[8]	1	1			T49	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	23	1			T21	1		T22	2		T23	1
class_index[0x1]	intr_timeout_cnt[1]	10	1			T43	1		T71	1		T72	1
class_index[0x1]	intr_timeout_cnt[2]	2	1			T258	1		T240	1		-	-
class_index[0x1]	intr_timeout_cnt[3]	5	1			T73	1		T259	1		T260	1
class_index[0x1]	intr_timeout_cnt[4]	8	1			T104	3		T261	1		T255	1
class_index[0x1]	intr_timeout_cnt[5]	3	1			T70	1		T102	1		T54	1
class_index[0x1]	intr_timeout_cnt[7]	1	1			T262	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	1	1			T247	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[9]	1	1			T249	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	21	1			T70	2		T73	1		T84	1
class_index[0x2]	intr_timeout_cnt[1]	19	1			T23	3		T78	1		T49	2
class_index[0x2]	intr_timeout_cnt[2]	2	1			T85	1		T256	1		-	-
class_index[0x2]	intr_timeout_cnt[3]	6	1			T23	1		T77	1		T263	1
class_index[0x2]	intr_timeout_cnt[4]	2	1			T78	1		T247	1		-	-
class_index[0x2]	intr_timeout_cnt[5]	2	1			T104	1		T264	1		-	-
class_index[0x2]	intr_timeout_cnt[6]	4	1			T81	1		T265	1		T266	1
class_index[0x2]	intr_timeout_cnt[7]	4	1			T246	1		T104	1		T192	1
class_index[0x2]	intr_timeout_cnt[8]	1	1			T248	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	31	1			T23	1		T42	2		T77	1
class_index[0x3]	intr_timeout_cnt[1]	27	1			T23	1		T73	2		T44	1
class_index[0x3]	intr_timeout_cnt[2]	8	1			T22	1		T48	1		T49	1
class_index[0x3]	intr_timeout_cnt[3]	2	1			T77	1		T246	1		-	-
class_index[0x3]	intr_timeout_cnt[4]	1	1			T267	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[5]	3	1			T102	1		T198	1		T192	1
class_index[0x3]	intr_timeout_cnt[6]	6	1			T18	1		T48	3		T268	1
class_index[0x3]	intr_timeout_cnt[7]	4	1			T264	1		T269	1		T192	1
class_index[0x3]	intr_timeout_cnt[9]	1	1			T250	1		-	-		-	-