Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	341369	1			T1	39		T2	911		T3	1161
all_values[1]	341369	1			T1	39		T2	911		T3	1161
all_values[2]	341369	1			T1	39		T2	911		T3	1161
all_values[3]	341369	1			T1	39		T2	911		T3	1161

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

678968

1

T2

1842

T3

2348

T15

26

auto[1]

686508

1

T1

156

T2

1802

T3

2296

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

820607

1

T1

136

T2

1838

T3

2621

auto[1]

544869

1

T1

20

T2

1806

T3

2023

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	99003	1			T2	232		T3	311		T15	2
all_values[0]	auto[0]	auto[1]	70905	1			T2	232		T3	283		T15	2
all_values[0]	auto[1]	auto[0]	100519	1			T1	37		T2	225		T3	293
all_values[0]	auto[1]	auto[1]	70942	1			T1	2		T2	222		T3	274
all_values[1]	auto[0]	auto[0]	102665	1			T2	240		T3	301		T15	5
all_values[1]	auto[0]	auto[1]	67041	1			T2	237		T3	297		T15	4
all_values[1]	auto[1]	auto[0]	104438	1			T1	35		T2	217		T3	292
all_values[1]	auto[1]	auto[1]	67225	1			T1	4		T2	217		T3	271
all_values[2]	auto[0]	auto[0]	102541	1			T2	242		T3	404		T15	2
all_values[2]	auto[0]	auto[1]	67071	1			T2	241		T3	175		T15	2
all_values[2]	auto[1]	auto[0]	104331	1			T1	25		T2	215		T3	412
all_values[2]	auto[1]	auto[1]	67426	1			T1	14		T2	213		T3	170
all_values[3]	auto[0]	auto[0]	102900	1			T2	214		T3	301		T15	5
all_values[3]	auto[0]	auto[1]	66842	1			T2	204		T3	276		T15	4
all_values[3]	auto[1]	auto[0]	104210	1			T1	39		T2	253		T3	307
all_values[3]	auto[1]	auto[1]	67417	1			T2	240		T3	277		T15	3