Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	341369	1			T1	39		T2	911		T3	1161
all_pins[1]	341369	1			T1	39		T2	911		T3	1161
all_pins[2]	341369	1			T1	39		T2	911		T3	1161
all_pins[3]	341369	1			T1	39		T2	911		T3	1161

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1092466	1			T1	136		T2	2752		T3	3652
values[0x1]	273010	1			T1	20		T2	892		T3	992
transitions[0x0=>0x1]	181952	1			T1	19		T2	564		T3	707
transitions[0x1=>0x0]	182206	1			T1	19		T2	565		T3	708

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	270427	1			T1	37		T2	689		T3	887
all_pins[0]	values[0x1]	70942	1			T1	2		T2	222		T3	274
all_pins[0]	transitions[0x0=>0x1]	70278	1			T1	2		T2	221		T3	273
all_pins[0]	transitions[0x1=>0x0]	67007	1			T2	240		T3	277		T15	3
all_pins[1]	values[0x0]	274144	1			T1	35		T2	694		T3	890
all_pins[1]	values[0x1]	67225	1			T1	4		T2	217		T3	271
all_pins[1]	transitions[0x0=>0x1]	37435	1			T1	3		T2	107		T3	154
all_pins[1]	transitions[0x1=>0x0]	41152	1			T1	1		T2	112		T3	157
all_pins[2]	values[0x0]	273943	1			T1	25		T2	698		T3	991
all_pins[2]	values[0x1]	67426	1			T1	14		T2	213		T3	170
all_pins[2]	transitions[0x0=>0x1]	37132	1			T1	14		T2	108		T3	92
all_pins[2]	transitions[0x1=>0x0]	36931	1			T1	4		T2	112		T3	193
all_pins[3]	values[0x0]	273952	1			T1	39		T2	671		T3	884
all_pins[3]	values[0x1]	67417	1			T2	240		T3	277		T15	3
all_pins[3]	transitions[0x0=>0x1]	37107	1			T2	128		T3	188		T15	2
all_pins[3]	transitions[0x1=>0x0]	37116	1			T1	14		T2	101		T3	81