Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	87156	1			T2	280		T3	182		T4	984
accum_cnt_1000	218955	1			T2	1574		T3	612		T4	1140
accum_cnt_100	24934	1			T2	99		T3	38		T4	58
accum_cnt_50	59606	1			T2	91		T3	27		T15	8
accum_cnt_10	177418	1			T2	35		T3	15		T15	30
accum_cnt_0	392686	1			T1	104		T2	709		T3	2602

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	252347	1			T1	26		T2	697		T3	869
class_index[0x1]	252347	1			T1	26		T2	697		T3	869
class_index[0x2]	252347	1			T1	26		T2	697		T3	869
class_index[0x3]	252347	1			T1	26		T2	697		T3	869

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	23388	1			T4	396		T86	508		T26	42
class_index[0x0]	accum_cnt_1000	56884	1			T4	402		T5	1085		T18	13
class_index[0x0]	accum_cnt_100	7609	1			T4	19		T16	8		T5	153
class_index[0x0]	accum_cnt_50	16669	1			T15	2		T4	18		T16	11
class_index[0x0]	accum_cnt_10	37076	1			T15	8		T4	5		T16	3
class_index[0x0]	accum_cnt_0	95926	1			T1	26		T2	697		T3	869
class_index[0x1]	accum_cnt_2000	23682	1			T2	136		T3	182		T14	540
class_index[0x1]	accum_cnt_1000	57423	1			T2	500		T3	612		T21	6
class_index[0x1]	accum_cnt_100	5955	1			T2	29		T3	38		T21	20
class_index[0x1]	accum_cnt_50	10954	1			T2	23		T3	26		T15	2
class_index[0x1]	accum_cnt_10	55277	1			T2	7		T3	9		T15	6
class_index[0x1]	accum_cnt_0	87498	1			T1	26		T2	2		T3	2
class_index[0x2]	accum_cnt_2000	22937	1			T2	144		T4	588		T14	540
class_index[0x2]	accum_cnt_1000	57824	1			T2	476		T4	738		T21	3
class_index[0x2]	accum_cnt_100	5982	1			T2	27		T4	39		T21	25
class_index[0x2]	accum_cnt_50	19335	1			T2	27		T4	32		T18	12
class_index[0x2]	accum_cnt_10	35881	1			T2	15		T3	3		T15	10
class_index[0x2]	accum_cnt_0	98320	1			T1	26		T2	8		T3	866
class_index[0x3]	accum_cnt_2000	17149	1			T36	327		T100	514		T44	212
class_index[0x3]	accum_cnt_1000	46824	1			T2	598		T21	9		T11	1069
class_index[0x3]	accum_cnt_100	5388	1			T2	43		T21	21		T11	83
class_index[0x3]	accum_cnt_50	12648	1			T2	41		T3	1		T15	4
class_index[0x3]	accum_cnt_10	49184	1			T2	13		T3	3		T15	6
class_index[0x3]	accum_cnt_0	110942	1			T1	26		T2	2		T3	865