Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	5828	1			T18	3		T30	2		T70	90
alert[0x1]	5518	1			T24	192		T74	489		T78	28
alert[0x2]	11298	1			T1	1		T24	3		T43	109
alert[0x3]	8631	1			T42	17		T70	17		T44	44
alert[0x4]	5909	1			T43	49		T288	1		T96	1
alert[0x5]	5205	1			T24	60		T42	1		T43	14
alert[0x6]	6470	1			T1	2		T11	1		T7	1
alert[0x7]	3188	1			T3	9		T7	1		T42	39
alert[0x8]	6301	1			T24	48		T42	4		T43	18
alert[0x9]	5518	1			T1	1		T7	1		T42	32
alert[0xa]	2551	1			T72	5		T74	2		T78	21
alert[0xb]	5091	1			T18	5		T24	12		T42	18
alert[0xc]	4569	1			T6	1		T24	84		T70	18
alert[0xd]	5153	1			T1	1		T70	1		T44	31
alert[0xe]	4167	1			T24	174		T42	186		T43	4
alert[0xf]	5150	1			T18	7		T7	1		T70	129
alert[0x10]	7515	1			T24	3		T78	17		T289	1
alert[0x11]	6395	1			T24	33		T70	1		T78	10
alert[0x12]	8312	1			T7	1		T70	7		T73	1
alert[0x13]	3366	1			T11	1		T290	32		T289	1
alert[0x14]	6889	1			T3	1		T7	1		T70	2
alert[0x15]	2813	1			T7	1		T67	4		T43	9
alert[0x16]	8075	1			T7	1		T24	93		T44	341
alert[0x17]	4968	1			T1	1		T43	10		T70	9
alert[0x18]	4829	1			T1	1		T6	1		T78	12
alert[0x19]	2608	1			T42	19		T73	4		T74	14
alert[0x1a]	4384	1			T1	1		T18	1		T24	68
alert[0x1b]	9883	1			T7	1		T24	41		T36	1
alert[0x1c]	9586	1			T30	1		T70	455		T73	6
alert[0x1d]	3185	1			T1	1		T24	6		T30	1
alert[0x1e]	2593	1			T24	9		T22	1		T43	50
alert[0x1f]	3298	1			T5	1		T70	14		T44	18
alert[0x20]	3612	1			T42	2		T73	2		T44	77
alert[0x21]	6352	1			T24	17		T43	6		T290	1
alert[0x22]	12260	1			T5	1		T41	1		T24	63
alert[0x23]	4600	1			T1	1		T43	14		T77	24
alert[0x24]	2726	1			T77	11		T290	77		T288	1
alert[0x25]	12034	1			T18	50		T42	573		T44	365
alert[0x26]	9418	1			T24	108		T43	8		T70	4
alert[0x27]	5867	1			T24	18		T30	11		T42	6
alert[0x28]	6174	1			T7	1		T24	2		T36	1
alert[0x29]	11160	1			T7	1		T24	17		T30	2
alert[0x2a]	5366	1			T6	1		T24	45		T43	1
alert[0x2b]	1837	1			T40	1		T70	37		T44	48
alert[0x2c]	4911	1			T11	1		T41	1		T70	644
alert[0x2d]	6264	1			T42	5		T70	3		T74	8
alert[0x2e]	7841	1			T78	16		T290	52		T288	1
alert[0x2f]	2967	1			T42	19		T288	1		T96	3
alert[0x30]	5772	1			T24	15		T67	1		T44	288
alert[0x31]	6110	1			T24	52		T70	15		T73	10
alert[0x32]	6083	1			T42	7		T43	8		T70	349
alert[0x33]	8039	1			T1	1		T42	5		T71	2
alert[0x34]	5774	1			T24	15		T42	7		T43	12
alert[0x35]	4487	1			T1	1		T18	1		T24	4
alert[0x36]	3517	1			T24	8		T43	8		T70	33
alert[0x37]	4383	1			T42	171		T70	8		T44	406
alert[0x38]	1610	1			T42	18		T43	38		T70	6
alert[0x39]	2043	1			T7	1		T24	8		T70	9
alert[0x3a]	10562	1			T71	1		T44	363		T290	869
alert[0x3b]	4008	1			T1	1		T24	321		T70	4
alert[0x3c]	5971	1			T24	170		T30	3		T42	24
alert[0x3d]	9086	1			T24	143		T42	121		T290	2
alert[0x3e]	6093	1			T1	1		T7	1		T24	15
alert[0x3f]	3900	1			T24	66		T71	1		T73	57
alert[0x40]	14170	1			T18	92		T24	3		T43	3

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	58386	1			T5	2		T18	113		T6	1
class_i[0x1]	106596	1			T1	1		T6	2		T7	2
class_i[0x2]	97816	1			T1	13		T18	46		T7	11
class_i[0x3]	121445	1			T3	10		T41	2		T24	1203

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

383556

1

T3

10

T18

159

T24

1916

alert_ping_fail

687

1

T1

14

T5

2

T6

3

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	5818	1			T18	3		T30	2		T70	90
alert_integrity_fail	alert[0x1]	5508	1			T24	192		T74	489		T78	28
alert_integrity_fail	alert[0x2]	11289	1			T24	3		T43	109		T70	14
alert_integrity_fail	alert[0x3]	8623	1			T42	17		T70	17		T44	44
alert_integrity_fail	alert[0x4]	5899	1			T43	49		T96	1		T50	12
alert_integrity_fail	alert[0x5]	5187	1			T24	60		T42	1		T43	14
alert_integrity_fail	alert[0x6]	6450	1			T71	16		T78	31		T91	2
alert_integrity_fail	alert[0x7]	3176	1			T3	9		T42	39		T43	70
alert_integrity_fail	alert[0x8]	6287	1			T24	48		T42	4		T43	18
alert_integrity_fail	alert[0x9]	5513	1			T42	32		T44	1673		T79	1
alert_integrity_fail	alert[0xa]	2539	1			T72	5		T74	2		T78	21
alert_integrity_fail	alert[0xb]	5080	1			T18	5		T24	12		T42	18
alert_integrity_fail	alert[0xc]	4557	1			T24	84		T70	18		T80	1
alert_integrity_fail	alert[0xd]	5143	1			T70	1		T44	31		T74	103
alert_integrity_fail	alert[0xe]	4157	1			T24	174		T42	186		T43	4
alert_integrity_fail	alert[0xf]	5140	1			T18	7		T70	129		T73	9
alert_integrity_fail	alert[0x10]	7510	1			T24	3		T78	17		T97	3
alert_integrity_fail	alert[0x11]	6388	1			T24	33		T70	1		T78	10
alert_integrity_fail	alert[0x12]	8305	1			T70	7		T73	1		T44	576
alert_integrity_fail	alert[0x13]	3351	1			T290	32		T80	4		T101	1949
alert_integrity_fail	alert[0x14]	6876	1			T3	1		T70	2		T78	31
alert_integrity_fail	alert[0x15]	2797	1			T67	4		T43	9		T73	1
alert_integrity_fail	alert[0x16]	8066	1			T24	93		T44	341		T74	56
alert_integrity_fail	alert[0x17]	4958	1			T43	10		T70	9		T73	3
alert_integrity_fail	alert[0x18]	4817	1			T78	12		T97	343		T50	808
alert_integrity_fail	alert[0x19]	2599	1			T42	19		T73	4		T74	14
alert_integrity_fail	alert[0x1a]	4369	1			T18	1		T24	68		T30	1
alert_integrity_fail	alert[0x1b]	9869	1			T24	41		T42	286		T43	688
alert_integrity_fail	alert[0x1c]	9576	1			T30	1		T70	455		T73	6
alert_integrity_fail	alert[0x1d]	3170	1			T24	6		T30	1		T42	7
alert_integrity_fail	alert[0x1e]	2588	1			T24	9		T22	1		T43	50
alert_integrity_fail	alert[0x1f]	3280	1			T70	14		T44	18		T74	1
alert_integrity_fail	alert[0x20]	3602	1			T42	2		T73	2		T44	77
alert_integrity_fail	alert[0x21]	6337	1			T24	17		T43	6		T290	1
alert_integrity_fail	alert[0x22]	12249	1			T24	63		T44	695		T101	17
alert_integrity_fail	alert[0x23]	4589	1			T43	14		T77	24		T74	5
alert_integrity_fail	alert[0x24]	2721	1			T77	11		T290	77		T97	174
alert_integrity_fail	alert[0x25]	12027	1			T18	50		T42	573		T44	365
alert_integrity_fail	alert[0x26]	9410	1			T24	108		T43	8		T70	4
alert_integrity_fail	alert[0x27]	5854	1			T24	18		T30	11		T42	6
alert_integrity_fail	alert[0x28]	6163	1			T24	2		T43	9		T70	2
alert_integrity_fail	alert[0x29]	11150	1			T24	17		T30	2		T42	64
alert_integrity_fail	alert[0x2a]	5346	1			T24	45		T43	1		T71	1
alert_integrity_fail	alert[0x2b]	1823	1			T70	37		T44	48		T74	6
alert_integrity_fail	alert[0x2c]	4900	1			T70	644		T71	1		T72	29
alert_integrity_fail	alert[0x2d]	6250	1			T42	5		T70	3		T74	8
alert_integrity_fail	alert[0x2e]	7832	1			T78	16		T290	52		T97	1800
alert_integrity_fail	alert[0x2f]	2956	1			T42	19		T96	3		T97	31
alert_integrity_fail	alert[0x30]	5761	1			T24	15		T67	1		T44	288
alert_integrity_fail	alert[0x31]	6099	1			T24	52		T70	15		T73	10
alert_integrity_fail	alert[0x32]	6076	1			T42	7		T43	8		T70	349
alert_integrity_fail	alert[0x33]	8025	1			T42	5		T71	2		T74	160
alert_integrity_fail	alert[0x34]	5768	1			T24	15		T42	7		T43	12
alert_integrity_fail	alert[0x35]	4473	1			T18	1		T24	4		T73	2
alert_integrity_fail	alert[0x36]	3506	1			T24	8		T43	8		T70	33
alert_integrity_fail	alert[0x37]	4378	1			T42	171		T70	8		T44	406
alert_integrity_fail	alert[0x38]	1604	1			T42	18		T43	38		T70	6
alert_integrity_fail	alert[0x39]	2027	1			T24	8		T70	9		T71	9
alert_integrity_fail	alert[0x3a]	10551	1			T71	1		T44	363		T290	869
alert_integrity_fail	alert[0x3b]	3999	1			T24	321		T70	4		T44	847
alert_integrity_fail	alert[0x3c]	5966	1			T24	170		T30	3		T42	24
alert_integrity_fail	alert[0x3d]	9080	1			T24	143		T42	121		T290	2
alert_integrity_fail	alert[0x3e]	6085	1			T24	15		T42	60		T43	4
alert_integrity_fail	alert[0x3f]	3898	1			T24	66		T71	1		T73	57
alert_integrity_fail	alert[0x40]	14166	1			T18	92		T24	3		T43	3
alert_ping_fail	alert[0x0]	10	1			T291	1		T292	1		T293	1
alert_ping_fail	alert[0x1]	10	1			T288	1		T292	3		T294	1
alert_ping_fail	alert[0x2]	9	1			T1	1		T295	1		T296	1
alert_ping_fail	alert[0x3]	8	1			T289	1		T87	1		T297	1
alert_ping_fail	alert[0x4]	10	1			T288	1		T298	1		T292	1
alert_ping_fail	alert[0x5]	18	1			T295	1		T288	1		T87	1
alert_ping_fail	alert[0x6]	20	1			T1	2		T11	1		T7	1
alert_ping_fail	alert[0x7]	12	1			T7	1		T111	1		T288	1
alert_ping_fail	alert[0x8]	14	1			T288	1		T299	1		T300	1
alert_ping_fail	alert[0x9]	5	1			T1	1		T7	1		T295	1
alert_ping_fail	alert[0xa]	12	1			T187	1		T295	1		T291	1
alert_ping_fail	alert[0xb]	11	1			T291	1		T87	1		T292	1
alert_ping_fail	alert[0xc]	12	1			T6	1		T295	1		T288	1
alert_ping_fail	alert[0xd]	10	1			T1	1		T289	1		T301	1
alert_ping_fail	alert[0xe]	10	1			T226	1		T298	1		T293	1
alert_ping_fail	alert[0xf]	10	1			T7	1		T294	1		T302	1
alert_ping_fail	alert[0x10]	5	1			T289	1		T227	1		T294	1
alert_ping_fail	alert[0x11]	7	1			T288	1		T289	1		T87	1
alert_ping_fail	alert[0x12]	7	1			T7	1		T295	1		T303	1
alert_ping_fail	alert[0x13]	15	1			T11	1		T289	1		T300	1
alert_ping_fail	alert[0x14]	13	1			T7	1		T111	1		T291	1
alert_ping_fail	alert[0x15]	16	1			T7	1		T182	1		T304	1
alert_ping_fail	alert[0x16]	9	1			T7	1		T87	1		T305	1
alert_ping_fail	alert[0x17]	10	1			T1	1		T295	1		T226	1
alert_ping_fail	alert[0x18]	12	1			T1	1		T6	1		T292	1
alert_ping_fail	alert[0x19]	9	1			T87	1		T301	1		T306	1
alert_ping_fail	alert[0x1a]	15	1			T1	1		T298	1		T292	1
alert_ping_fail	alert[0x1b]	14	1			T7	1		T36	1		T295	1
alert_ping_fail	alert[0x1c]	10	1			T295	1		T293	1		T301	1
alert_ping_fail	alert[0x1d]	15	1			T1	1		T295	1		T87	1
alert_ping_fail	alert[0x1e]	5	1			T288	1		T87	1		T305	1
alert_ping_fail	alert[0x1f]	18	1			T5	1		T288	1		T289	1
alert_ping_fail	alert[0x20]	10	1			T301	1		T307	1		T308	1
alert_ping_fail	alert[0x21]	15	1			T289	1		T309	2		T310	1
alert_ping_fail	alert[0x22]	11	1			T5	1		T41	1		T184	1
alert_ping_fail	alert[0x23]	11	1			T1	1		T295	1		T87	1
alert_ping_fail	alert[0x24]	5	1			T288	1		T294	1		T311	1
alert_ping_fail	alert[0x25]	7	1			T87	1		T294	1		T311	1
alert_ping_fail	alert[0x26]	8	1			T289	1		T87	1		T302	1
alert_ping_fail	alert[0x27]	13	1			T288	1		T305	1		T293	1
alert_ping_fail	alert[0x28]	11	1			T7	1		T36	1		T288	1
alert_ping_fail	alert[0x29]	10	1			T7	1		T289	1		T312	1
alert_ping_fail	alert[0x2a]	20	1			T6	1		T182	1		T288	2
alert_ping_fail	alert[0x2b]	14	1			T40	1		T288	1		T313	1
alert_ping_fail	alert[0x2c]	11	1			T11	1		T41	1		T295	1
alert_ping_fail	alert[0x2d]	14	1			T87	1		T292	1		T304	1
alert_ping_fail	alert[0x2e]	9	1			T288	1		T293	1		T294	1
alert_ping_fail	alert[0x2f]	11	1			T288	1		T298	1		T301	1
alert_ping_fail	alert[0x30]	11	1			T288	1		T287	1		T302	1
alert_ping_fail	alert[0x31]	11	1			T288	1		T293	1		T302	1
alert_ping_fail	alert[0x32]	7	1			T305	1		T314	1		T315	1
alert_ping_fail	alert[0x33]	14	1			T1	1		T295	1		T288	1
alert_ping_fail	alert[0x34]	6	1			T301	1		T297	1		T314	1
alert_ping_fail	alert[0x35]	14	1			T1	1		T226	1		T227	1
alert_ping_fail	alert[0x36]	11	1			T295	1		T301	1		T297	1
alert_ping_fail	alert[0x37]	5	1			T227	1		T294	1		T296	1
alert_ping_fail	alert[0x38]	6	1			T288	1		T305	1		T298	1
alert_ping_fail	alert[0x39]	16	1			T7	1		T295	1		T289	1
alert_ping_fail	alert[0x3a]	11	1			T288	1		T291	1		T305	1
alert_ping_fail	alert[0x3b]	9	1			T1	1		T316	1		T308	1
alert_ping_fail	alert[0x3c]	5	1			T295	1		T288	1		T87	1
alert_ping_fail	alert[0x3d]	6	1			T311	2		T317	1		T315	1
alert_ping_fail	alert[0x3e]	8	1			T1	1		T7	1		T295	1
alert_ping_fail	alert[0x3f]	2	1			T308	1		T317	1		-	-
alert_ping_fail	alert[0x40]	4	1			T295	1		T301	1		T318	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	58191	1			T18	113		T24	675		T42	1593
alert_integrity_fail	class_i[0x1]	106451	1			T24	11		T30	5		T67	5
alert_integrity_fail	class_i[0x2]	97669	1			T18	46		T24	27		T70	1828
alert_integrity_fail	class_i[0x3]	121245	1			T3	10		T24	1203		T30	16
alert_ping_fail	class_i[0x0]	195	1			T5	2		T6	1		T11	3
alert_ping_fail	class_i[0x1]	145	1			T1	1		T6	2		T7	2
alert_ping_fail	class_i[0x2]	147	1			T1	13		T7	11		T36	2
alert_ping_fail	class_i[0x3]	200	1			T41	2		T111	2		T295	1