Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.64 99.99 98.72 99.97 100.00 100.00 99.38 99.44


Total test records in report: 828
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T772 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.3818098180 Mar 12 12:58:38 PM PDT 24 Mar 12 12:58:40 PM PDT 24 6388539 ps
T773 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2457438282 Mar 12 12:58:09 PM PDT 24 Mar 12 12:58:22 PM PDT 24 173804480 ps
T774 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.1288863232 Mar 12 12:58:26 PM PDT 24 Mar 12 12:58:27 PM PDT 24 14451154 ps
T775 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.810612125 Mar 12 12:58:27 PM PDT 24 Mar 12 12:58:30 PM PDT 24 18523527 ps
T776 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.884910362 Mar 12 12:58:17 PM PDT 24 Mar 12 12:58:55 PM PDT 24 608438003 ps
T777 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.3594969526 Mar 12 12:58:09 PM PDT 24 Mar 12 12:58:13 PM PDT 24 35547035 ps
T149 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1745924392 Mar 12 12:58:05 PM PDT 24 Mar 12 01:03:13 PM PDT 24 2244315894 ps
T778 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1648003404 Mar 12 12:58:26 PM PDT 24 Mar 12 12:58:36 PM PDT 24 174199819 ps
T779 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1265652999 Mar 12 12:58:27 PM PDT 24 Mar 12 12:58:47 PM PDT 24 411487561 ps
T780 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2726166224 Mar 12 12:58:08 PM PDT 24 Mar 12 01:01:30 PM PDT 24 1704558051 ps
T137 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1756575966 Mar 12 12:58:06 PM PDT 24 Mar 12 01:03:14 PM PDT 24 8882608881 ps
T781 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1777521986 Mar 12 12:58:10 PM PDT 24 Mar 12 12:58:21 PM PDT 24 323420061 ps
T782 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.3202790245 Mar 12 12:58:24 PM PDT 24 Mar 12 12:58:26 PM PDT 24 43823634 ps
T783 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2661434802 Mar 12 12:58:05 PM PDT 24 Mar 12 01:04:02 PM PDT 24 11453886246 ps
T135 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.767846567 Mar 12 12:58:18 PM PDT 24 Mar 12 01:00:52 PM PDT 24 8659922530 ps
T784 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1460445357 Mar 12 12:58:06 PM PDT 24 Mar 12 12:58:13 PM PDT 24 186646435 ps
T785 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.537068312 Mar 12 12:58:17 PM PDT 24 Mar 12 12:58:41 PM PDT 24 350197286 ps
T786 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2063091706 Mar 12 12:58:18 PM PDT 24 Mar 12 12:58:20 PM PDT 24 7563799 ps
T148 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.295929603 Mar 12 12:58:06 PM PDT 24 Mar 12 01:01:35 PM PDT 24 7555674951 ps
T787 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.1677173014 Mar 12 12:58:10 PM PDT 24 Mar 12 12:58:21 PM PDT 24 92540613 ps
T788 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.1398831813 Mar 12 12:58:48 PM PDT 24 Mar 12 12:58:50 PM PDT 24 22868840 ps
T152 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3521477867 Mar 12 12:58:26 PM PDT 24 Mar 12 01:01:07 PM PDT 24 2101025575 ps
T789 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1038054999 Mar 12 12:58:06 PM PDT 24 Mar 12 12:58:11 PM PDT 24 137807243 ps
T168 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3118115118 Mar 12 12:58:09 PM PDT 24 Mar 12 12:58:53 PM PDT 24 2614463223 ps
T790 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3293069520 Mar 12 12:58:08 PM PDT 24 Mar 12 01:02:17 PM PDT 24 3257575616 ps
T791 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.393953156 Mar 12 12:58:05 PM PDT 24 Mar 12 12:58:06 PM PDT 24 6774458 ps
T792 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.357644212 Mar 12 12:58:08 PM PDT 24 Mar 12 12:58:09 PM PDT 24 87181017 ps
T793 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.2728820126 Mar 12 12:58:10 PM PDT 24 Mar 12 12:58:16 PM PDT 24 33874422 ps
T794 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3471627101 Mar 12 12:58:24 PM PDT 24 Mar 12 12:58:32 PM PDT 24 379594272 ps
T170 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3241334795 Mar 12 12:58:09 PM PDT 24 Mar 12 12:58:13 PM PDT 24 39191792 ps
T150 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3714361 Mar 12 12:58:09 PM PDT 24 Mar 12 01:05:52 PM PDT 24 25266691460 ps
T795 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.1046759085 Mar 12 12:58:10 PM PDT 24 Mar 12 12:58:12 PM PDT 24 20780318 ps
T796 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.1028242315 Mar 12 12:58:30 PM PDT 24 Mar 12 12:58:31 PM PDT 24 7771725 ps
T797 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.582837717 Mar 12 12:58:18 PM PDT 24 Mar 12 12:58:28 PM PDT 24 1024292059 ps
T798 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.2162255967 Mar 12 12:58:13 PM PDT 24 Mar 12 12:58:17 PM PDT 24 20196341 ps
T164 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.93944018 Mar 12 12:58:18 PM PDT 24 Mar 12 12:58:23 PM PDT 24 185387264 ps
T156 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2101473429 Mar 12 12:58:27 PM PDT 24 Mar 12 01:18:26 PM PDT 24 67441365819 ps
T344 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2515988750 Mar 12 12:58:08 PM PDT 24 Mar 12 01:07:25 PM PDT 24 8309363455 ps
T799 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.3784233577 Mar 12 12:58:10 PM PDT 24 Mar 12 12:58:12 PM PDT 24 9593561 ps
T165 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.3193125207 Mar 12 12:58:08 PM PDT 24 Mar 12 12:58:11 PM PDT 24 35767829 ps
T800 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2984770912 Mar 12 12:58:08 PM PDT 24 Mar 12 12:58:13 PM PDT 24 180955743 ps
T151 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.222774628 Mar 12 12:58:26 PM PDT 24 Mar 12 01:06:24 PM PDT 24 6205762076 ps
T801 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2219937747 Mar 12 12:58:09 PM PDT 24 Mar 12 12:58:10 PM PDT 24 12078871 ps
T802 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.4018179211 Mar 12 12:58:27 PM PDT 24 Mar 12 12:58:32 PM PDT 24 34743134 ps
T803 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.4158898936 Mar 12 12:58:26 PM PDT 24 Mar 12 12:58:27 PM PDT 24 10945579 ps
T804 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2581475650 Mar 12 12:58:09 PM PDT 24 Mar 12 12:58:16 PM PDT 24 46366858 ps
T166 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.1385586293 Mar 12 12:58:15 PM PDT 24 Mar 12 12:59:22 PM PDT 24 1847743434 ps
T141 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3332109692 Mar 12 12:58:09 PM PDT 24 Mar 12 01:09:16 PM PDT 24 4567856896 ps
T155 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1311427615 Mar 12 12:58:19 PM PDT 24 Mar 12 01:03:44 PM PDT 24 34350695306 ps
T805 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.3677635605 Mar 12 12:58:26 PM PDT 24 Mar 12 12:58:29 PM PDT 24 36749188 ps
T806 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2184341424 Mar 12 12:58:17 PM PDT 24 Mar 12 12:58:22 PM PDT 24 264986559 ps
T807 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2052325701 Mar 12 12:58:14 PM PDT 24 Mar 12 12:58:27 PM PDT 24 176531220 ps
T808 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.1558081471 Mar 12 12:58:13 PM PDT 24 Mar 12 12:58:34 PM PDT 24 1407757752 ps
T809 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.3720670453 Mar 12 12:58:28 PM PDT 24 Mar 12 12:58:29 PM PDT 24 6369957 ps
T810 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.145304097 Mar 12 12:58:20 PM PDT 24 Mar 12 12:58:27 PM PDT 24 1912997840 ps
T811 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2414602881 Mar 12 12:58:28 PM PDT 24 Mar 12 12:58:33 PM PDT 24 257454878 ps
T812 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.3721319526 Mar 12 12:58:11 PM PDT 24 Mar 12 12:58:29 PM PDT 24 287333961 ps
T813 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.2787738371 Mar 12 12:58:06 PM PDT 24 Mar 12 12:58:28 PM PDT 24 1487318690 ps
T814 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.4095202721 Mar 12 12:58:30 PM PDT 24 Mar 12 12:58:31 PM PDT 24 15168652 ps
T815 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.2459110994 Mar 12 12:58:04 PM PDT 24 Mar 12 12:58:13 PM PDT 24 491371489 ps
T178 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.450245848 Mar 12 12:58:27 PM PDT 24 Mar 12 12:58:30 PM PDT 24 30093473 ps
T171 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.562428619 Mar 12 12:58:07 PM PDT 24 Mar 12 12:59:15 PM PDT 24 1769049224 ps
T816 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2817374099 Mar 12 12:58:22 PM PDT 24 Mar 12 12:58:24 PM PDT 24 55148506 ps
T817 /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3042661348 Mar 12 12:58:09 PM PDT 24 Mar 12 01:05:23 PM PDT 24 7710347294 ps
T818 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3282613578 Mar 12 12:58:16 PM PDT 24 Mar 12 12:58:24 PM PDT 24 98703723 ps
T819 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3585906616 Mar 12 12:58:25 PM PDT 24 Mar 12 12:58:44 PM PDT 24 501908418 ps
T142 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3992037264 Mar 12 12:58:10 PM PDT 24 Mar 12 01:06:57 PM PDT 24 4467981181 ps
T820 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3866426951 Mar 12 12:58:09 PM PDT 24 Mar 12 12:58:23 PM PDT 24 357534965 ps
T821 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3621897750 Mar 12 12:58:10 PM PDT 24 Mar 12 12:58:26 PM PDT 24 222305055 ps
T822 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.3475155859 Mar 12 12:58:09 PM PDT 24 Mar 12 12:58:15 PM PDT 24 128084886 ps
T163 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3720609552 Mar 12 12:57:59 PM PDT 24 Mar 12 12:59:11 PM PDT 24 3720207455 ps
T823 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.949637309 Mar 12 12:58:18 PM PDT 24 Mar 12 12:58:19 PM PDT 24 15187562 ps
T824 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2329148025 Mar 12 12:58:17 PM PDT 24 Mar 12 12:58:22 PM PDT 24 52847663 ps
T825 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.3264550805 Mar 12 12:58:26 PM PDT 24 Mar 12 12:58:29 PM PDT 24 12296494 ps
T826 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.2217145853 Mar 12 12:58:15 PM PDT 24 Mar 12 12:58:21 PM PDT 24 266338134 ps
T827 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.1766784724 Mar 12 12:58:06 PM PDT 24 Mar 12 01:00:27 PM PDT 24 4754241809 ps
T828 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.117286499 Mar 12 12:58:16 PM PDT 24 Mar 12 12:58:22 PM PDT 24 465736667 ps
T153 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.325115438 Mar 12 12:58:04 PM PDT 24 Mar 12 12:59:34 PM PDT 24 2899197761 ps

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.1110028318
Short name T2
Test name
Test status
Simulation time 178834515597 ps
CPU time 1247.63 seconds
Started Mar 12 01:39:15 PM PDT 24
Finished Mar 12 02:00:07 PM PDT 24
Peak memory 272756 kb
Host smart-80474898-d455-4c38-ae35-e3f57cbb7f6d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110028318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.1110028318
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.2598163274
Short name T24
Test name
Test status
Simulation time 123457130095 ps
CPU time 2597.87 seconds
Started Mar 12 01:40:37 PM PDT 24
Finished Mar 12 02:23:56 PM PDT 24
Peak memory 321848 kb
Host smart-2fd4f775-ee08-44ec-93ef-365b3298924f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598163274 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.2598163274
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.2808071118
Short name T9
Test name
Test status
Simulation time 342455543 ps
CPU time 25.33 seconds
Started Mar 12 01:39:06 PM PDT 24
Finished Mar 12 01:39:31 PM PDT 24
Peak memory 276756 kb
Host smart-514c7059-9b8c-4ca9-86fc-622383655b59
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2808071118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.2808071118
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.1690467568
Short name T21
Test name
Test status
Simulation time 2914815853 ps
CPU time 184.09 seconds
Started Mar 12 01:40:05 PM PDT 24
Finished Mar 12 01:43:09 PM PDT 24
Peak memory 256760 kb
Host smart-f5d6854b-1a8e-4d69-be0f-d898bfe42556
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690467568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.1690467568
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.1953786700
Short name T73
Test name
Test status
Simulation time 70205947804 ps
CPU time 2442.68 seconds
Started Mar 12 01:39:33 PM PDT 24
Finished Mar 12 02:20:16 PM PDT 24
Peak memory 282604 kb
Host smart-62ed08b0-0762-43e4-a831-66c5e81ed653
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953786700 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.1953786700
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.2636921357
Short name T157
Test name
Test status
Simulation time 1700342746 ps
CPU time 31.33 seconds
Started Mar 12 12:58:23 PM PDT 24
Finished Mar 12 12:58:54 PM PDT 24
Peak memory 244780 kb
Host smart-5fffe748-b52e-4b27-8051-c4f49845c7b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2636921357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.2636921357
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.2191874957
Short name T44
Test name
Test status
Simulation time 50149283460 ps
CPU time 2991.83 seconds
Started Mar 12 01:40:13 PM PDT 24
Finished Mar 12 02:30:05 PM PDT 24
Peak memory 288688 kb
Host smart-fd9cdff9-ece4-44d0-87c4-cf4041bbfb37
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191874957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.2191874957
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.2847971652
Short name T54
Test name
Test status
Simulation time 34743972112 ps
CPU time 3076.14 seconds
Started Mar 12 01:42:48 PM PDT 24
Finished Mar 12 02:34:05 PM PDT 24
Peak memory 304620 kb
Host smart-97de8b9b-8b90-4b8b-b317-322206d8c9cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847971652 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.2847971652
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.1837662162
Short name T41
Test name
Test status
Simulation time 51581127608 ps
CPU time 3396.6 seconds
Started Mar 12 01:42:40 PM PDT 24
Finished Mar 12 02:39:18 PM PDT 24
Peak memory 288740 kb
Host smart-e1708575-3535-4994-b8be-1edcda32aac5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837662162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.1837662162
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.394057123
Short name T128
Test name
Test status
Simulation time 12538377953 ps
CPU time 909.85 seconds
Started Mar 12 12:58:09 PM PDT 24
Finished Mar 12 01:13:20 PM PDT 24
Peak memory 265388 kb
Host smart-2b4c4254-c095-4416-9600-858d6593ad03
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394057123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.394057123
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.3458661965
Short name T79
Test name
Test status
Simulation time 73256293027 ps
CPU time 1760.57 seconds
Started Mar 12 01:40:22 PM PDT 24
Finished Mar 12 02:09:43 PM PDT 24
Peak memory 289120 kb
Host smart-597e430c-f38d-49f7-b43e-092d0069a5e8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458661965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.3458661965
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.2931605120
Short name T132
Test name
Test status
Simulation time 4253615721 ps
CPU time 303.07 seconds
Started Mar 12 12:58:07 PM PDT 24
Finished Mar 12 01:03:10 PM PDT 24
Peak memory 265188 kb
Host smart-1c5b4829-8cb5-40af-a82e-7ec070e00574
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2931605120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.2931605120
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.1931315988
Short name T102
Test name
Test status
Simulation time 24073546380 ps
CPU time 394.25 seconds
Started Mar 12 01:39:18 PM PDT 24
Finished Mar 12 01:45:57 PM PDT 24
Peak memory 253272 kb
Host smart-ae79d4df-0682-4210-993b-e9079d659195
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931315988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.1931315988
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1057634598
Short name T121
Test name
Test status
Simulation time 17359759577 ps
CPU time 598.12 seconds
Started Mar 12 12:57:52 PM PDT 24
Finished Mar 12 01:07:50 PM PDT 24
Peak memory 272364 kb
Host smart-e7a7b267-5f97-4c12-99cc-539a20b77241
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057634598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.1057634598
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.2474405829
Short name T34
Test name
Test status
Simulation time 402435886 ps
CPU time 6.87 seconds
Started Mar 12 01:38:24 PM PDT 24
Finished Mar 12 01:38:31 PM PDT 24
Peak memory 240320 kb
Host smart-a37e804d-a37e-4da3-af33-fb2270a7585a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2474405829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.2474405829
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.1295496294
Short name T78
Test name
Test status
Simulation time 44098702332 ps
CPU time 3099.83 seconds
Started Mar 12 01:38:55 PM PDT 24
Finished Mar 12 02:30:35 PM PDT 24
Peak memory 289468 kb
Host smart-b75a2a63-add8-4a45-ad6e-4e2207610df0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295496294 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.1295496294
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.651744442
Short name T288
Test name
Test status
Simulation time 94185539391 ps
CPU time 750.86 seconds
Started Mar 12 01:40:13 PM PDT 24
Finished Mar 12 01:52:44 PM PDT 24
Peak memory 248516 kb
Host smart-4f455258-20f6-4311-8e1d-e19fcdc4e91e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651744442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.651744442
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2033429780
Short name T129
Test name
Test status
Simulation time 1931302537 ps
CPU time 182.38 seconds
Started Mar 12 12:58:13 PM PDT 24
Finished Mar 12 01:01:16 PM PDT 24
Peak memory 265024 kb
Host smart-ac620165-9616-4930-9208-fddb84f66e3e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2033429780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.2033429780
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.754650427
Short name T160
Test name
Test status
Simulation time 21691376 ps
CPU time 1.39 seconds
Started Mar 12 12:58:26 PM PDT 24
Finished Mar 12 12:58:28 PM PDT 24
Peak memory 235552 kb
Host smart-10205b18-e199-46d4-bcc3-03b7c11cda22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=754650427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.754650427
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.1030167997
Short name T12
Test name
Test status
Simulation time 31624577185 ps
CPU time 1005.36 seconds
Started Mar 12 01:42:48 PM PDT 24
Finished Mar 12 01:59:34 PM PDT 24
Peak memory 272508 kb
Host smart-0071a04e-779e-4a6d-9c52-f1c214e5a459
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030167997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.1030167997
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3992037264
Short name T142
Test name
Test status
Simulation time 4467981181 ps
CPU time 527.31 seconds
Started Mar 12 12:58:10 PM PDT 24
Finished Mar 12 01:06:57 PM PDT 24
Peak memory 265220 kb
Host smart-1d552899-d704-4672-afaf-23bb82b5e972
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992037264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.3992037264
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.2284871017
Short name T320
Test name
Test status
Simulation time 53699025333 ps
CPU time 1425.11 seconds
Started Mar 12 01:40:13 PM PDT 24
Finished Mar 12 02:03:58 PM PDT 24
Peak memory 272592 kb
Host smart-2815ff8a-d199-4737-99b5-50ffb3da38e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284871017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.2284871017
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.446504736
Short name T23
Test name
Test status
Simulation time 235487173269 ps
CPU time 3478.77 seconds
Started Mar 12 01:40:27 PM PDT 24
Finished Mar 12 02:38:27 PM PDT 24
Peak memory 288796 kb
Host smart-49014c19-fba6-440c-a449-2b1f9f76a4a0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446504736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_han
dler_stress_all.446504736
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.80958959
Short name T1
Test name
Test status
Simulation time 8949665255 ps
CPU time 401.33 seconds
Started Mar 12 01:41:04 PM PDT 24
Finished Mar 12 01:47:46 PM PDT 24
Peak memory 247400 kb
Host smart-a0f9e1d6-5b0a-415c-bb2f-3d451a5560c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80958959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.80958959
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3521477867
Short name T152
Test name
Test status
Simulation time 2101025575 ps
CPU time 159.76 seconds
Started Mar 12 12:58:26 PM PDT 24
Finished Mar 12 01:01:07 PM PDT 24
Peak memory 256952 kb
Host smart-0bc95323-8922-4b13-b714-5081b4316ed4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3521477867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.3521477867
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.3213323997
Short name T119
Test name
Test status
Simulation time 4603060471 ps
CPU time 651.04 seconds
Started Mar 12 12:58:18 PM PDT 24
Finished Mar 12 01:09:09 PM PDT 24
Peak memory 272992 kb
Host smart-b854d08d-4c5b-4599-9bdc-d729f17fab7c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213323997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.3213323997
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.2288851672
Short name T301
Test name
Test status
Simulation time 22071947234 ps
CPU time 465.39 seconds
Started Mar 12 01:39:45 PM PDT 24
Finished Mar 12 01:47:31 PM PDT 24
Peak memory 246420 kb
Host smart-0a89a675-4756-4f45-82d6-2c4385fbf711
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288851672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.2288851672
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.180036336
Short name T111
Test name
Test status
Simulation time 40301973156 ps
CPU time 2637.59 seconds
Started Mar 12 01:41:18 PM PDT 24
Finished Mar 12 02:25:16 PM PDT 24
Peak memory 289432 kb
Host smart-df0bebf9-9713-49cb-958d-de6928039ac8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180036336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.180036336
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.98971221
Short name T104
Test name
Test status
Simulation time 66089972470 ps
CPU time 1985.66 seconds
Started Mar 12 01:39:18 PM PDT 24
Finished Mar 12 02:12:29 PM PDT 24
Peak memory 281368 kb
Host smart-6bda30e0-467d-4821-a197-883c89251497
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98971221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_hand
ler_stress_all.98971221
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.325115438
Short name T153
Test name
Test status
Simulation time 2899197761 ps
CPU time 90.01 seconds
Started Mar 12 12:58:04 PM PDT 24
Finished Mar 12 12:59:34 PM PDT 24
Peak memory 257000 kb
Host smart-c44f65db-84b1-4c63-a1ec-b30366abafe3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=325115438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_error
s.325115438
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.1833638180
Short name T7
Test name
Test status
Simulation time 31334494962 ps
CPU time 341.38 seconds
Started Mar 12 01:40:02 PM PDT 24
Finished Mar 12 01:45:45 PM PDT 24
Peak memory 247332 kb
Host smart-e0181438-5007-4f47-b215-b443b9efcd18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833638180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.1833638180
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.3482451127
Short name T300
Test name
Test status
Simulation time 36194957523 ps
CPU time 2054.32 seconds
Started Mar 12 01:42:33 PM PDT 24
Finished Mar 12 02:16:48 PM PDT 24
Peak memory 272752 kb
Host smart-ccb0dd7c-d8ef-4790-96a2-f1840c24137d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482451127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.3482451127
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.4172545933
Short name T146
Test name
Test status
Simulation time 4550869384 ps
CPU time 335.85 seconds
Started Mar 12 12:58:18 PM PDT 24
Finished Mar 12 01:03:54 PM PDT 24
Peak memory 265140 kb
Host smart-e769c85c-e124-4aef-9147-9308308aefbe
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172545933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.4172545933
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.4238705742
Short name T43
Test name
Test status
Simulation time 145966594339 ps
CPU time 3757.33 seconds
Started Mar 12 01:41:32 PM PDT 24
Finished Mar 12 02:44:10 PM PDT 24
Peak memory 338524 kb
Host smart-965d8907-c8e7-459e-beee-2b082919775a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238705742 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.4238705742
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.1941054409
Short name T49
Test name
Test status
Simulation time 480050853628 ps
CPU time 9107.94 seconds
Started Mar 12 01:39:15 PM PDT 24
Finished Mar 12 04:11:06 PM PDT 24
Peak memory 394400 kb
Host smart-7fc9c32a-d0bd-481d-b8d1-423909bb3ff8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941054409 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.1941054409
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.3960919349
Short name T169
Test name
Test status
Simulation time 105181657 ps
CPU time 2.48 seconds
Started Mar 12 12:58:05 PM PDT 24
Finished Mar 12 12:58:08 PM PDT 24
Peak memory 236764 kb
Host smart-7d115fb4-20c2-4828-9b58-7d181b39868b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3960919349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.3960919349
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.2716574771
Short name T40
Test name
Test status
Simulation time 57908641316 ps
CPU time 1822.87 seconds
Started Mar 12 01:42:27 PM PDT 24
Finished Mar 12 02:12:50 PM PDT 24
Peak memory 288944 kb
Host smart-16929c47-ec26-4fc7-9380-fdc177299bbf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716574771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.2716574771
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3789306849
Short name T130
Test name
Test status
Simulation time 3807412209 ps
CPU time 277.63 seconds
Started Mar 12 12:58:10 PM PDT 24
Finished Mar 12 01:02:48 PM PDT 24
Peak memory 265184 kb
Host smart-74f74b4c-8e0b-42c5-8714-366b6054257c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3789306849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.3789306849
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.3477146521
Short name T317
Test name
Test status
Simulation time 14323135885 ps
CPU time 587.01 seconds
Started Mar 12 01:39:32 PM PDT 24
Finished Mar 12 01:49:20 PM PDT 24
Peak memory 247452 kb
Host smart-21d04cc1-a0c5-4635-9d52-d3694569c050
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477146521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.3477146521
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.1158599418
Short name T322
Test name
Test status
Simulation time 154125447813 ps
CPU time 2264 seconds
Started Mar 12 01:40:28 PM PDT 24
Finished Mar 12 02:18:12 PM PDT 24
Peak memory 288636 kb
Host smart-c6d3cbfb-f30f-4ad3-8299-60235d57e60e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158599418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.1158599418
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.2552480881
Short name T246
Test name
Test status
Simulation time 189061445341 ps
CPU time 3337.09 seconds
Started Mar 12 01:41:32 PM PDT 24
Finished Mar 12 02:37:09 PM PDT 24
Peak memory 299528 kb
Host smart-f43c4a74-15ab-47cd-880d-53bf89b634f2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552480881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.2552480881
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.3474311620
Short name T161
Test name
Test status
Simulation time 6547747 ps
CPU time 1.43 seconds
Started Mar 12 12:58:26 PM PDT 24
Finished Mar 12 12:58:28 PM PDT 24
Peak memory 235556 kb
Host smart-96012363-6ded-4fd9-9b30-80943409f32e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3474311620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.3474311620
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.563193930
Short name T330
Test name
Test status
Simulation time 168456427544 ps
CPU time 2463.43 seconds
Started Mar 12 01:39:55 PM PDT 24
Finished Mar 12 02:21:00 PM PDT 24
Peak memory 281240 kb
Host smart-554e088b-33c1-43db-92ea-cbf6251d52f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563193930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.563193930
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.13783788
Short name T126
Test name
Test status
Simulation time 9207203526 ps
CPU time 637.1 seconds
Started Mar 12 12:58:16 PM PDT 24
Finished Mar 12 01:08:54 PM PDT 24
Peak memory 265260 kb
Host smart-e72b9eaa-d196-4c96-b9a2-afda679e5010
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13783788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.13783788
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.3066733481
Short name T689
Test name
Test status
Simulation time 35085238144 ps
CPU time 396.39 seconds
Started Mar 12 01:38:56 PM PDT 24
Finished Mar 12 01:45:32 PM PDT 24
Peak memory 247216 kb
Host smart-e885af33-204d-4887-87b1-d1b51899f6a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066733481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.3066733481
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.2237781634
Short name T85
Test name
Test status
Simulation time 291936584477 ps
CPU time 7495.09 seconds
Started Mar 12 01:40:08 PM PDT 24
Finished Mar 12 03:45:03 PM PDT 24
Peak memory 367132 kb
Host smart-b05b34ee-1881-4cc0-af76-4c05042d82f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237781634 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.2237781634
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.721881492
Short name T240
Test name
Test status
Simulation time 212190372837 ps
CPU time 2429.98 seconds
Started Mar 12 01:40:14 PM PDT 24
Finished Mar 12 02:20:44 PM PDT 24
Peak memory 289004 kb
Host smart-b60b10f6-7eb7-4e25-9f40-5a4c6a4c4abe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721881492 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.721881492
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.815833234
Short name T250
Test name
Test status
Simulation time 3522036609 ps
CPU time 50.62 seconds
Started Mar 12 01:40:07 PM PDT 24
Finished Mar 12 01:40:58 PM PDT 24
Peak memory 255576 kb
Host smart-3f2c30ac-33f7-45fc-b8de-04a64961945d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81583
3234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.815833234
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.3904080983
Short name T289
Test name
Test status
Simulation time 8368589358 ps
CPU time 361.17 seconds
Started Mar 12 01:40:43 PM PDT 24
Finished Mar 12 01:46:44 PM PDT 24
Peak memory 247396 kb
Host smart-9392601f-04be-48de-b7f4-88c2e51e3e3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904080983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3904080983
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.3098613223
Short name T264
Test name
Test status
Simulation time 35107139061 ps
CPU time 2304.63 seconds
Started Mar 12 01:42:11 PM PDT 24
Finished Mar 12 02:20:36 PM PDT 24
Peak memory 288696 kb
Host smart-55c4037f-aa67-481b-a12f-5c69c3388e66
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098613223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.3098613223
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.698706387
Short name T145
Test name
Test status
Simulation time 18418190184 ps
CPU time 211.01 seconds
Started Mar 12 12:58:33 PM PDT 24
Finished Mar 12 01:02:04 PM PDT 24
Peak memory 265188 kb
Host smart-442dce40-db56-4393-8663-a33b9254f5fe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=698706387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_erro
rs.698706387
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1745924392
Short name T149
Test name
Test status
Simulation time 2244315894 ps
CPU time 307.72 seconds
Started Mar 12 12:58:05 PM PDT 24
Finished Mar 12 01:03:13 PM PDT 24
Peak memory 268492 kb
Host smart-789befa1-9c23-41ef-9098-b2c2c2712b62
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745924392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.1745924392
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.3069950972
Short name T202
Test name
Test status
Simulation time 22342106 ps
CPU time 2.73 seconds
Started Mar 12 01:38:56 PM PDT 24
Finished Mar 12 01:38:58 PM PDT 24
Peak memory 248688 kb
Host smart-a9ef1b4e-3bb0-4b49-85c0-4b14d4b54a56
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3069950972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.3069950972
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.3056784438
Short name T204
Test name
Test status
Simulation time 61918519 ps
CPU time 2.27 seconds
Started Mar 12 01:39:13 PM PDT 24
Finished Mar 12 01:39:16 PM PDT 24
Peak memory 248688 kb
Host smart-57c901db-42a7-47d4-aa96-3a13a34a5512
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3056784438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.3056784438
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.3216720049
Short name T207
Test name
Test status
Simulation time 41517048 ps
CPU time 3.81 seconds
Started Mar 12 01:39:17 PM PDT 24
Finished Mar 12 01:39:26 PM PDT 24
Peak memory 248676 kb
Host smart-612fc229-9cdf-4bf1-9a03-d305a7bcca78
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3216720049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.3216720049
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.4208367738
Short name T205
Test name
Test status
Simulation time 42490213 ps
CPU time 3.66 seconds
Started Mar 12 01:39:26 PM PDT 24
Finished Mar 12 01:39:31 PM PDT 24
Peak memory 248696 kb
Host smart-ac379ccf-e045-4aa4-9a55-08a01619f1c8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4208367738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.4208367738
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.4106708888
Short name T26
Test name
Test status
Simulation time 78683370872 ps
CPU time 1670.84 seconds
Started Mar 12 01:39:55 PM PDT 24
Finished Mar 12 02:07:47 PM PDT 24
Peak memory 289048 kb
Host smart-41471a58-a434-4e53-89fd-4072f092b6ac
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106708888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.4106708888
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.565936982
Short name T192
Test name
Test status
Simulation time 370787250169 ps
CPU time 4660.32 seconds
Started Mar 12 01:39:06 PM PDT 24
Finished Mar 12 02:56:48 PM PDT 24
Peak memory 322200 kb
Host smart-54de09cb-9858-44cc-98f4-4998ce1c472e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565936982 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.565936982
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3992712502
Short name T118
Test name
Test status
Simulation time 15485089005 ps
CPU time 557.66 seconds
Started Mar 12 12:58:23 PM PDT 24
Finished Mar 12 01:07:41 PM PDT 24
Peak memory 269376 kb
Host smart-1a67b243-98c8-49c4-ab06-e16a28a9f36e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992712502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.3992712502
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3720609552
Short name T163
Test name
Test status
Simulation time 3720207455 ps
CPU time 71.46 seconds
Started Mar 12 12:57:59 PM PDT 24
Finished Mar 12 12:59:11 PM PDT 24
Peak memory 237712 kb
Host smart-4861957b-b0ea-4781-af99-d9eff4972bac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3720609552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.3720609552
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.4158157548
Short name T158
Test name
Test status
Simulation time 155918306 ps
CPU time 20.49 seconds
Started Mar 12 12:58:16 PM PDT 24
Finished Mar 12 12:58:36 PM PDT 24
Peak memory 239376 kb
Host smart-03b01bea-dc72-4c83-8c6f-0639b4baf8b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4158157548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.4158157548
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.1313861920
Short name T724
Test name
Test status
Simulation time 10748143 ps
CPU time 1.28 seconds
Started Mar 12 12:58:04 PM PDT 24
Finished Mar 12 12:58:05 PM PDT 24
Peak memory 235508 kb
Host smart-f2048085-df2d-49e3-99d3-b90dfbc4c270
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1313861920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.1313861920
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3609455219
Short name T124
Test name
Test status
Simulation time 12664979311 ps
CPU time 892.98 seconds
Started Mar 12 12:58:07 PM PDT 24
Finished Mar 12 01:13:00 PM PDT 24
Peak memory 265192 kb
Host smart-4ec97495-b7af-4ef1-bebc-31a3b519d181
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609455219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.3609455219
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.2878401832
Short name T649
Test name
Test status
Simulation time 99501249871 ps
CPU time 4254.98 seconds
Started Mar 12 01:39:15 PM PDT 24
Finished Mar 12 02:50:13 PM PDT 24
Peak memory 338764 kb
Host smart-d8daa2e3-1ddd-43d1-aa53-39dd44eaa3df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878401832 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.2878401832
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.2141492302
Short name T290
Test name
Test status
Simulation time 68551119261 ps
CPU time 2218.43 seconds
Started Mar 12 01:39:12 PM PDT 24
Finished Mar 12 02:16:11 PM PDT 24
Peak memory 288952 kb
Host smart-76cf8c6e-7a36-43cf-88bb-618574b10326
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141492302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.2141492302
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1413874408
Short name T323
Test name
Test status
Simulation time 50133029877 ps
CPU time 3164.01 seconds
Started Mar 12 01:38:51 PM PDT 24
Finished Mar 12 02:31:35 PM PDT 24
Peak memory 287628 kb
Host smart-6b47ecc2-c446-455d-a0b6-5ad84ec83293
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413874408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1413874408
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.4118838007
Short name T698
Test name
Test status
Simulation time 7621534952 ps
CPU time 158.42 seconds
Started Mar 12 01:39:15 PM PDT 24
Finished Mar 12 01:41:55 PM PDT 24
Peak memory 246232 kb
Host smart-b4ba99ee-ed37-421a-9bb8-8dff4e67b706
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118838007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.4118838007
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.77131964
Short name T197
Test name
Test status
Simulation time 192786099269 ps
CPU time 2785.21 seconds
Started Mar 12 01:38:39 PM PDT 24
Finished Mar 12 02:25:05 PM PDT 24
Peak memory 304816 kb
Host smart-376d82db-190a-47f9-a0d2-adc622181cca
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77131964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_hand
ler_stress_all.77131964
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.790894396
Short name T267
Test name
Test status
Simulation time 14664488121 ps
CPU time 866.76 seconds
Started Mar 12 01:39:28 PM PDT 24
Finished Mar 12 01:53:56 PM PDT 24
Peak memory 264964 kb
Host smart-4fdc0c5b-5457-4d26-871b-119751f87a96
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790894396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_han
dler_stress_all.790894396
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.3397043641
Short name T276
Test name
Test status
Simulation time 34681350775 ps
CPU time 999.46 seconds
Started Mar 12 01:39:56 PM PDT 24
Finished Mar 12 01:56:37 PM PDT 24
Peak memory 273168 kb
Host smart-4abef0f9-4d0d-4678-bc2b-d4c3a24018d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397043641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.3397043641
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.3281316138
Short name T247
Test name
Test status
Simulation time 2478308650 ps
CPU time 58.76 seconds
Started Mar 12 01:40:04 PM PDT 24
Finished Mar 12 01:41:03 PM PDT 24
Peak memory 254964 kb
Host smart-27d8a3fe-517c-46c1-8320-e68fcbfa17ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32813
16138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.3281316138
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.4274062555
Short name T248
Test name
Test status
Simulation time 47276588671 ps
CPU time 2456.28 seconds
Started Mar 12 01:40:03 PM PDT 24
Finished Mar 12 02:21:00 PM PDT 24
Peak memory 286956 kb
Host smart-777175c1-b9cd-41e9-aacf-b1db5dfeb02f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274062555 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.4274062555
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.4172977024
Short name T270
Test name
Test status
Simulation time 54057265221 ps
CPU time 1126.37 seconds
Started Mar 12 01:40:13 PM PDT 24
Finished Mar 12 01:59:00 PM PDT 24
Peak memory 289624 kb
Host smart-1d61ea25-e21e-49d1-b93e-05d55b33ad4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172977024 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.4172977024
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.1383472768
Short name T74
Test name
Test status
Simulation time 20725338259 ps
CPU time 745.79 seconds
Started Mar 12 01:40:11 PM PDT 24
Finished Mar 12 01:52:37 PM PDT 24
Peak memory 273340 kb
Host smart-b6f196b8-0e27-4e64-959e-05c3a5f04ceb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383472768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.1383472768
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.1069499896
Short name T249
Test name
Test status
Simulation time 629020474 ps
CPU time 26.22 seconds
Started Mar 12 01:40:21 PM PDT 24
Finished Mar 12 01:40:47 PM PDT 24
Peak memory 246716 kb
Host smart-7f278635-ddbe-4a84-ae39-451c90178bda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10694
99896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.1069499896
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.2824405409
Short name T262
Test name
Test status
Simulation time 60003970047 ps
CPU time 5093.14 seconds
Started Mar 12 01:40:50 PM PDT 24
Finished Mar 12 03:05:44 PM PDT 24
Peak memory 306064 kb
Host smart-eae8359a-5614-4aaa-be93-75748b63f191
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824405409 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.2824405409
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.505038632
Short name T127
Test name
Test status
Simulation time 3074555099 ps
CPU time 95.86 seconds
Started Mar 12 12:58:09 PM PDT 24
Finished Mar 12 12:59:45 PM PDT 24
Peak memory 256896 kb
Host smart-2314f076-1593-46f5-9120-c2820537824d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=505038632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_erro
rs.505038632
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.767846567
Short name T135
Test name
Test status
Simulation time 8659922530 ps
CPU time 153.34 seconds
Started Mar 12 12:58:18 PM PDT 24
Finished Mar 12 01:00:52 PM PDT 24
Peak memory 265008 kb
Host smart-693c8e6a-5877-4e4b-967a-ac2ad0d2ceac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=767846567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_erro
rs.767846567
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3241334795
Short name T170
Test name
Test status
Simulation time 39191792 ps
CPU time 3.41 seconds
Started Mar 12 12:58:09 PM PDT 24
Finished Mar 12 12:58:13 PM PDT 24
Peak memory 236344 kb
Host smart-21f56593-df66-40b1-aecf-a6ea3d016de8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3241334795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.3241334795
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1367587731
Short name T172
Test name
Test status
Simulation time 491956986 ps
CPU time 35.6 seconds
Started Mar 12 12:58:18 PM PDT 24
Finished Mar 12 12:58:53 PM PDT 24
Peak memory 240252 kb
Host smart-797b610e-6388-45d5-9fc7-2d870eddef84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1367587731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.1367587731
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.941666198
Short name T174
Test name
Test status
Simulation time 1315318727 ps
CPU time 41.92 seconds
Started Mar 12 12:58:06 PM PDT 24
Finished Mar 12 12:58:48 PM PDT 24
Peak memory 240296 kb
Host smart-9e7b6280-f49f-4ef9-ab71-1dd83255faa8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=941666198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.941666198
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.3193125207
Short name T165
Test name
Test status
Simulation time 35767829 ps
CPU time 2.83 seconds
Started Mar 12 12:58:08 PM PDT 24
Finished Mar 12 12:58:11 PM PDT 24
Peak memory 236364 kb
Host smart-e14f491f-b47f-4b43-a5e1-51ac757f38b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3193125207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.3193125207
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3332109692
Short name T141
Test name
Test status
Simulation time 4567856896 ps
CPU time 666.96 seconds
Started Mar 12 12:58:09 PM PDT 24
Finished Mar 12 01:09:16 PM PDT 24
Peak memory 265168 kb
Host smart-74725a91-2d64-49e7-bdc5-615cbcbdf3ac
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332109692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.3332109692
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2482991375
Short name T175
Test name
Test status
Simulation time 53155965 ps
CPU time 3.79 seconds
Started Mar 12 12:58:18 PM PDT 24
Finished Mar 12 12:58:22 PM PDT 24
Peak memory 236720 kb
Host smart-663af63d-3cd5-4266-b16d-32d83f0f8a8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2482991375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.2482991375
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.93944018
Short name T164
Test name
Test status
Simulation time 185387264 ps
CPU time 3.84 seconds
Started Mar 12 12:58:18 PM PDT 24
Finished Mar 12 12:58:23 PM PDT 24
Peak memory 236252 kb
Host smart-577739a9-d05d-46b1-aeb2-054594ddadd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=93944018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.93944018
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.1385586293
Short name T166
Test name
Test status
Simulation time 1847743434 ps
CPU time 66.03 seconds
Started Mar 12 12:58:15 PM PDT 24
Finished Mar 12 12:59:22 PM PDT 24
Peak memory 240304 kb
Host smart-06bffc19-fc5a-4b59-9505-b663ca340aee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1385586293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.1385586293
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.988787527
Short name T123
Test name
Test status
Simulation time 6404113471 ps
CPU time 162.99 seconds
Started Mar 12 12:58:25 PM PDT 24
Finished Mar 12 01:01:08 PM PDT 24
Peak memory 265180 kb
Host smart-f8ba6ec6-c2bf-4ab2-8b73-d0a9f31be4e2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=988787527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_erro
rs.988787527
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.796460611
Short name T173
Test name
Test status
Simulation time 926776298 ps
CPU time 68.33 seconds
Started Mar 12 12:58:23 PM PDT 24
Finished Mar 12 12:59:36 PM PDT 24
Peak memory 236476 kb
Host smart-f7dd0548-febc-4442-ae34-f0f3798c1452
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=796460611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.796460611
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3251640320
Short name T159
Test name
Test status
Simulation time 55178242 ps
CPU time 3.57 seconds
Started Mar 12 12:58:08 PM PDT 24
Finished Mar 12 12:58:11 PM PDT 24
Peak memory 237396 kb
Host smart-b0089c40-25f9-4188-818a-13f17db78c37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3251640320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.3251640320
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.1903049328
Short name T167
Test name
Test status
Simulation time 714835300 ps
CPU time 36.97 seconds
Started Mar 12 12:58:10 PM PDT 24
Finished Mar 12 12:58:47 PM PDT 24
Peak memory 236712 kb
Host smart-c7f0f410-5691-4dc8-b3b0-318aac47e299
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1903049328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.1903049328
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.562428619
Short name T171
Test name
Test status
Simulation time 1769049224 ps
CPU time 67.2 seconds
Started Mar 12 12:58:07 PM PDT 24
Finished Mar 12 12:59:15 PM PDT 24
Peak memory 240328 kb
Host smart-d71a611b-8e3c-4fcc-b366-6aad2aea47ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=562428619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.562428619
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.450245848
Short name T178
Test name
Test status
Simulation time 30093473 ps
CPU time 2.71 seconds
Started Mar 12 12:58:27 PM PDT 24
Finished Mar 12 12:58:30 PM PDT 24
Peak memory 236400 kb
Host smart-1428739e-25b2-421e-8ba2-f1726ad5f1c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=450245848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.450245848
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2988004628
Short name T180
Test name
Test status
Simulation time 913537995 ps
CPU time 34.81 seconds
Started Mar 12 12:58:09 PM PDT 24
Finished Mar 12 12:58:44 PM PDT 24
Peak memory 245112 kb
Host smart-bec58d5f-be2f-492e-940d-ccf29378b14b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2988004628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.2988004628
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3118115118
Short name T168
Test name
Test status
Simulation time 2614463223 ps
CPU time 42.9 seconds
Started Mar 12 12:58:09 PM PDT 24
Finished Mar 12 12:58:53 PM PDT 24
Peak memory 236700 kb
Host smart-5a85db18-a83a-42dc-b150-d254e18a46da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3118115118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.3118115118
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.1972757241
Short name T3
Test name
Test status
Simulation time 7894954438 ps
CPU time 1012.16 seconds
Started Mar 12 01:39:00 PM PDT 24
Finished Mar 12 01:55:52 PM PDT 24
Peak memory 269076 kb
Host smart-a440eda0-c078-40d6-bb5c-cefc03880dd9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972757241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.1972757241
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.1008497348
Short name T20
Test name
Test status
Simulation time 64978874456 ps
CPU time 2221.89 seconds
Started Mar 12 01:40:33 PM PDT 24
Finished Mar 12 02:17:35 PM PDT 24
Peak memory 285916 kb
Host smart-f99c21ac-a836-499c-992a-0b9f2a5d8d3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008497348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.1008497348
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.3234936013
Short name T25
Test name
Test status
Simulation time 117345639159 ps
CPU time 1521.63 seconds
Started Mar 12 01:39:15 PM PDT 24
Finished Mar 12 02:04:41 PM PDT 24
Peak memory 272084 kb
Host smart-9ced16c4-de8a-4c6f-8977-15db97d3318e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234936013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.3234936013
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.225211429
Short name T191
Test name
Test status
Simulation time 8082679306 ps
CPU time 129.69 seconds
Started Mar 12 12:58:04 PM PDT 24
Finished Mar 12 01:00:14 PM PDT 24
Peak memory 240280 kb
Host smart-27ce9d34-acd9-4769-80e1-46da5248e995
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=225211429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.225211429
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.113628842
Short name T765
Test name
Test status
Simulation time 13741103221 ps
CPU time 203.29 seconds
Started Mar 12 12:58:08 PM PDT 24
Finished Mar 12 01:01:31 PM PDT 24
Peak memory 235428 kb
Host smart-9537e78a-1c44-4189-bb65-83039673cf7a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=113628842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.113628842
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2984770912
Short name T800
Test name
Test status
Simulation time 180955743 ps
CPU time 4.76 seconds
Started Mar 12 12:58:08 PM PDT 24
Finished Mar 12 12:58:13 PM PDT 24
Peak memory 240208 kb
Host smart-4b5b36f7-e312-4bf6-9e66-23e609ecd916
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2984770912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2984770912
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1038054999
Short name T789
Test name
Test status
Simulation time 137807243 ps
CPU time 4.97 seconds
Started Mar 12 12:58:06 PM PDT 24
Finished Mar 12 12:58:11 PM PDT 24
Peak memory 240188 kb
Host smart-656fb696-6b01-4964-950c-d8da353b0bb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038054999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.1038054999
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.3787858199
Short name T771
Test name
Test status
Simulation time 467999700 ps
CPU time 8.05 seconds
Started Mar 12 12:58:09 PM PDT 24
Finished Mar 12 12:58:17 PM PDT 24
Peak memory 236312 kb
Host smart-c36dc088-e43a-42e9-8330-6b9b2c60541b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3787858199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.3787858199
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.770721351
Short name T756
Test name
Test status
Simulation time 677737356 ps
CPU time 22.84 seconds
Started Mar 12 12:58:13 PM PDT 24
Finished Mar 12 12:58:36 PM PDT 24
Peak memory 240228 kb
Host smart-5f3a67b9-85d6-4319-93c3-6ec11e8487b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=770721351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outs
tanding.770721351
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.2217145853
Short name T826
Test name
Test status
Simulation time 266338134 ps
CPU time 5.39 seconds
Started Mar 12 12:58:15 PM PDT 24
Finished Mar 12 12:58:21 PM PDT 24
Peak memory 248148 kb
Host smart-deead1c0-495a-496d-8f8a-9a90966f8852
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2217145853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.2217145853
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.1766784724
Short name T827
Test name
Test status
Simulation time 4754241809 ps
CPU time 140.63 seconds
Started Mar 12 12:58:06 PM PDT 24
Finished Mar 12 01:00:27 PM PDT 24
Peak memory 240216 kb
Host smart-aae2db27-e5f7-4552-8ef0-7d605d7419a9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1766784724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.1766784724
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2661434802
Short name T783
Test name
Test status
Simulation time 11453886246 ps
CPU time 356.4 seconds
Started Mar 12 12:58:05 PM PDT 24
Finished Mar 12 01:04:02 PM PDT 24
Peak memory 240312 kb
Host smart-f6c6d7d0-974b-4034-b7a1-c2582f0fb948
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2661434802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.2661434802
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.452983078
Short name T712
Test name
Test status
Simulation time 99934801 ps
CPU time 5.64 seconds
Started Mar 12 12:58:09 PM PDT 24
Finished Mar 12 12:58:15 PM PDT 24
Peak memory 240252 kb
Host smart-b94bcc49-abeb-4200-8491-3611fa08f08c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=452983078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.452983078
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.2011248440
Short name T753
Test name
Test status
Simulation time 1238370716 ps
CPU time 8.54 seconds
Started Mar 12 12:58:04 PM PDT 24
Finished Mar 12 12:58:12 PM PDT 24
Peak memory 239648 kb
Host smart-945edf8e-4928-4a76-8784-71ff4da07325
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011248440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.2011248440
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.410439546
Short name T746
Test name
Test status
Simulation time 67007026 ps
CPU time 5.03 seconds
Started Mar 12 12:58:04 PM PDT 24
Finished Mar 12 12:58:09 PM PDT 24
Peak memory 235260 kb
Host smart-b6e45c29-be1a-4d6a-98e2-36eee88c6a97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=410439546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.410439546
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3813807725
Short name T736
Test name
Test status
Simulation time 8609064 ps
CPU time 1.52 seconds
Started Mar 12 12:58:15 PM PDT 24
Finished Mar 12 12:58:17 PM PDT 24
Peak memory 236420 kb
Host smart-b4e3318a-3a38-4a63-ae98-2116c05248e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3813807725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.3813807725
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.505664653
Short name T734
Test name
Test status
Simulation time 361762360 ps
CPU time 20 seconds
Started Mar 12 12:58:08 PM PDT 24
Finished Mar 12 12:58:28 PM PDT 24
Peak memory 243592 kb
Host smart-f3372773-b1be-460f-94d3-6e29657a1bd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=505664653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_outs
tanding.505664653
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.697585595
Short name T144
Test name
Test status
Simulation time 2114105401 ps
CPU time 291.7 seconds
Started Mar 12 12:58:14 PM PDT 24
Finished Mar 12 01:03:06 PM PDT 24
Peak memory 265368 kb
Host smart-602269f6-3301-4dac-992b-ecb1a314384e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697585595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.697585595
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.356463511
Short name T706
Test name
Test status
Simulation time 117333633 ps
CPU time 6.86 seconds
Started Mar 12 12:58:08 PM PDT 24
Finished Mar 12 12:58:15 PM PDT 24
Peak memory 248168 kb
Host smart-c6417b23-b2f0-47eb-8506-1855d81fe29d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=356463511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.356463511
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.3838485506
Short name T766
Test name
Test status
Simulation time 59993569 ps
CPU time 9.18 seconds
Started Mar 12 12:58:10 PM PDT 24
Finished Mar 12 12:58:20 PM PDT 24
Peak memory 254964 kb
Host smart-c3aff637-55dd-4f3c-81ca-8a572ac849d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838485506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.3838485506
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.117286499
Short name T828
Test name
Test status
Simulation time 465736667 ps
CPU time 5.56 seconds
Started Mar 12 12:58:16 PM PDT 24
Finished Mar 12 12:58:22 PM PDT 24
Peak memory 236184 kb
Host smart-ebad00b6-0566-473b-ad6b-745070fcdd82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=117286499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.117286499
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.1046759085
Short name T795
Test name
Test status
Simulation time 20780318 ps
CPU time 1.43 seconds
Started Mar 12 12:58:10 PM PDT 24
Finished Mar 12 12:58:12 PM PDT 24
Peak memory 236420 kb
Host smart-aae3e4e3-1a4b-4499-8fd1-7e0156823b5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1046759085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.1046759085
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.1558081471
Short name T808
Test name
Test status
Simulation time 1407757752 ps
CPU time 20.14 seconds
Started Mar 12 12:58:13 PM PDT 24
Finished Mar 12 12:58:34 PM PDT 24
Peak memory 240296 kb
Host smart-8b2309ef-3d99-42a4-b969-b5d618c35002
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1558081471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.1558081471
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.1677173014
Short name T787
Test name
Test status
Simulation time 92540613 ps
CPU time 11.44 seconds
Started Mar 12 12:58:10 PM PDT 24
Finished Mar 12 12:58:21 PM PDT 24
Peak memory 248520 kb
Host smart-84d420f2-8a52-4a39-9ec3-0987db15fdf6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1677173014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.1677173014
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1376158123
Short name T343
Test name
Test status
Simulation time 33221298 ps
CPU time 5.92 seconds
Started Mar 12 12:58:13 PM PDT 24
Finished Mar 12 12:58:19 PM PDT 24
Peak memory 241712 kb
Host smart-0e4864ac-13ca-47cd-8434-917e17517650
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376158123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.1376158123
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.2459110994
Short name T815
Test name
Test status
Simulation time 491371489 ps
CPU time 8.23 seconds
Started Mar 12 12:58:04 PM PDT 24
Finished Mar 12 12:58:13 PM PDT 24
Peak memory 236212 kb
Host smart-9574dd5e-783a-4e5f-9b9f-33b230f33f8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2459110994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.2459110994
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.1357118787
Short name T748
Test name
Test status
Simulation time 8500539 ps
CPU time 1.49 seconds
Started Mar 12 12:58:07 PM PDT 24
Finished Mar 12 12:58:09 PM PDT 24
Peak memory 236400 kb
Host smart-09b3e340-f041-4b30-9f36-81512b67ad2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1357118787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.1357118787
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.847553087
Short name T709
Test name
Test status
Simulation time 748331995 ps
CPU time 41.41 seconds
Started Mar 12 12:58:13 PM PDT 24
Finished Mar 12 12:58:54 PM PDT 24
Peak memory 239996 kb
Host smart-d6000512-42ab-4862-ae49-557bf5b2da7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=847553087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_out
standing.847553087
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.4174061970
Short name T120
Test name
Test status
Simulation time 8002074304 ps
CPU time 155.33 seconds
Started Mar 12 12:58:15 PM PDT 24
Finished Mar 12 01:00:51 PM PDT 24
Peak memory 265208 kb
Host smart-d9892737-2d67-43ce-ae1b-0cb66795ecc5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4174061970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.4174061970
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3714361
Short name T150
Test name
Test status
Simulation time 25266691460 ps
CPU time 462.66 seconds
Started Mar 12 12:58:09 PM PDT 24
Finished Mar 12 01:05:52 PM PDT 24
Peak memory 265080 kb
Host smart-e7985bcf-6291-4d6f-b363-a26d03606126
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_shadow_reg_errors_with_csr_rw.3714361
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.3721319526
Short name T812
Test name
Test status
Simulation time 287333961 ps
CPU time 17.62 seconds
Started Mar 12 12:58:11 PM PDT 24
Finished Mar 12 12:58:29 PM PDT 24
Peak memory 248492 kb
Host smart-d22287eb-d121-4357-aece-d0f5202607c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3721319526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.3721319526
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3932087908
Short name T733
Test name
Test status
Simulation time 455958720 ps
CPU time 7.78 seconds
Started Mar 12 12:58:22 PM PDT 24
Finished Mar 12 12:58:30 PM PDT 24
Peak memory 240380 kb
Host smart-d61a6350-3be5-4a42-bdb6-8329aa85265a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932087908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.3932087908
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2329148025
Short name T824
Test name
Test status
Simulation time 52847663 ps
CPU time 5.03 seconds
Started Mar 12 12:58:17 PM PDT 24
Finished Mar 12 12:58:22 PM PDT 24
Peak memory 236300 kb
Host smart-38d7a66e-7c72-404a-ab8f-f99a02a620b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2329148025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.2329148025
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.916889353
Short name T738
Test name
Test status
Simulation time 6040019 ps
CPU time 1.38 seconds
Started Mar 12 12:58:27 PM PDT 24
Finished Mar 12 12:58:29 PM PDT 24
Peak memory 236268 kb
Host smart-c59bb8d9-3c30-4584-9c2f-eebe3d3ba254
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=916889353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.916889353
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.884910362
Short name T776
Test name
Test status
Simulation time 608438003 ps
CPU time 38.09 seconds
Started Mar 12 12:58:17 PM PDT 24
Finished Mar 12 12:58:55 PM PDT 24
Peak memory 243712 kb
Host smart-187007e4-7834-4aee-b6aa-332107d8cf0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=884910362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_out
standing.884910362
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.769226236
Short name T769
Test name
Test status
Simulation time 144980312 ps
CPU time 9.65 seconds
Started Mar 12 12:58:22 PM PDT 24
Finished Mar 12 12:58:32 PM PDT 24
Peak memory 248468 kb
Host smart-5e195083-1495-4768-b944-af0ae1d62b9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=769226236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.769226236
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.1406309352
Short name T713
Test name
Test status
Simulation time 200256572 ps
CPU time 4.57 seconds
Started Mar 12 12:58:17 PM PDT 24
Finished Mar 12 12:58:22 PM PDT 24
Peak memory 239048 kb
Host smart-bcc01793-7481-4b0b-b997-fc17f54e1774
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406309352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.1406309352
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3014553117
Short name T179
Test name
Test status
Simulation time 258267523 ps
CPU time 4.89 seconds
Started Mar 12 12:58:22 PM PDT 24
Finished Mar 12 12:58:28 PM PDT 24
Peak memory 240232 kb
Host smart-04c3a6a2-0a79-411b-b0bd-67d3dcaae5e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3014553117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.3014553117
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.949637309
Short name T823
Test name
Test status
Simulation time 15187562 ps
CPU time 1.26 seconds
Started Mar 12 12:58:18 PM PDT 24
Finished Mar 12 12:58:19 PM PDT 24
Peak memory 236420 kb
Host smart-3af26480-ce58-4fa5-bd29-233005a2ae3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=949637309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.949637309
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.990401657
Short name T708
Test name
Test status
Simulation time 536793113 ps
CPU time 18.76 seconds
Started Mar 12 12:58:27 PM PDT 24
Finished Mar 12 12:58:46 PM PDT 24
Peak memory 240104 kb
Host smart-d9ef1977-05cf-4a33-9e60-5ed7d4f34a18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=990401657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_out
standing.990401657
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1311427615
Short name T155
Test name
Test status
Simulation time 34350695306 ps
CPU time 323.74 seconds
Started Mar 12 12:58:19 PM PDT 24
Finished Mar 12 01:03:44 PM PDT 24
Peak memory 265208 kb
Host smart-42b2efc5-e935-4e46-b9d7-f183c41efc44
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1311427615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.1311427615
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1171363466
Short name T707
Test name
Test status
Simulation time 209807976 ps
CPU time 5.45 seconds
Started Mar 12 12:58:21 PM PDT 24
Finished Mar 12 12:58:27 PM PDT 24
Peak memory 248596 kb
Host smart-fad7d283-4e01-4f7a-a07d-f2c52dbecd17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1171363466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.1171363466
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.303076469
Short name T758
Test name
Test status
Simulation time 660724340 ps
CPU time 42.38 seconds
Started Mar 12 12:58:20 PM PDT 24
Finished Mar 12 12:59:03 PM PDT 24
Peak memory 248520 kb
Host smart-f8f16b6d-e7f1-4a40-9f7b-47a2ac8defab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=303076469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.303076469
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.650553553
Short name T340
Test name
Test status
Simulation time 54723356 ps
CPU time 4.57 seconds
Started Mar 12 12:58:27 PM PDT 24
Finished Mar 12 12:58:32 PM PDT 24
Peak memory 238880 kb
Host smart-6f82a63f-f117-4cb6-bdc4-2d2d1eb57b21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650553553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.alert_handler_csr_mem_rw_with_rand_reset.650553553
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.2970625757
Short name T747
Test name
Test status
Simulation time 316454636 ps
CPU time 7.59 seconds
Started Mar 12 12:58:21 PM PDT 24
Finished Mar 12 12:58:29 PM PDT 24
Peak memory 236308 kb
Host smart-9fdaa34e-3c1d-4783-b189-3f1ad9d764ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2970625757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.2970625757
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.2577246208
Short name T339
Test name
Test status
Simulation time 13684064 ps
CPU time 1.73 seconds
Started Mar 12 12:58:26 PM PDT 24
Finished Mar 12 12:58:28 PM PDT 24
Peak memory 236440 kb
Host smart-e5d5cc91-f997-4b30-a3b4-cd5edb85a005
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2577246208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.2577246208
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.321746345
Short name T722
Test name
Test status
Simulation time 357298812 ps
CPU time 13.18 seconds
Started Mar 12 12:58:26 PM PDT 24
Finished Mar 12 12:58:40 PM PDT 24
Peak memory 244612 kb
Host smart-376e7c59-b8e3-43bf-8ee7-c03bd7ff88b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=321746345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_out
standing.321746345
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.546738770
Short name T741
Test name
Test status
Simulation time 903652879 ps
CPU time 16.15 seconds
Started Mar 12 12:58:20 PM PDT 24
Finished Mar 12 12:58:36 PM PDT 24
Peak memory 248528 kb
Host smart-dd695701-af81-4d7f-9f57-30e139bbc073
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=546738770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.546738770
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.4290301436
Short name T716
Test name
Test status
Simulation time 59857737 ps
CPU time 5.31 seconds
Started Mar 12 12:58:17 PM PDT 24
Finished Mar 12 12:58:22 PM PDT 24
Peak memory 239568 kb
Host smart-72fd3ebc-aaef-4b5d-855d-2db312444ec1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290301436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.4290301436
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2554710161
Short name T189
Test name
Test status
Simulation time 93074767 ps
CPU time 4.74 seconds
Started Mar 12 12:58:28 PM PDT 24
Finished Mar 12 12:58:33 PM PDT 24
Peak memory 235424 kb
Host smart-481c0d77-fc38-4fba-8786-cc0039c87232
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2554710161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.2554710161
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1605304841
Short name T749
Test name
Test status
Simulation time 8205438 ps
CPU time 1.48 seconds
Started Mar 12 12:58:23 PM PDT 24
Finished Mar 12 12:58:24 PM PDT 24
Peak memory 236304 kb
Host smart-0a2383ba-8182-455a-835f-c4c0c1eb0589
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1605304841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.1605304841
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.637717395
Short name T757
Test name
Test status
Simulation time 86247926 ps
CPU time 11.33 seconds
Started Mar 12 12:58:24 PM PDT 24
Finished Mar 12 12:58:36 PM PDT 24
Peak memory 240276 kb
Host smart-4c52a872-a4b5-44c1-9bd6-df517b9a2718
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=637717395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_out
standing.637717395
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.222774628
Short name T151
Test name
Test status
Simulation time 6205762076 ps
CPU time 478.28 seconds
Started Mar 12 12:58:26 PM PDT 24
Finished Mar 12 01:06:24 PM PDT 24
Peak memory 265288 kb
Host smart-371b5ec0-4f30-48c4-a6b0-b0a29fc0e717
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222774628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.222774628
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.4263019594
Short name T710
Test name
Test status
Simulation time 158316184 ps
CPU time 6.77 seconds
Started Mar 12 12:58:19 PM PDT 24
Finished Mar 12 12:58:26 PM PDT 24
Peak memory 249856 kb
Host smart-c1e22452-a24c-47e5-ba35-526e991d5920
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4263019594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.4263019594
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.582837717
Short name T797
Test name
Test status
Simulation time 1024292059 ps
CPU time 9.36 seconds
Started Mar 12 12:58:18 PM PDT 24
Finished Mar 12 12:58:28 PM PDT 24
Peak memory 240380 kb
Host smart-e66ed81b-2b20-4ae0-a1f0-cc3ce87f3589
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582837717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.alert_handler_csr_mem_rw_with_rand_reset.582837717
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.660804572
Short name T345
Test name
Test status
Simulation time 94510617 ps
CPU time 7.13 seconds
Started Mar 12 12:58:24 PM PDT 24
Finished Mar 12 12:58:32 PM PDT 24
Peak memory 240192 kb
Host smart-df18c655-11fd-41de-93b1-f47ad5ca7853
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=660804572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.660804572
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.4014626834
Short name T333
Test name
Test status
Simulation time 7553239 ps
CPU time 1.41 seconds
Started Mar 12 12:58:23 PM PDT 24
Finished Mar 12 12:58:25 PM PDT 24
Peak memory 236420 kb
Host smart-2ab65bf4-e0ef-4386-99d6-c3b07052593a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4014626834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.4014626834
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.476702036
Short name T176
Test name
Test status
Simulation time 430340881 ps
CPU time 11.75 seconds
Started Mar 12 12:58:25 PM PDT 24
Finished Mar 12 12:58:37 PM PDT 24
Peak memory 244564 kb
Host smart-7123fe15-27cc-407d-819e-4e46585371f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=476702036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_out
standing.476702036
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1152287085
Short name T139
Test name
Test status
Simulation time 27717585393 ps
CPU time 185.63 seconds
Started Mar 12 12:58:18 PM PDT 24
Finished Mar 12 01:01:24 PM PDT 24
Peak memory 265360 kb
Host smart-40c8e6da-eaa9-4354-91dc-b3eafe19cb30
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1152287085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.1152287085
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2232529471
Short name T131
Test name
Test status
Simulation time 8435645905 ps
CPU time 559.7 seconds
Started Mar 12 12:58:20 PM PDT 24
Finished Mar 12 01:07:40 PM PDT 24
Peak memory 272932 kb
Host smart-0a27678c-287e-4caf-8fe0-67407a83452d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232529471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.2232529471
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.537068312
Short name T785
Test name
Test status
Simulation time 350197286 ps
CPU time 23.1 seconds
Started Mar 12 12:58:17 PM PDT 24
Finished Mar 12 12:58:41 PM PDT 24
Peak memory 248268 kb
Host smart-4628cbf0-a034-4dc1-8b3f-b29eac149ed1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=537068312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.537068312
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.2966325301
Short name T723
Test name
Test status
Simulation time 960270778 ps
CPU time 13.76 seconds
Started Mar 12 12:58:26 PM PDT 24
Finished Mar 12 12:58:40 PM PDT 24
Peak memory 248388 kb
Host smart-c50dc156-bc5c-4bf2-8f2a-22e20f05642a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966325301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.2966325301
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.2060766706
Short name T715
Test name
Test status
Simulation time 63660772 ps
CPU time 3.13 seconds
Started Mar 12 12:58:22 PM PDT 24
Finished Mar 12 12:58:25 PM PDT 24
Peak memory 236288 kb
Host smart-398a51e8-e898-41f2-aa02-9e57d4ec6603
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2060766706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.2060766706
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.3202790245
Short name T782
Test name
Test status
Simulation time 43823634 ps
CPU time 1.36 seconds
Started Mar 12 12:58:24 PM PDT 24
Finished Mar 12 12:58:26 PM PDT 24
Peak memory 235468 kb
Host smart-e1f5484b-5119-4b1f-ab37-036341624fc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3202790245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.3202790245
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3585906616
Short name T819
Test name
Test status
Simulation time 501908418 ps
CPU time 17.97 seconds
Started Mar 12 12:58:25 PM PDT 24
Finished Mar 12 12:58:44 PM PDT 24
Peak memory 243692 kb
Host smart-bdd1987e-d364-44d0-84be-4e7832d626a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3585906616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.3585906616
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.145304097
Short name T810
Test name
Test status
Simulation time 1912997840 ps
CPU time 7.05 seconds
Started Mar 12 12:58:20 PM PDT 24
Finished Mar 12 12:58:27 PM PDT 24
Peak memory 251592 kb
Host smart-b61d56bd-23e1-4563-aded-724a4749c1d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=145304097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.145304097
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.1916715879
Short name T718
Test name
Test status
Simulation time 78167053 ps
CPU time 5.08 seconds
Started Mar 12 12:58:28 PM PDT 24
Finished Mar 12 12:58:33 PM PDT 24
Peak memory 240112 kb
Host smart-10092d68-35de-4006-bdd7-490c6cdded74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916715879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.1916715879
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2184341424
Short name T806
Test name
Test status
Simulation time 264986559 ps
CPU time 5.14 seconds
Started Mar 12 12:58:17 PM PDT 24
Finished Mar 12 12:58:22 PM PDT 24
Peak memory 236336 kb
Host smart-7f305408-324a-4a9f-92d7-a8fb8f8bdc84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2184341424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.2184341424
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.3593036141
Short name T762
Test name
Test status
Simulation time 6255372 ps
CPU time 1.39 seconds
Started Mar 12 12:58:20 PM PDT 24
Finished Mar 12 12:58:21 PM PDT 24
Peak memory 234524 kb
Host smart-75bc94d4-be7d-4de7-b809-b3bd71340170
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3593036141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.3593036141
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1648003404
Short name T778
Test name
Test status
Simulation time 174199819 ps
CPU time 10.07 seconds
Started Mar 12 12:58:26 PM PDT 24
Finished Mar 12 12:58:36 PM PDT 24
Peak memory 240292 kb
Host smart-52180ebb-10a6-45ac-8329-9e36ce24bda0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1648003404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.1648003404
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3033095645
Short name T140
Test name
Test status
Simulation time 4335967895 ps
CPU time 182.25 seconds
Started Mar 12 12:58:23 PM PDT 24
Finished Mar 12 01:01:25 PM PDT 24
Peak memory 265060 kb
Host smart-d4b7edca-2403-4d4f-bfab-6a287b12f213
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3033095645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.3033095645
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1487997114
Short name T728
Test name
Test status
Simulation time 329591796 ps
CPU time 19.81 seconds
Started Mar 12 12:58:25 PM PDT 24
Finished Mar 12 12:58:45 PM PDT 24
Peak memory 248484 kb
Host smart-800b6cb3-483a-449f-ad76-25f095939f05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1487997114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.1487997114
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.4018179211
Short name T802
Test name
Test status
Simulation time 34743134 ps
CPU time 4.88 seconds
Started Mar 12 12:58:27 PM PDT 24
Finished Mar 12 12:58:32 PM PDT 24
Peak memory 240376 kb
Host smart-d2eb4015-3528-4f33-a479-221de18556c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018179211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.4018179211
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2414602881
Short name T811
Test name
Test status
Simulation time 257454878 ps
CPU time 5.41 seconds
Started Mar 12 12:58:28 PM PDT 24
Finished Mar 12 12:58:33 PM PDT 24
Peak memory 240164 kb
Host smart-98d5754a-07b2-4040-ae04-a529123959a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2414602881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.2414602881
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.729631463
Short name T729
Test name
Test status
Simulation time 16546837 ps
CPU time 1.89 seconds
Started Mar 12 12:58:26 PM PDT 24
Finished Mar 12 12:58:28 PM PDT 24
Peak memory 235580 kb
Host smart-266b896f-38cb-49bc-81b4-ab1fa43ae03a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=729631463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.729631463
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1265652999
Short name T779
Test name
Test status
Simulation time 411487561 ps
CPU time 18.82 seconds
Started Mar 12 12:58:27 PM PDT 24
Finished Mar 12 12:58:47 PM PDT 24
Peak memory 244576 kb
Host smart-533c8b37-2b70-42b6-aa8b-513a71f9bce9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1265652999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.1265652999
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2101473429
Short name T156
Test name
Test status
Simulation time 67441365819 ps
CPU time 1198.43 seconds
Started Mar 12 12:58:27 PM PDT 24
Finished Mar 12 01:18:26 PM PDT 24
Peak memory 265112 kb
Host smart-62dadde7-13cf-46b8-bab4-7bea71c03dba
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101473429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.2101473429
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3471627101
Short name T794
Test name
Test status
Simulation time 379594272 ps
CPU time 7.84 seconds
Started Mar 12 12:58:24 PM PDT 24
Finished Mar 12 12:58:32 PM PDT 24
Peak memory 248448 kb
Host smart-1525b749-80f5-4909-9cc0-83f251e2e174
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3471627101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.3471627101
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3293069520
Short name T790
Test name
Test status
Simulation time 3257575616 ps
CPU time 248.83 seconds
Started Mar 12 12:58:08 PM PDT 24
Finished Mar 12 01:02:17 PM PDT 24
Peak memory 240052 kb
Host smart-13714ca9-1f6e-4033-b1c6-013540ea4721
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3293069520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.3293069520
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2533659215
Short name T737
Test name
Test status
Simulation time 6530556890 ps
CPU time 210.71 seconds
Started Mar 12 12:58:05 PM PDT 24
Finished Mar 12 01:01:36 PM PDT 24
Peak memory 236352 kb
Host smart-5de54e1a-5bf5-4279-b70c-fddbbd2ff8a8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2533659215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.2533659215
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1175982757
Short name T750
Test name
Test status
Simulation time 535054283 ps
CPU time 10.72 seconds
Started Mar 12 12:58:15 PM PDT 24
Finished Mar 12 12:58:26 PM PDT 24
Peak memory 240176 kb
Host smart-67397af5-2132-4711-a3b4-cabb9535cf1a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1175982757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.1175982757
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2316077258
Short name T346
Test name
Test status
Simulation time 57298184 ps
CPU time 5.65 seconds
Started Mar 12 12:58:15 PM PDT 24
Finished Mar 12 12:58:21 PM PDT 24
Peak memory 240380 kb
Host smart-5cc414cb-e40c-4f3b-8d11-6e70ad19c62c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316077258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.2316077258
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.3594969526
Short name T777
Test name
Test status
Simulation time 35547035 ps
CPU time 3.79 seconds
Started Mar 12 12:58:09 PM PDT 24
Finished Mar 12 12:58:13 PM PDT 24
Peak memory 236332 kb
Host smart-5dfeb95a-03d5-4d78-9388-e44b0138d72c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3594969526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.3594969526
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.3235860298
Short name T745
Test name
Test status
Simulation time 20445318 ps
CPU time 1.45 seconds
Started Mar 12 12:58:01 PM PDT 24
Finished Mar 12 12:58:02 PM PDT 24
Peak memory 235552 kb
Host smart-29f066ff-47bc-4df1-9198-9591cc7d620a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3235860298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.3235860298
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1089911795
Short name T764
Test name
Test status
Simulation time 1440951690 ps
CPU time 23.8 seconds
Started Mar 12 12:58:08 PM PDT 24
Finished Mar 12 12:58:33 PM PDT 24
Peak memory 244528 kb
Host smart-f82a96fc-969f-43f7-a0b0-21b556a47d52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1089911795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.1089911795
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.3526078868
Short name T147
Test name
Test status
Simulation time 2770375792 ps
CPU time 179.49 seconds
Started Mar 12 12:58:09 PM PDT 24
Finished Mar 12 01:01:08 PM PDT 24
Peak memory 265184 kb
Host smart-296be603-d1a8-4f8a-8af6-8e054afce419
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3526078868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.3526078868
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2515988750
Short name T344
Test name
Test status
Simulation time 8309363455 ps
CPU time 556.68 seconds
Started Mar 12 12:58:08 PM PDT 24
Finished Mar 12 01:07:25 PM PDT 24
Peak memory 265124 kb
Host smart-f906ae7c-aaca-49b0-bb34-53d8ee809c1a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515988750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.2515988750
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.2223716217
Short name T714
Test name
Test status
Simulation time 104727266 ps
CPU time 8.44 seconds
Started Mar 12 12:58:07 PM PDT 24
Finished Mar 12 12:58:16 PM PDT 24
Peak memory 251916 kb
Host smart-b1f03b29-1f4c-44d0-b213-e0a3c30a4e63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2223716217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.2223716217
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.3477336758
Short name T752
Test name
Test status
Simulation time 16216706 ps
CPU time 1.38 seconds
Started Mar 12 12:58:22 PM PDT 24
Finished Mar 12 12:58:24 PM PDT 24
Peak memory 236396 kb
Host smart-9184b9fd-ab94-4abc-94a3-4b907d313ebb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3477336758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.3477336758
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.2774858643
Short name T735
Test name
Test status
Simulation time 12921820 ps
CPU time 1.7 seconds
Started Mar 12 12:58:26 PM PDT 24
Finished Mar 12 12:58:29 PM PDT 24
Peak memory 235536 kb
Host smart-8e33f4a0-f4f9-4418-81ab-fca0b244b863
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2774858643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.2774858643
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.4158898936
Short name T803
Test name
Test status
Simulation time 10945579 ps
CPU time 1.25 seconds
Started Mar 12 12:58:26 PM PDT 24
Finished Mar 12 12:58:27 PM PDT 24
Peak memory 236432 kb
Host smart-e8bfc198-47c9-435a-93ff-693d13270436
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4158898936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.4158898936
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1499737051
Short name T761
Test name
Test status
Simulation time 9246685 ps
CPU time 1.53 seconds
Started Mar 12 12:58:27 PM PDT 24
Finished Mar 12 12:58:29 PM PDT 24
Peak memory 236384 kb
Host smart-4ac27478-ba1b-400b-ac85-fc72486f5a8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1499737051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.1499737051
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.676240618
Short name T162
Test name
Test status
Simulation time 16397864 ps
CPU time 1.45 seconds
Started Mar 12 12:58:26 PM PDT 24
Finished Mar 12 12:58:28 PM PDT 24
Peak memory 236416 kb
Host smart-fa9f6041-d25d-4d8b-bf3a-c976070ec3b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=676240618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.676240618
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.2765742596
Short name T767
Test name
Test status
Simulation time 10704886 ps
CPU time 1.31 seconds
Started Mar 12 12:58:19 PM PDT 24
Finished Mar 12 12:58:26 PM PDT 24
Peak memory 234528 kb
Host smart-49ebddf9-9ea9-4954-8c15-2564a79aac94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2765742596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.2765742596
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.1398831813
Short name T788
Test name
Test status
Simulation time 22868840 ps
CPU time 1.45 seconds
Started Mar 12 12:58:48 PM PDT 24
Finished Mar 12 12:58:50 PM PDT 24
Peak memory 235560 kb
Host smart-c56796c4-6888-49b7-8b52-834f651ce18c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1398831813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.1398831813
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.3264550805
Short name T825
Test name
Test status
Simulation time 12296494 ps
CPU time 1.29 seconds
Started Mar 12 12:58:26 PM PDT 24
Finished Mar 12 12:58:29 PM PDT 24
Peak memory 236348 kb
Host smart-8cf8008c-94c3-492d-a073-0d465ede70ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3264550805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.3264550805
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.254938645
Short name T177
Test name
Test status
Simulation time 8592241738 ps
CPU time 126.15 seconds
Started Mar 12 12:58:09 PM PDT 24
Finished Mar 12 01:00:15 PM PDT 24
Peak memory 236360 kb
Host smart-27e46e78-a9c2-4b9b-90f9-6a997d08e9d6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=254938645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.254938645
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3042661348
Short name T817
Test name
Test status
Simulation time 7710347294 ps
CPU time 434.2 seconds
Started Mar 12 12:58:09 PM PDT 24
Finished Mar 12 01:05:23 PM PDT 24
Peak memory 235488 kb
Host smart-0471f65a-0894-45c4-bafe-4b1b07edc59e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3042661348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3042661348
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.816684230
Short name T742
Test name
Test status
Simulation time 102856660 ps
CPU time 9.55 seconds
Started Mar 12 12:58:09 PM PDT 24
Finished Mar 12 12:58:19 PM PDT 24
Peak memory 240044 kb
Host smart-47bbeed5-c608-49a6-b02b-60e34ef21a41
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=816684230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.816684230
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2191626006
Short name T720
Test name
Test status
Simulation time 123592804 ps
CPU time 4.99 seconds
Started Mar 12 12:58:04 PM PDT 24
Finished Mar 12 12:58:09 PM PDT 24
Peak memory 240944 kb
Host smart-da1b175f-6330-4dd2-b73a-323150535478
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191626006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.2191626006
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.3538156863
Short name T755
Test name
Test status
Simulation time 353181379 ps
CPU time 8.16 seconds
Started Mar 12 12:58:13 PM PDT 24
Finished Mar 12 12:58:22 PM PDT 24
Peak memory 236264 kb
Host smart-8bbb58c1-9391-40cd-913d-475341a487e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3538156863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.3538156863
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.393953156
Short name T791
Test name
Test status
Simulation time 6774458 ps
CPU time 1.55 seconds
Started Mar 12 12:58:05 PM PDT 24
Finished Mar 12 12:58:06 PM PDT 24
Peak memory 235464 kb
Host smart-ed588a98-3c01-4a12-ab11-145c30f33298
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=393953156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.393953156
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2457438282
Short name T773
Test name
Test status
Simulation time 173804480 ps
CPU time 12.68 seconds
Started Mar 12 12:58:09 PM PDT 24
Finished Mar 12 12:58:22 PM PDT 24
Peak memory 244560 kb
Host smart-957e2823-6f82-48ff-9d54-750adbc0bbe8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2457438282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.2457438282
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.295929603
Short name T148
Test name
Test status
Simulation time 7555674951 ps
CPU time 209.2 seconds
Started Mar 12 12:58:06 PM PDT 24
Finished Mar 12 01:01:35 PM PDT 24
Peak memory 265176 kb
Host smart-6896e4c8-0ba2-40f7-9dc3-16aa9f434813
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=295929603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_error
s.295929603
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3282613578
Short name T818
Test name
Test status
Simulation time 98703723 ps
CPU time 7.46 seconds
Started Mar 12 12:58:16 PM PDT 24
Finished Mar 12 12:58:24 PM PDT 24
Peak memory 248512 kb
Host smart-74696c47-14dd-4b56-9c79-c74e0e7d9fb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3282613578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.3282613578
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.3677635605
Short name T805
Test name
Test status
Simulation time 36749188 ps
CPU time 1.39 seconds
Started Mar 12 12:58:26 PM PDT 24
Finished Mar 12 12:58:29 PM PDT 24
Peak memory 235416 kb
Host smart-c21ee148-2415-40ac-85be-562f67ca5939
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3677635605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.3677635605
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.181463403
Short name T334
Test name
Test status
Simulation time 7327874 ps
CPU time 1.24 seconds
Started Mar 12 12:58:28 PM PDT 24
Finished Mar 12 12:58:30 PM PDT 24
Peak memory 236396 kb
Host smart-ff0b23c9-7ae5-438f-a020-83b3aec9d4df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=181463403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.181463403
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3216390778
Short name T732
Test name
Test status
Simulation time 10155300 ps
CPU time 1.26 seconds
Started Mar 12 12:58:26 PM PDT 24
Finished Mar 12 12:58:28 PM PDT 24
Peak memory 236348 kb
Host smart-17693572-af25-4f36-ad5e-49785ca3ea4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3216390778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.3216390778
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.2455889479
Short name T335
Test name
Test status
Simulation time 8415887 ps
CPU time 1.27 seconds
Started Mar 12 12:58:28 PM PDT 24
Finished Mar 12 12:58:30 PM PDT 24
Peak memory 234512 kb
Host smart-f505fad7-3235-4fbd-a62b-76040107ba7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2455889479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.2455889479
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.780985358
Short name T770
Test name
Test status
Simulation time 7679594 ps
CPU time 1.46 seconds
Started Mar 12 12:58:28 PM PDT 24
Finished Mar 12 12:58:30 PM PDT 24
Peak memory 236392 kb
Host smart-27a07dd5-a8de-451e-9f07-c436df21ea46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=780985358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.780985358
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2063091706
Short name T786
Test name
Test status
Simulation time 7563799 ps
CPU time 1.5 seconds
Started Mar 12 12:58:18 PM PDT 24
Finished Mar 12 12:58:20 PM PDT 24
Peak memory 235492 kb
Host smart-ca56c9b0-7a96-47e4-9ae7-6ba19a0a8e1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2063091706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.2063091706
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.3818098180
Short name T772
Test name
Test status
Simulation time 6388539 ps
CPU time 1.36 seconds
Started Mar 12 12:58:38 PM PDT 24
Finished Mar 12 12:58:40 PM PDT 24
Peak memory 235512 kb
Host smart-e47c6f77-cc53-4dd9-8d17-ce22993f22fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3818098180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.3818098180
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1115072660
Short name T238
Test name
Test status
Simulation time 6717238 ps
CPU time 1.45 seconds
Started Mar 12 12:58:38 PM PDT 24
Finished Mar 12 12:58:40 PM PDT 24
Peak memory 236296 kb
Host smart-27780330-7cac-402e-9126-c3d4a7726679
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1115072660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.1115072660
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.4095202721
Short name T814
Test name
Test status
Simulation time 15168652 ps
CPU time 1.36 seconds
Started Mar 12 12:58:30 PM PDT 24
Finished Mar 12 12:58:31 PM PDT 24
Peak memory 234496 kb
Host smart-cd5e6ef0-bba7-4e38-a11b-ddde41635180
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4095202721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.4095202721
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.1958098776
Short name T721
Test name
Test status
Simulation time 6665884 ps
CPU time 1.38 seconds
Started Mar 12 12:58:31 PM PDT 24
Finished Mar 12 12:58:32 PM PDT 24
Peak memory 236388 kb
Host smart-d6271a80-032e-4417-9f46-61db5511d7ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1958098776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.1958098776
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2785418611
Short name T743
Test name
Test status
Simulation time 1446015553 ps
CPU time 139.86 seconds
Started Mar 12 12:58:09 PM PDT 24
Finished Mar 12 01:00:29 PM PDT 24
Peak memory 240140 kb
Host smart-a3a6385e-da35-4f52-94ed-9c659aa8abbe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2785418611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.2785418611
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2726166224
Short name T780
Test name
Test status
Simulation time 1704558051 ps
CPU time 202.27 seconds
Started Mar 12 12:58:08 PM PDT 24
Finished Mar 12 01:01:30 PM PDT 24
Peak memory 240172 kb
Host smart-0d1f4257-612b-4b44-9b03-45c88f68e30d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2726166224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.2726166224
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2581475650
Short name T804
Test name
Test status
Simulation time 46366858 ps
CPU time 6.56 seconds
Started Mar 12 12:58:09 PM PDT 24
Finished Mar 12 12:58:16 PM PDT 24
Peak memory 240208 kb
Host smart-a1b882ca-c1c4-42dc-b6b3-92c7ad96b4f4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2581475650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.2581475650
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.4176301270
Short name T717
Test name
Test status
Simulation time 391571485 ps
CPU time 7.9 seconds
Started Mar 12 12:58:08 PM PDT 24
Finished Mar 12 12:58:16 PM PDT 24
Peak memory 237848 kb
Host smart-fddaf3bb-01e2-4266-83bb-cbcee69245f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176301270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.4176301270
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.2207981896
Short name T751
Test name
Test status
Simulation time 34607701 ps
CPU time 6.6 seconds
Started Mar 12 12:58:09 PM PDT 24
Finished Mar 12 12:58:16 PM PDT 24
Peak memory 236216 kb
Host smart-cfe541c5-e7ad-4538-8c8f-46397622a3f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2207981896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.2207981896
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2219937747
Short name T801
Test name
Test status
Simulation time 12078871 ps
CPU time 1.57 seconds
Started Mar 12 12:58:09 PM PDT 24
Finished Mar 12 12:58:10 PM PDT 24
Peak memory 236380 kb
Host smart-7300ea7a-fff7-4442-ab63-a54bf781a89a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2219937747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.2219937747
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1777521986
Short name T781
Test name
Test status
Simulation time 323420061 ps
CPU time 11.6 seconds
Started Mar 12 12:58:10 PM PDT 24
Finished Mar 12 12:58:21 PM PDT 24
Peak memory 240284 kb
Host smart-4ff8cc90-22f9-46f3-b3ba-bb09f31e4483
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1777521986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.1777521986
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.689998393
Short name T134
Test name
Test status
Simulation time 12267731489 ps
CPU time 477.8 seconds
Started Mar 12 12:58:09 PM PDT 24
Finished Mar 12 01:06:07 PM PDT 24
Peak memory 268684 kb
Host smart-7720376b-4583-4444-b503-7d12b71a24ca
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689998393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.689998393
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.3003864564
Short name T719
Test name
Test status
Simulation time 60967016 ps
CPU time 6.75 seconds
Started Mar 12 12:58:17 PM PDT 24
Finished Mar 12 12:58:24 PM PDT 24
Peak memory 248440 kb
Host smart-676ccb4f-e99a-488a-8480-f26add370451
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3003864564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.3003864564
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.716644448
Short name T730
Test name
Test status
Simulation time 6444206 ps
CPU time 1.43 seconds
Started Mar 12 12:58:41 PM PDT 24
Finished Mar 12 12:58:42 PM PDT 24
Peak memory 236288 kb
Host smart-83cd7054-e414-4975-aa54-24965018c572
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=716644448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.716644448
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1669719758
Short name T711
Test name
Test status
Simulation time 8660267 ps
CPU time 1.45 seconds
Started Mar 12 12:58:28 PM PDT 24
Finished Mar 12 12:58:30 PM PDT 24
Peak memory 235532 kb
Host smart-ff8f8811-cf9a-47e2-b767-2354b2230b5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1669719758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.1669719758
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.68874836
Short name T338
Test name
Test status
Simulation time 10590020 ps
CPU time 1.21 seconds
Started Mar 12 12:58:28 PM PDT 24
Finished Mar 12 12:58:30 PM PDT 24
Peak memory 234484 kb
Host smart-4b871da9-a65d-4cac-9e05-99dd0e319236
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=68874836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.68874836
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.810612125
Short name T775
Test name
Test status
Simulation time 18523527 ps
CPU time 1.87 seconds
Started Mar 12 12:58:27 PM PDT 24
Finished Mar 12 12:58:30 PM PDT 24
Peak memory 234504 kb
Host smart-e65862f1-7d43-46e5-829e-fdf35fc329aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=810612125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.810612125
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.1028242315
Short name T796
Test name
Test status
Simulation time 7771725 ps
CPU time 1.34 seconds
Started Mar 12 12:58:30 PM PDT 24
Finished Mar 12 12:58:31 PM PDT 24
Peak memory 236392 kb
Host smart-4fb74b40-dd51-4299-8a6c-7772249f1c15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1028242315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.1028242315
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3359613047
Short name T739
Test name
Test status
Simulation time 10078511 ps
CPU time 1.51 seconds
Started Mar 12 12:58:41 PM PDT 24
Finished Mar 12 12:58:42 PM PDT 24
Peak memory 236296 kb
Host smart-ab6930cf-1de7-4979-8130-147f1bac88b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3359613047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.3359613047
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.907103790
Short name T744
Test name
Test status
Simulation time 19318822 ps
CPU time 1.33 seconds
Started Mar 12 12:58:46 PM PDT 24
Finished Mar 12 12:58:47 PM PDT 24
Peak memory 235412 kb
Host smart-8501803f-7e0d-4e56-ae82-83e3f265fd40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=907103790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.907103790
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.3720670453
Short name T809
Test name
Test status
Simulation time 6369957 ps
CPU time 1.33 seconds
Started Mar 12 12:58:28 PM PDT 24
Finished Mar 12 12:58:29 PM PDT 24
Peak memory 234588 kb
Host smart-6c31cb86-410c-4732-bfbf-35d465cd2b2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3720670453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.3720670453
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2817374099
Short name T816
Test name
Test status
Simulation time 55148506 ps
CPU time 1.3 seconds
Started Mar 12 12:58:22 PM PDT 24
Finished Mar 12 12:58:24 PM PDT 24
Peak memory 236252 kb
Host smart-5882c010-7bf9-439d-b5cc-56191fed79b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2817374099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.2817374099
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.1288863232
Short name T774
Test name
Test status
Simulation time 14451154 ps
CPU time 1.15 seconds
Started Mar 12 12:58:26 PM PDT 24
Finished Mar 12 12:58:27 PM PDT 24
Peak memory 236376 kb
Host smart-a800b76d-f9fa-45d6-8cd7-f0abcfba5487
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1288863232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.1288863232
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.492377384
Short name T759
Test name
Test status
Simulation time 60432739 ps
CPU time 5.64 seconds
Started Mar 12 12:58:13 PM PDT 24
Finished Mar 12 12:58:19 PM PDT 24
Peak memory 240956 kb
Host smart-70c6236d-1685-475f-8189-776cdc95ab56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492377384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.alert_handler_csr_mem_rw_with_rand_reset.492377384
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.3475155859
Short name T822
Test name
Test status
Simulation time 128084886 ps
CPU time 5.87 seconds
Started Mar 12 12:58:09 PM PDT 24
Finished Mar 12 12:58:15 PM PDT 24
Peak memory 236288 kb
Host smart-15cb5ae6-e7c0-4c46-af73-bd89e4e0a518
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3475155859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.3475155859
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.357644212
Short name T792
Test name
Test status
Simulation time 87181017 ps
CPU time 1.36 seconds
Started Mar 12 12:58:08 PM PDT 24
Finished Mar 12 12:58:09 PM PDT 24
Peak memory 235412 kb
Host smart-8febf7d8-53ad-460f-bd56-f233da9ee5e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=357644212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.357644212
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.2959651492
Short name T727
Test name
Test status
Simulation time 176949304 ps
CPU time 10.41 seconds
Started Mar 12 12:58:08 PM PDT 24
Finished Mar 12 12:58:19 PM PDT 24
Peak memory 243688 kb
Host smart-66305602-97ab-47e8-880d-9895d33280aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2959651492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.2959651492
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.2688589203
Short name T138
Test name
Test status
Simulation time 1015319436 ps
CPU time 94.94 seconds
Started Mar 12 12:58:07 PM PDT 24
Finished Mar 12 12:59:42 PM PDT 24
Peak memory 256852 kb
Host smart-55766ae5-c217-4deb-971c-e8ea73a8f84d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2688589203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.2688589203
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1756575966
Short name T137
Test name
Test status
Simulation time 8882608881 ps
CPU time 307.32 seconds
Started Mar 12 12:58:06 PM PDT 24
Finished Mar 12 01:03:14 PM PDT 24
Peak memory 265196 kb
Host smart-b9fb11c4-5f84-4401-b139-573c841df590
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756575966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.1756575966
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.1024235657
Short name T760
Test name
Test status
Simulation time 627617469 ps
CPU time 10.98 seconds
Started Mar 12 12:58:13 PM PDT 24
Finished Mar 12 12:58:24 PM PDT 24
Peak memory 252244 kb
Host smart-956e2469-1c2b-45d0-af8b-5c6c4fa9a352
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1024235657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.1024235657
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3317521153
Short name T726
Test name
Test status
Simulation time 81286659 ps
CPU time 7.56 seconds
Started Mar 12 12:58:09 PM PDT 24
Finished Mar 12 12:58:17 PM PDT 24
Peak memory 238952 kb
Host smart-03deaae3-ac46-4333-81f1-e47cbcda60c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317521153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.3317521153
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.2728820126
Short name T793
Test name
Test status
Simulation time 33874422 ps
CPU time 5.54 seconds
Started Mar 12 12:58:10 PM PDT 24
Finished Mar 12 12:58:16 PM PDT 24
Peak memory 235428 kb
Host smart-7e642e61-e769-4c65-b5ba-fa50bcd909b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2728820126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.2728820126
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3709234643
Short name T337
Test name
Test status
Simulation time 15348444 ps
CPU time 1.67 seconds
Started Mar 12 12:58:11 PM PDT 24
Finished Mar 12 12:58:13 PM PDT 24
Peak memory 236424 kb
Host smart-506085c9-b498-4184-88c1-a2c6319ef65a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3709234643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.3709234643
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3866426951
Short name T820
Test name
Test status
Simulation time 357534965 ps
CPU time 13.58 seconds
Started Mar 12 12:58:09 PM PDT 24
Finished Mar 12 12:58:23 PM PDT 24
Peak memory 244584 kb
Host smart-84b19437-ed99-4c50-9484-4d982fe5095b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3866426951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.3866426951
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1695520509
Short name T133
Test name
Test status
Simulation time 1548003979 ps
CPU time 191.16 seconds
Started Mar 12 12:58:10 PM PDT 24
Finished Mar 12 01:01:21 PM PDT 24
Peak memory 265144 kb
Host smart-79fe7329-2dd8-448f-b123-0971dc4d0a1f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1695520509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.1695520509
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1411207165
Short name T154
Test name
Test status
Simulation time 27080934817 ps
CPU time 468.44 seconds
Started Mar 12 12:58:04 PM PDT 24
Finished Mar 12 01:05:53 PM PDT 24
Peak memory 265452 kb
Host smart-1e224710-9b9d-4aab-b1f9-0bbfd68f3a83
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411207165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.1411207165
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3621897750
Short name T821
Test name
Test status
Simulation time 222305055 ps
CPU time 15.44 seconds
Started Mar 12 12:58:10 PM PDT 24
Finished Mar 12 12:58:26 PM PDT 24
Peak memory 248496 kb
Host smart-8ff4cb97-1340-41d1-805f-2914ff3fbcc6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3621897750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.3621897750
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.511451842
Short name T342
Test name
Test status
Simulation time 57314459 ps
CPU time 5.56 seconds
Started Mar 12 12:58:16 PM PDT 24
Finished Mar 12 12:58:22 PM PDT 24
Peak memory 248584 kb
Host smart-d9074b46-e495-4a69-989a-ff21c67bbf56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511451842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.alert_handler_csr_mem_rw_with_rand_reset.511451842
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1568956379
Short name T731
Test name
Test status
Simulation time 954512353 ps
CPU time 10.1 seconds
Started Mar 12 12:58:09 PM PDT 24
Finished Mar 12 12:58:19 PM PDT 24
Peak memory 236288 kb
Host smart-aee46f52-0e94-466e-93ae-b133cb24f709
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1568956379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.1568956379
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.4060404342
Short name T336
Test name
Test status
Simulation time 9216848 ps
CPU time 1.43 seconds
Started Mar 12 12:58:07 PM PDT 24
Finished Mar 12 12:58:08 PM PDT 24
Peak memory 234540 kb
Host smart-5b598d17-5e05-4100-b7da-536dc19c8b9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4060404342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.4060404342
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3732474733
Short name T190
Test name
Test status
Simulation time 1778432617 ps
CPU time 42.58 seconds
Started Mar 12 12:58:03 PM PDT 24
Finished Mar 12 12:58:45 PM PDT 24
Peak memory 244556 kb
Host smart-2f43f5d7-28e7-416f-aa03-7f6e786e72d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3732474733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.3732474733
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1520526876
Short name T125
Test name
Test status
Simulation time 4892128695 ps
CPU time 159.1 seconds
Started Mar 12 12:58:06 PM PDT 24
Finished Mar 12 01:00:45 PM PDT 24
Peak memory 255996 kb
Host smart-72ad4d8c-ca91-4b93-9897-9b837f96d81a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1520526876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.1520526876
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2873046096
Short name T725
Test name
Test status
Simulation time 1209267149 ps
CPU time 19.62 seconds
Started Mar 12 12:58:09 PM PDT 24
Finished Mar 12 12:58:29 PM PDT 24
Peak memory 251920 kb
Host smart-607a0089-3911-40cd-9937-844ade3e046b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2873046096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.2873046096
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.4212713884
Short name T768
Test name
Test status
Simulation time 536229919 ps
CPU time 11.31 seconds
Started Mar 12 12:58:10 PM PDT 24
Finished Mar 12 12:58:22 PM PDT 24
Peak memory 255172 kb
Host smart-7eb9c437-0283-45a3-b1d3-ec7f2ba3134b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212713884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.4212713884
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.2162255967
Short name T798
Test name
Test status
Simulation time 20196341 ps
CPU time 3.86 seconds
Started Mar 12 12:58:13 PM PDT 24
Finished Mar 12 12:58:17 PM PDT 24
Peak memory 240128 kb
Host smart-93959449-734c-42af-846b-0ac970393b76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2162255967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.2162255967
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1330779243
Short name T763
Test name
Test status
Simulation time 24370668 ps
CPU time 1.53 seconds
Started Mar 12 12:58:09 PM PDT 24
Finished Mar 12 12:58:10 PM PDT 24
Peak memory 236424 kb
Host smart-1457a4c9-9d56-4e86-a270-eafcbbf3b823
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1330779243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.1330779243
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2052325701
Short name T807
Test name
Test status
Simulation time 176531220 ps
CPU time 12.54 seconds
Started Mar 12 12:58:14 PM PDT 24
Finished Mar 12 12:58:27 PM PDT 24
Peak memory 244584 kb
Host smart-57614708-499d-440c-a471-7b89806653dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2052325701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.2052325701
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.117841571
Short name T143
Test name
Test status
Simulation time 1693786827 ps
CPU time 109.86 seconds
Started Mar 12 12:58:13 PM PDT 24
Finished Mar 12 01:00:03 PM PDT 24
Peak memory 256824 kb
Host smart-6d261e3e-0166-4aed-93a2-2005768bfc8f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=117841571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_error
s.117841571
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.470251277
Short name T136
Test name
Test status
Simulation time 61441453043 ps
CPU time 529.66 seconds
Started Mar 12 12:58:05 PM PDT 24
Finished Mar 12 01:06:55 PM PDT 24
Peak memory 268720 kb
Host smart-0f62cfe2-daf9-467b-a703-eef8aa02cbc9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470251277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.470251277
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.2787738371
Short name T813
Test name
Test status
Simulation time 1487318690 ps
CPU time 22.23 seconds
Started Mar 12 12:58:06 PM PDT 24
Finished Mar 12 12:58:28 PM PDT 24
Peak memory 248500 kb
Host smart-7e355713-2a8c-47cb-816f-3f2646d789d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2787738371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.2787738371
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1469048765
Short name T740
Test name
Test status
Simulation time 510830514 ps
CPU time 8.62 seconds
Started Mar 12 12:58:13 PM PDT 24
Finished Mar 12 12:58:22 PM PDT 24
Peak memory 240312 kb
Host smart-a7d26515-5391-4a8e-a417-0304cf0c127b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469048765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.1469048765
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.1060175515
Short name T341
Test name
Test status
Simulation time 355196599 ps
CPU time 7.79 seconds
Started Mar 12 12:58:10 PM PDT 24
Finished Mar 12 12:58:18 PM PDT 24
Peak memory 240220 kb
Host smart-374addf7-34a8-4bc2-a573-6767199bbd73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1060175515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.1060175515
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.3784233577
Short name T799
Test name
Test status
Simulation time 9593561 ps
CPU time 1.37 seconds
Started Mar 12 12:58:10 PM PDT 24
Finished Mar 12 12:58:12 PM PDT 24
Peak memory 234504 kb
Host smart-b00ac8a5-85ca-46eb-b514-f69ec8f9221c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3784233577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.3784233577
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.728068193
Short name T754
Test name
Test status
Simulation time 315976293 ps
CPU time 20.31 seconds
Started Mar 12 12:58:09 PM PDT 24
Finished Mar 12 12:58:29 PM PDT 24
Peak memory 244576 kb
Host smart-5bb0faea-0069-47fd-be57-c8d2753c94dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=728068193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_outs
tanding.728068193
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.4250969963
Short name T122
Test name
Test status
Simulation time 5629482716 ps
CPU time 201.12 seconds
Started Mar 12 12:58:10 PM PDT 24
Finished Mar 12 01:01:31 PM PDT 24
Peak memory 265184 kb
Host smart-9b165f4f-6fa9-44b2-9e48-538bd0a5bc71
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4250969963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.4250969963
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1460445357
Short name T784
Test name
Test status
Simulation time 186646435 ps
CPU time 7.46 seconds
Started Mar 12 12:58:06 PM PDT 24
Finished Mar 12 12:58:13 PM PDT 24
Peak memory 251440 kb
Host smart-c53852db-c2c1-4aab-9c7c-c15844e0656c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1460445357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.1460445357
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3552831308
Short name T193
Test name
Test status
Simulation time 251413521 ps
CPU time 3.22 seconds
Started Mar 12 12:58:10 PM PDT 24
Finished Mar 12 12:58:13 PM PDT 24
Peak memory 236848 kb
Host smart-a9fc9530-5d47-4a19-a35c-bbb5b0998f20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3552831308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.3552831308
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.1273410177
Short name T521
Test name
Test status
Simulation time 108459383951 ps
CPU time 1799.58 seconds
Started Mar 12 01:39:12 PM PDT 24
Finished Mar 12 02:09:12 PM PDT 24
Peak memory 283168 kb
Host smart-3faacd88-5bf5-4969-907e-14cf1981286d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273410177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.1273410177
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.1162742359
Short name T450
Test name
Test status
Simulation time 1686095129 ps
CPU time 70.59 seconds
Started Mar 12 01:39:13 PM PDT 24
Finished Mar 12 01:40:24 PM PDT 24
Peak memory 248524 kb
Host smart-caab7245-bc45-4ef2-a22b-35985c922cf4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1162742359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.1162742359
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.915029380
Short name T390
Test name
Test status
Simulation time 13093164420 ps
CPU time 192.23 seconds
Started Mar 12 01:39:14 PM PDT 24
Finished Mar 12 01:42:28 PM PDT 24
Peak memory 256336 kb
Host smart-a644fb5e-d5f1-4e9a-91fc-991caaf3bc3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91502
9380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.915029380
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.2370360406
Short name T356
Test name
Test status
Simulation time 13050854216 ps
CPU time 38.21 seconds
Started Mar 12 01:39:12 PM PDT 24
Finished Mar 12 01:39:50 PM PDT 24
Peak memory 254948 kb
Host smart-1f2e5784-c875-49ba-bf01-5d6e2968870d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23703
60406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.2370360406
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.681677677
Short name T282
Test name
Test status
Simulation time 33436202786 ps
CPU time 770.89 seconds
Started Mar 12 01:39:12 PM PDT 24
Finished Mar 12 01:52:03 PM PDT 24
Peak memory 272444 kb
Host smart-0eb6b1c5-d3a8-416a-9984-cd2fb6ad3c3d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681677677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.681677677
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.2159573035
Short name T684
Test name
Test status
Simulation time 14733288786 ps
CPU time 1483.83 seconds
Started Mar 12 01:39:07 PM PDT 24
Finished Mar 12 02:03:51 PM PDT 24
Peak memory 288700 kb
Host smart-6fc00f1c-2b2e-4114-b7d1-bf0da2b74adb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159573035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.2159573035
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.3902711171
Short name T280
Test name
Test status
Simulation time 1588844409 ps
CPU time 39.11 seconds
Started Mar 12 01:39:15 PM PDT 24
Finished Mar 12 01:39:56 PM PDT 24
Peak memory 255456 kb
Host smart-8a172cb2-9ab0-4f41-8c76-73223f8df06a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39027
11171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.3902711171
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.3082896778
Short name T555
Test name
Test status
Simulation time 965417177 ps
CPU time 9.84 seconds
Started Mar 12 01:39:17 PM PDT 24
Finished Mar 12 01:39:32 PM PDT 24
Peak memory 250592 kb
Host smart-b15c05d5-dc16-4bed-88a1-b8127b6d5d8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30828
96778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.3082896778
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.2139347059
Short name T33
Test name
Test status
Simulation time 476053063 ps
CPU time 14.39 seconds
Started Mar 12 01:39:00 PM PDT 24
Finished Mar 12 01:39:14 PM PDT 24
Peak memory 273160 kb
Host smart-b3602958-1168-41d0-90a5-0276692e63fa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2139347059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.2139347059
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.4157460917
Short name T284
Test name
Test status
Simulation time 1964781070 ps
CPU time 33.62 seconds
Started Mar 12 01:39:14 PM PDT 24
Finished Mar 12 01:39:48 PM PDT 24
Peak memory 246800 kb
Host smart-4569e0cc-07e1-49ef-b5df-3fe079be44f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41574
60917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.4157460917
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.3182825228
Short name T352
Test name
Test status
Simulation time 537404376 ps
CPU time 12.59 seconds
Started Mar 12 01:39:13 PM PDT 24
Finished Mar 12 01:39:27 PM PDT 24
Peak memory 256732 kb
Host smart-ac0eae21-9b33-4986-9c6b-58146611962a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31828
25228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.3182825228
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.1224416027
Short name T481
Test name
Test status
Simulation time 3025107714 ps
CPU time 205.41 seconds
Started Mar 12 01:39:12 PM PDT 24
Finished Mar 12 01:42:38 PM PDT 24
Peak memory 254940 kb
Host smart-5d548ce4-46f2-4956-afa5-2c42e666e230
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224416027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.1224416027
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.3591721862
Short name T591
Test name
Test status
Simulation time 44130547500 ps
CPU time 2590.5 seconds
Started Mar 12 01:39:07 PM PDT 24
Finished Mar 12 02:22:18 PM PDT 24
Peak memory 288576 kb
Host smart-05dd6cad-cb42-44ee-bc05-ec732b8c177c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591721862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.3591721862
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.611355989
Short name T237
Test name
Test status
Simulation time 1135241016 ps
CPU time 54.4 seconds
Started Mar 12 01:38:53 PM PDT 24
Finished Mar 12 01:39:47 PM PDT 24
Peak memory 247968 kb
Host smart-475d3b88-9271-4445-a5be-4dcd49623e22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61135
5989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.611355989
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.419349823
Short name T547
Test name
Test status
Simulation time 700929866 ps
CPU time 39.89 seconds
Started Mar 12 01:38:35 PM PDT 24
Finished Mar 12 01:39:15 PM PDT 24
Peak memory 254280 kb
Host smart-e78183a1-8823-484c-916d-3a59c75467ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41934
9823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.419349823
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.212443202
Short name T62
Test name
Test status
Simulation time 35325775501 ps
CPU time 709.51 seconds
Started Mar 12 01:38:57 PM PDT 24
Finished Mar 12 01:50:46 PM PDT 24
Peak memory 269496 kb
Host smart-eb8326f1-f7bb-4424-b47f-3e08a516730a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212443202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.212443202
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.2533526462
Short name T529
Test name
Test status
Simulation time 18093243327 ps
CPU time 1086.25 seconds
Started Mar 12 01:39:12 PM PDT 24
Finished Mar 12 01:57:19 PM PDT 24
Peak memory 272124 kb
Host smart-35cca0e2-5a52-45c7-bdb0-c138ae870b0c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533526462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.2533526462
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.1871471299
Short name T682
Test name
Test status
Simulation time 13517926219 ps
CPU time 568.88 seconds
Started Mar 12 01:39:01 PM PDT 24
Finished Mar 12 01:48:30 PM PDT 24
Peak memory 247392 kb
Host smart-366ce7bd-f375-48d4-b8bb-213f621e011b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871471299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.1871471299
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.716942722
Short name T509
Test name
Test status
Simulation time 1242498706 ps
CPU time 75.02 seconds
Started Mar 12 01:39:07 PM PDT 24
Finished Mar 12 01:40:23 PM PDT 24
Peak memory 248500 kb
Host smart-61716b20-ff54-4e7b-b08d-ed79436e9972
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71694
2722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.716942722
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.1996218737
Short name T656
Test name
Test status
Simulation time 749631502 ps
CPU time 50.44 seconds
Started Mar 12 01:39:07 PM PDT 24
Finished Mar 12 01:39:58 PM PDT 24
Peak memory 248048 kb
Host smart-1e19dd1f-93f0-4b3b-9bf9-2804b7dd6447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19962
18737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.1996218737
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.924155970
Short name T10
Test name
Test status
Simulation time 896688044 ps
CPU time 13.55 seconds
Started Mar 12 01:39:14 PM PDT 24
Finished Mar 12 01:39:30 PM PDT 24
Peak memory 269208 kb
Host smart-78f1c326-b3ca-4b5b-8f6c-5569c835b459
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=924155970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.924155970
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.4238979671
Short name T507
Test name
Test status
Simulation time 816403711 ps
CPU time 53.13 seconds
Started Mar 12 01:39:14 PM PDT 24
Finished Mar 12 01:40:08 PM PDT 24
Peak memory 255196 kb
Host smart-10fa5ca7-0543-421c-aba9-fb6d060707d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42389
79671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.4238979671
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.739072967
Short name T115
Test name
Test status
Simulation time 356767573 ps
CPU time 24.44 seconds
Started Mar 12 01:39:12 PM PDT 24
Finished Mar 12 01:39:36 PM PDT 24
Peak memory 248684 kb
Host smart-30973348-9969-4ce9-81a4-efe905a7d964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73907
2967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.739072967
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.1451621238
Short name T268
Test name
Test status
Simulation time 8638229802 ps
CPU time 419.85 seconds
Started Mar 12 01:39:01 PM PDT 24
Finished Mar 12 01:46:01 PM PDT 24
Peak memory 254648 kb
Host smart-f5d9647e-eed0-4216-b4ad-719845ba3d3e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451621238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.1451621238
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.432266946
Short name T215
Test name
Test status
Simulation time 137930699 ps
CPU time 2.26 seconds
Started Mar 12 01:39:16 PM PDT 24
Finished Mar 12 01:39:24 PM PDT 24
Peak memory 248712 kb
Host smart-daa7d1c0-f6e9-4cac-93ea-5cdd4d016ec5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=432266946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.432266946
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.1354603985
Short name T401
Test name
Test status
Simulation time 1683792042 ps
CPU time 13.01 seconds
Started Mar 12 01:39:18 PM PDT 24
Finished Mar 12 01:39:36 PM PDT 24
Peak memory 240336 kb
Host smart-0fac74a9-c373-4795-9e51-99a9429a328e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1354603985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.1354603985
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.4209521836
Short name T351
Test name
Test status
Simulation time 2170866529 ps
CPU time 112.75 seconds
Started Mar 12 01:38:48 PM PDT 24
Finished Mar 12 01:40:41 PM PDT 24
Peak memory 256104 kb
Host smart-3e943cab-49ff-48d8-b764-7e632669ccc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42095
21836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.4209521836
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.961181067
Short name T114
Test name
Test status
Simulation time 3012595359 ps
CPU time 30.05 seconds
Started Mar 12 01:38:55 PM PDT 24
Finished Mar 12 01:39:25 PM PDT 24
Peak memory 256184 kb
Host smart-77f7042f-642e-4ce8-b275-d54ffea324ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96118
1067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.961181067
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.3942270873
Short name T321
Test name
Test status
Simulation time 92132764248 ps
CPU time 2635.9 seconds
Started Mar 12 01:39:18 PM PDT 24
Finished Mar 12 02:23:19 PM PDT 24
Peak memory 289156 kb
Host smart-94b8d78f-e152-44ca-b02f-24769d095daa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942270873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.3942270873
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.1380647847
Short name T508
Test name
Test status
Simulation time 36082911133 ps
CPU time 2085.94 seconds
Started Mar 12 01:38:51 PM PDT 24
Finished Mar 12 02:13:38 PM PDT 24
Peak memory 288660 kb
Host smart-9a5befb9-6162-4e2a-84d8-7aae7a853e7b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380647847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1380647847
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.3821617762
Short name T697
Test name
Test status
Simulation time 23283448407 ps
CPU time 496.02 seconds
Started Mar 12 01:39:14 PM PDT 24
Finished Mar 12 01:47:32 PM PDT 24
Peak memory 246448 kb
Host smart-56d4d281-b138-4939-b805-b89c291e3587
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821617762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3821617762
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.2307531787
Short name T392
Test name
Test status
Simulation time 60103424 ps
CPU time 4.81 seconds
Started Mar 12 01:39:14 PM PDT 24
Finished Mar 12 01:39:20 PM PDT 24
Peak memory 240336 kb
Host smart-f30d9dc1-7c1b-4754-a398-333d30064cd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23075
31787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.2307531787
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.4241450317
Short name T511
Test name
Test status
Simulation time 787926413 ps
CPU time 33.04 seconds
Started Mar 12 01:39:14 PM PDT 24
Finished Mar 12 01:39:50 PM PDT 24
Peak memory 246812 kb
Host smart-5d471004-e848-45a1-b259-5ff03dfc1a4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42414
50317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.4241450317
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.3161569788
Short name T675
Test name
Test status
Simulation time 778171901 ps
CPU time 57.34 seconds
Started Mar 12 01:39:03 PM PDT 24
Finished Mar 12 01:40:01 PM PDT 24
Peak memory 247136 kb
Host smart-7959385b-266f-492b-b088-5cd199b3680f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31615
69788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.3161569788
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.3164068229
Short name T688
Test name
Test status
Simulation time 293520172 ps
CPU time 9.62 seconds
Started Mar 12 01:39:13 PM PDT 24
Finished Mar 12 01:39:24 PM PDT 24
Peak memory 248528 kb
Host smart-57befb81-cf6c-4210-99e9-7e39424d89f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31640
68229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.3164068229
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.2698718580
Short name T674
Test name
Test status
Simulation time 5312717159 ps
CPU time 528.11 seconds
Started Mar 12 01:38:45 PM PDT 24
Finished Mar 12 01:47:33 PM PDT 24
Peak memory 264964 kb
Host smart-222c1303-1241-4198-a220-5ebb71e14a39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698718580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.2698718580
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.3902048739
Short name T596
Test name
Test status
Simulation time 566217816 ps
CPU time 25.75 seconds
Started Mar 12 01:39:16 PM PDT 24
Finished Mar 12 01:39:47 PM PDT 24
Peak memory 240316 kb
Host smart-70fbb65c-e432-4960-97fa-fcf7f4289e8f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3902048739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.3902048739
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.237216468
Short name T565
Test name
Test status
Simulation time 3401373110 ps
CPU time 189.46 seconds
Started Mar 12 01:39:15 PM PDT 24
Finished Mar 12 01:42:27 PM PDT 24
Peak memory 255928 kb
Host smart-a7bf7dcf-fddd-4f4c-ab1f-53ba5293af60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23721
6468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.237216468
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.506448665
Short name T431
Test name
Test status
Simulation time 1098848206 ps
CPU time 60.11 seconds
Started Mar 12 01:39:18 PM PDT 24
Finished Mar 12 01:40:23 PM PDT 24
Peak memory 255852 kb
Host smart-85146d90-f84f-4791-8b0b-46466b2a484a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50644
8665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.506448665
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.1384898342
Short name T696
Test name
Test status
Simulation time 21861845811 ps
CPU time 1243.76 seconds
Started Mar 12 01:38:32 PM PDT 24
Finished Mar 12 01:59:16 PM PDT 24
Peak memory 288464 kb
Host smart-b19bbdd5-18a7-4527-98a4-14c7420d2247
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384898342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.1384898342
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.1056815338
Short name T468
Test name
Test status
Simulation time 667858111 ps
CPU time 20.28 seconds
Started Mar 12 01:39:15 PM PDT 24
Finished Mar 12 01:39:40 PM PDT 24
Peak memory 248532 kb
Host smart-052ad9db-e908-49e3-bd09-e9971a987001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10568
15338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.1056815338
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.2168126200
Short name T629
Test name
Test status
Simulation time 331937733 ps
CPU time 18.73 seconds
Started Mar 12 01:39:15 PM PDT 24
Finished Mar 12 01:39:36 PM PDT 24
Peak memory 254808 kb
Host smart-d04d9c71-825f-4627-be59-e05949e18aef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21681
26200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2168126200
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.3699396276
Short name T430
Test name
Test status
Simulation time 98982571 ps
CPU time 8.09 seconds
Started Mar 12 01:39:18 PM PDT 24
Finished Mar 12 01:39:31 PM PDT 24
Peak memory 248252 kb
Host smart-e4118754-b150-422c-a836-40e32d91ea11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36993
96276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.3699396276
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.4093344695
Short name T391
Test name
Test status
Simulation time 5472508340 ps
CPU time 40.5 seconds
Started Mar 12 01:38:24 PM PDT 24
Finished Mar 12 01:39:05 PM PDT 24
Peak memory 248564 kb
Host smart-67c5d885-f2a1-4223-a440-88ef21bcb9d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40933
44695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.4093344695
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.896565968
Short name T672
Test name
Test status
Simulation time 7546289979 ps
CPU time 843.04 seconds
Started Mar 12 01:39:16 PM PDT 24
Finished Mar 12 01:53:25 PM PDT 24
Peak memory 273096 kb
Host smart-c7b8ae87-06ef-4beb-aba1-ddf2fabba673
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896565968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_han
dler_stress_all.896565968
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.4150259347
Short name T71
Test name
Test status
Simulation time 52155238694 ps
CPU time 2433.36 seconds
Started Mar 12 01:39:16 PM PDT 24
Finished Mar 12 02:19:55 PM PDT 24
Peak memory 305356 kb
Host smart-e28a95d7-3f58-4591-9cc2-f92b787fee02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150259347 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.4150259347
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.1610842041
Short name T212
Test name
Test status
Simulation time 425546378 ps
CPU time 3.74 seconds
Started Mar 12 01:38:35 PM PDT 24
Finished Mar 12 01:38:38 PM PDT 24
Peak memory 248644 kb
Host smart-a6e11efc-6266-429d-a874-b85a4c3822d3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1610842041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.1610842041
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.1318588897
Short name T525
Test name
Test status
Simulation time 30688494341 ps
CPU time 829.73 seconds
Started Mar 12 01:39:16 PM PDT 24
Finished Mar 12 01:53:12 PM PDT 24
Peak memory 273164 kb
Host smart-45a21215-f691-40e8-b0a1-af4dae3cc05e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318588897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.1318588897
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.3380178326
Short name T110
Test name
Test status
Simulation time 923742491 ps
CPU time 22.6 seconds
Started Mar 12 01:39:17 PM PDT 24
Finished Mar 12 01:39:44 PM PDT 24
Peak memory 248520 kb
Host smart-72f0b805-d149-44d5-8d28-e5a912399f98
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3380178326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.3380178326
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.1961879396
Short name T676
Test name
Test status
Simulation time 759619633 ps
CPU time 63.6 seconds
Started Mar 12 01:39:17 PM PDT 24
Finished Mar 12 01:40:26 PM PDT 24
Peak memory 256296 kb
Host smart-32f7fa3c-53a4-400d-9dfb-f3e49a36644a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19618
79396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.1961879396
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.2847027962
Short name T251
Test name
Test status
Simulation time 5493554080 ps
CPU time 54.06 seconds
Started Mar 12 01:39:17 PM PDT 24
Finished Mar 12 01:40:17 PM PDT 24
Peak memory 254384 kb
Host smart-b201fe17-2219-4eed-9014-bf220a422996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28470
27962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.2847027962
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.3603637260
Short name T411
Test name
Test status
Simulation time 16519761378 ps
CPU time 1277.7 seconds
Started Mar 12 01:39:18 PM PDT 24
Finished Mar 12 02:00:40 PM PDT 24
Peak memory 289100 kb
Host smart-92d92971-55be-4bad-b697-bbd190ef848d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603637260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.3603637260
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.653820154
Short name T642
Test name
Test status
Simulation time 42789429739 ps
CPU time 1451.21 seconds
Started Mar 12 01:39:18 PM PDT 24
Finished Mar 12 02:03:34 PM PDT 24
Peak memory 273168 kb
Host smart-2bfc710b-7b5b-4ac5-81cc-57c42a21b83c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653820154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.653820154
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.2442089016
Short name T87
Test name
Test status
Simulation time 22832940478 ps
CPU time 485.68 seconds
Started Mar 12 01:39:18 PM PDT 24
Finished Mar 12 01:47:28 PM PDT 24
Peak memory 247452 kb
Host smart-80f444d4-162c-4eb8-b525-5470ce3f09b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442089016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.2442089016
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.542548488
Short name T600
Test name
Test status
Simulation time 970336503 ps
CPU time 30.34 seconds
Started Mar 12 01:38:51 PM PDT 24
Finished Mar 12 01:39:22 PM PDT 24
Peak memory 248480 kb
Host smart-c9039e94-996b-47ca-b448-ee119305318a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54254
8488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.542548488
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.2251649021
Short name T526
Test name
Test status
Simulation time 1511224730 ps
CPU time 40.4 seconds
Started Mar 12 01:39:13 PM PDT 24
Finished Mar 12 01:39:55 PM PDT 24
Peak memory 248076 kb
Host smart-5ac423c5-90b4-453c-ac01-744ed3413a3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22516
49021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.2251649021
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.3879101435
Short name T671
Test name
Test status
Simulation time 672479984 ps
CPU time 41.18 seconds
Started Mar 12 01:38:21 PM PDT 24
Finished Mar 12 01:39:03 PM PDT 24
Peak memory 254660 kb
Host smart-a4fab8e6-bd62-49f0-8463-7053e3f9ecd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38791
01435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.3879101435
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.2018274295
Short name T617
Test name
Test status
Simulation time 3466753535 ps
CPU time 55.77 seconds
Started Mar 12 01:38:56 PM PDT 24
Finished Mar 12 01:39:51 PM PDT 24
Peak memory 248648 kb
Host smart-8e143e4b-257d-49ff-954b-aecd0ebc40c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20182
74295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2018274295
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.2714090789
Short name T256
Test name
Test status
Simulation time 258740124144 ps
CPU time 4172.73 seconds
Started Mar 12 01:38:54 PM PDT 24
Finished Mar 12 02:48:27 PM PDT 24
Peak memory 297912 kb
Host smart-97de190b-7ef8-4060-b2b5-c0320b39acc8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714090789 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.2714090789
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.1430985870
Short name T183
Test name
Test status
Simulation time 2216666712 ps
CPU time 28.93 seconds
Started Mar 12 01:39:15 PM PDT 24
Finished Mar 12 01:39:48 PM PDT 24
Peak memory 240384 kb
Host smart-a940e7da-d2d7-4fa1-9637-1bfb4e5c7c14
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1430985870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.1430985870
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.1546064598
Short name T664
Test name
Test status
Simulation time 5430190768 ps
CPU time 342.74 seconds
Started Mar 12 01:39:14 PM PDT 24
Finished Mar 12 01:44:57 PM PDT 24
Peak memory 256728 kb
Host smart-9a66e57a-37e4-4552-afd7-61e271f71843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15460
64598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.1546064598
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.1081844433
Short name T66
Test name
Test status
Simulation time 606337224 ps
CPU time 30.48 seconds
Started Mar 12 01:39:15 PM PDT 24
Finished Mar 12 01:39:49 PM PDT 24
Peak memory 254100 kb
Host smart-75b0ebeb-f006-47b7-aea5-b59be150f0db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10818
44433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.1081844433
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.807882498
Short name T331
Test name
Test status
Simulation time 29264521840 ps
CPU time 1200.73 seconds
Started Mar 12 01:39:15 PM PDT 24
Finished Mar 12 01:59:20 PM PDT 24
Peak memory 272848 kb
Host smart-3a2bfd0f-5d33-4ab3-a1d4-b65147922a8e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807882498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.807882498
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.1723947076
Short name T615
Test name
Test status
Simulation time 25216194177 ps
CPU time 1729.8 seconds
Started Mar 12 01:39:16 PM PDT 24
Finished Mar 12 02:08:11 PM PDT 24
Peak memory 282868 kb
Host smart-2667227e-16a4-4b8f-90c5-d7d7488df8cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723947076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.1723947076
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.821636341
Short name T303
Test name
Test status
Simulation time 6769216059 ps
CPU time 265.81 seconds
Started Mar 12 01:39:14 PM PDT 24
Finished Mar 12 01:43:42 PM PDT 24
Peak memory 246504 kb
Host smart-faa4c25a-97a0-4144-b571-b9c475185fd3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821636341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.821636341
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.3678229951
Short name T605
Test name
Test status
Simulation time 314521263 ps
CPU time 8.66 seconds
Started Mar 12 01:39:15 PM PDT 24
Finished Mar 12 01:39:28 PM PDT 24
Peak memory 253432 kb
Host smart-3ed2cb8f-efce-44e1-906f-46c178ffc410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36782
29951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.3678229951
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.4182891628
Short name T539
Test name
Test status
Simulation time 2029654175 ps
CPU time 25.53 seconds
Started Mar 12 01:39:16 PM PDT 24
Finished Mar 12 01:39:45 PM PDT 24
Peak memory 247992 kb
Host smart-90c8ddc5-9880-4fe4-a25b-d926d5ea79b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41828
91628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.4182891628
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.2818505480
Short name T470
Test name
Test status
Simulation time 2718021636 ps
CPU time 43.2 seconds
Started Mar 12 01:38:51 PM PDT 24
Finished Mar 12 01:39:34 PM PDT 24
Peak memory 248536 kb
Host smart-0196103d-ebf4-43d9-bd2e-d43fa6772cc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28185
05480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.2818505480
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.1262597027
Short name T444
Test name
Test status
Simulation time 793649728 ps
CPU time 31.59 seconds
Started Mar 12 01:39:14 PM PDT 24
Finished Mar 12 01:39:48 PM PDT 24
Peak memory 248540 kb
Host smart-34b87e40-2f89-45a6-a118-23610f5ca846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12625
97027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.1262597027
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.3796710813
Short name T198
Test name
Test status
Simulation time 101635056237 ps
CPU time 2842.59 seconds
Started Mar 12 01:39:32 PM PDT 24
Finished Mar 12 02:26:55 PM PDT 24
Peak memory 305888 kb
Host smart-a4fb1204-7134-4c05-94e8-7c39f0c8017f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796710813 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.3796710813
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.2132338643
Short name T214
Test name
Test status
Simulation time 54507804 ps
CPU time 4.05 seconds
Started Mar 12 01:39:25 PM PDT 24
Finished Mar 12 01:39:30 PM PDT 24
Peak memory 248696 kb
Host smart-ada6c8d6-93f6-4f0b-b9a1-59e2476f213c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2132338643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.2132338643
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.1398719152
Short name T628
Test name
Test status
Simulation time 48015660271 ps
CPU time 2690.28 seconds
Started Mar 12 01:39:24 PM PDT 24
Finished Mar 12 02:24:15 PM PDT 24
Peak memory 281356 kb
Host smart-e33401cc-e0b6-4aee-b189-49186ce0b6b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398719152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.1398719152
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.589242951
Short name T491
Test name
Test status
Simulation time 677162458 ps
CPU time 16.69 seconds
Started Mar 12 01:39:16 PM PDT 24
Finished Mar 12 01:39:36 PM PDT 24
Peak memory 240284 kb
Host smart-5b00f6d3-e63d-4101-b2af-94c0ea674970
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=589242951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.589242951
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.692348621
Short name T495
Test name
Test status
Simulation time 3156882607 ps
CPU time 152.66 seconds
Started Mar 12 01:39:25 PM PDT 24
Finished Mar 12 01:41:58 PM PDT 24
Peak memory 256256 kb
Host smart-dccff207-ae9b-4bd2-b89d-04187f401dd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69234
8621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.692348621
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.3324815570
Short name T253
Test name
Test status
Simulation time 807398715 ps
CPU time 47.33 seconds
Started Mar 12 01:39:26 PM PDT 24
Finished Mar 12 01:40:14 PM PDT 24
Peak memory 254960 kb
Host smart-a516a3d6-b374-49af-bb2e-f5d51f169c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33248
15570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3324815570
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.4170499361
Short name T325
Test name
Test status
Simulation time 228556046675 ps
CPU time 3194.05 seconds
Started Mar 12 01:39:17 PM PDT 24
Finished Mar 12 02:32:37 PM PDT 24
Peak memory 289024 kb
Host smart-f0c7cfa0-a784-45ff-b9fa-939263228463
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170499361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.4170499361
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.1941146632
Short name T273
Test name
Test status
Simulation time 26424795961 ps
CPU time 1179.7 seconds
Started Mar 12 01:39:28 PM PDT 24
Finished Mar 12 01:59:10 PM PDT 24
Peak memory 288852 kb
Host smart-87f852b2-3f86-46ce-9558-1138ba837409
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941146632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.1941146632
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.3787409891
Short name T314
Test name
Test status
Simulation time 13621907961 ps
CPU time 525.53 seconds
Started Mar 12 01:39:26 PM PDT 24
Finished Mar 12 01:48:12 PM PDT 24
Peak memory 247460 kb
Host smart-766b6a6a-bb4d-4ce2-b16a-95a75870a06d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787409891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.3787409891
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.1728242640
Short name T241
Test name
Test status
Simulation time 28006462 ps
CPU time 3.92 seconds
Started Mar 12 01:39:18 PM PDT 24
Finished Mar 12 01:39:26 PM PDT 24
Peak memory 240276 kb
Host smart-2cb65563-86a2-4bff-ac6e-ddd9b5fc1cae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17282
42640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.1728242640
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.3351681308
Short name T543
Test name
Test status
Simulation time 764745757 ps
CPU time 52.87 seconds
Started Mar 12 01:39:24 PM PDT 24
Finished Mar 12 01:40:17 PM PDT 24
Peak memory 246680 kb
Host smart-6d94425d-8e47-47d3-9fba-2c97ffdb2d78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33516
81308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.3351681308
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.4128129292
Short name T662
Test name
Test status
Simulation time 3302183078 ps
CPU time 26.94 seconds
Started Mar 12 01:39:23 PM PDT 24
Finished Mar 12 01:39:50 PM PDT 24
Peak memory 255660 kb
Host smart-cf5c202b-a88b-40d6-95bd-9d5b1bdd3848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41281
29292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.4128129292
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.1285160494
Short name T669
Test name
Test status
Simulation time 165689409 ps
CPU time 19.35 seconds
Started Mar 12 01:39:24 PM PDT 24
Finished Mar 12 01:39:43 PM PDT 24
Peak memory 248540 kb
Host smart-1dbc910e-72d7-4cca-a624-9e1a6d475f4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12851
60494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.1285160494
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.1299981749
Short name T208
Test name
Test status
Simulation time 115331258 ps
CPU time 3.34 seconds
Started Mar 12 01:39:26 PM PDT 24
Finished Mar 12 01:39:30 PM PDT 24
Peak memory 248704 kb
Host smart-44b03766-9e96-479a-a989-a84204efa7ec
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1299981749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.1299981749
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.3370703702
Short name T550
Test name
Test status
Simulation time 15990948897 ps
CPU time 843.88 seconds
Started Mar 12 01:39:28 PM PDT 24
Finished Mar 12 01:53:33 PM PDT 24
Peak memory 272048 kb
Host smart-0c36fb55-4615-4d80-b528-080fcd6882de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370703702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.3370703702
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.3717205696
Short name T517
Test name
Test status
Simulation time 409487322 ps
CPU time 8.64 seconds
Started Mar 12 01:39:24 PM PDT 24
Finished Mar 12 01:39:34 PM PDT 24
Peak memory 240308 kb
Host smart-11727de7-becf-4d39-b94c-a5d8299ac794
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3717205696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.3717205696
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.639036379
Short name T440
Test name
Test status
Simulation time 1991431056 ps
CPU time 168.19 seconds
Started Mar 12 01:39:23 PM PDT 24
Finished Mar 12 01:42:11 PM PDT 24
Peak memory 256204 kb
Host smart-5b802bbd-ef32-4b2b-a398-4ece402b6b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63903
6379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.639036379
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.3305707646
Short name T479
Test name
Test status
Simulation time 156492424 ps
CPU time 11.18 seconds
Started Mar 12 01:39:32 PM PDT 24
Finished Mar 12 01:39:44 PM PDT 24
Peak memory 252532 kb
Host smart-fee4d006-478e-493b-9281-9ae0fb6192b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33057
07646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.3305707646
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.188645323
Short name T647
Test name
Test status
Simulation time 23510847042 ps
CPU time 1736.32 seconds
Started Mar 12 01:39:25 PM PDT 24
Finished Mar 12 02:08:22 PM PDT 24
Peak memory 272832 kb
Host smart-adf394e2-d99c-4fc3-b3f5-9e1b257cb67b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188645323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.188645323
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.2045306895
Short name T14
Test name
Test status
Simulation time 92868364861 ps
CPU time 2644.77 seconds
Started Mar 12 01:39:33 PM PDT 24
Finished Mar 12 02:23:38 PM PDT 24
Peak memory 283164 kb
Host smart-0f3ea259-e8c6-42f3-ad85-1c2753f8eb83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045306895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.2045306895
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.862099874
Short name T225
Test name
Test status
Simulation time 42740453 ps
CPU time 4.16 seconds
Started Mar 12 01:39:21 PM PDT 24
Finished Mar 12 01:39:27 PM PDT 24
Peak memory 240332 kb
Host smart-8c5426f1-b90b-426e-a01e-6a809005b81b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86209
9874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.862099874
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.1188835216
Short name T272
Test name
Test status
Simulation time 296343012 ps
CPU time 24.74 seconds
Started Mar 12 01:39:28 PM PDT 24
Finished Mar 12 01:39:54 PM PDT 24
Peak memory 247136 kb
Host smart-13614c12-bbd4-43c3-8905-a41204cc888a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11888
35216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.1188835216
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.2222276326
Short name T400
Test name
Test status
Simulation time 187269868 ps
CPU time 20.16 seconds
Started Mar 12 01:39:21 PM PDT 24
Finished Mar 12 01:39:43 PM PDT 24
Peak memory 248552 kb
Host smart-ebec8ae3-5435-4a83-86c1-8f3cc55d684b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22222
76326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.2222276326
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.4131770847
Short name T259
Test name
Test status
Simulation time 13002129591 ps
CPU time 422.94 seconds
Started Mar 12 01:39:24 PM PDT 24
Finished Mar 12 01:46:27 PM PDT 24
Peak memory 256772 kb
Host smart-555caf5f-77ec-4c2d-af60-25e004cc4f1c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131770847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.4131770847
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.3101361857
Short name T77
Test name
Test status
Simulation time 24414493528 ps
CPU time 1568.11 seconds
Started Mar 12 01:39:25 PM PDT 24
Finished Mar 12 02:05:34 PM PDT 24
Peak memory 288644 kb
Host smart-de81d489-7706-4832-a37c-2f3752c5d8ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101361857 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.3101361857
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.90082086
Short name T209
Test name
Test status
Simulation time 14584903 ps
CPU time 3.03 seconds
Started Mar 12 01:39:25 PM PDT 24
Finished Mar 12 01:39:29 PM PDT 24
Peak memory 248692 kb
Host smart-32b777e0-d540-4506-bc7c-aed6243cf7b7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=90082086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.90082086
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.3060126808
Short name T30
Test name
Test status
Simulation time 25374178251 ps
CPU time 1570.6 seconds
Started Mar 12 01:39:20 PM PDT 24
Finished Mar 12 02:05:34 PM PDT 24
Peak memory 273136 kb
Host smart-06454052-6379-48e5-a386-ea85bcec61e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060126808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.3060126808
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.1300922085
Short name T476
Test name
Test status
Simulation time 1212110641 ps
CPU time 15.81 seconds
Started Mar 12 01:39:23 PM PDT 24
Finished Mar 12 01:39:39 PM PDT 24
Peak memory 248488 kb
Host smart-b4c860a7-3a47-49f7-a786-8f485787913c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1300922085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1300922085
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.1918174053
Short name T690
Test name
Test status
Simulation time 413385720 ps
CPU time 29.96 seconds
Started Mar 12 01:39:32 PM PDT 24
Finished Mar 12 01:40:03 PM PDT 24
Peak memory 248100 kb
Host smart-5b31bbac-94ae-4ad6-b189-5dfe50c3e878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19181
74053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.1918174053
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.1545615222
Short name T583
Test name
Test status
Simulation time 1128509553 ps
CPU time 24.56 seconds
Started Mar 12 01:39:21 PM PDT 24
Finished Mar 12 01:39:47 PM PDT 24
Peak memory 254840 kb
Host smart-d0bca943-c0f1-4c61-8d6a-a3182a054152
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15456
15222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.1545615222
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.3333292909
Short name T5
Test name
Test status
Simulation time 159986777384 ps
CPU time 2645.78 seconds
Started Mar 12 01:39:25 PM PDT 24
Finished Mar 12 02:23:32 PM PDT 24
Peak memory 288940 kb
Host smart-8579c5d9-9ec8-48d1-8bc6-b0694134590d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333292909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.3333292909
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.2777854749
Short name T437
Test name
Test status
Simulation time 39302800645 ps
CPU time 2330.69 seconds
Started Mar 12 01:39:25 PM PDT 24
Finished Mar 12 02:18:16 PM PDT 24
Peak memory 273160 kb
Host smart-b35e969d-542c-48d1-abd9-3cedfef11048
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777854749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.2777854749
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.2467152658
Short name T632
Test name
Test status
Simulation time 28911864345 ps
CPU time 558.34 seconds
Started Mar 12 01:39:26 PM PDT 24
Finished Mar 12 01:48:45 PM PDT 24
Peak memory 247456 kb
Host smart-b2ef51c1-9024-4ed8-b2d0-f86f39dc00b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467152658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.2467152658
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.4109282475
Short name T385
Test name
Test status
Simulation time 1215352520 ps
CPU time 75.77 seconds
Started Mar 12 01:39:28 PM PDT 24
Finished Mar 12 01:40:45 PM PDT 24
Peak memory 248548 kb
Host smart-3838f1e4-067c-480a-8dd7-4808d876cfdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41092
82475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.4109282475
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.496036492
Short name T51
Test name
Test status
Simulation time 397225097 ps
CPU time 41.35 seconds
Started Mar 12 01:39:23 PM PDT 24
Finished Mar 12 01:40:05 PM PDT 24
Peak memory 256000 kb
Host smart-d0786388-bb0c-4ece-b9d8-8e97578e2768
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49603
6492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.496036492
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.2012051740
Short name T524
Test name
Test status
Simulation time 400045243 ps
CPU time 19.15 seconds
Started Mar 12 01:39:28 PM PDT 24
Finished Mar 12 01:39:48 PM PDT 24
Peak memory 254444 kb
Host smart-d84bdddd-d8e2-4ad5-af21-d3e1f9c059af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20120
51740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.2012051740
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.1414967428
Short name T260
Test name
Test status
Simulation time 48532409148 ps
CPU time 2628.25 seconds
Started Mar 12 01:39:26 PM PDT 24
Finished Mar 12 02:23:16 PM PDT 24
Peak memory 287240 kb
Host smart-f2da3928-6b15-4cb9-b3f3-eaa462ac5560
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414967428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.1414967428
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.3355779243
Short name T234
Test name
Test status
Simulation time 129530245752 ps
CPU time 4599.78 seconds
Started Mar 12 01:39:25 PM PDT 24
Finished Mar 12 02:56:06 PM PDT 24
Peak memory 315640 kb
Host smart-dedc6e5f-bc5d-4215-8632-be4101b70a85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355779243 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.3355779243
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.3575100429
Short name T201
Test name
Test status
Simulation time 32495210 ps
CPU time 2.32 seconds
Started Mar 12 01:39:37 PM PDT 24
Finished Mar 12 01:39:39 PM PDT 24
Peak memory 248540 kb
Host smart-b91629a1-b4fb-4d85-a322-203a8f88d3d0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3575100429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.3575100429
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.1577925244
Short name T488
Test name
Test status
Simulation time 35018537255 ps
CPU time 825.1 seconds
Started Mar 12 01:39:31 PM PDT 24
Finished Mar 12 01:53:18 PM PDT 24
Peak memory 267000 kb
Host smart-2895f9a8-920f-4431-bf36-e4a1cbc705fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577925244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.1577925244
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.1157963371
Short name T668
Test name
Test status
Simulation time 271906556 ps
CPU time 14.78 seconds
Started Mar 12 01:39:37 PM PDT 24
Finished Mar 12 01:39:52 PM PDT 24
Peak memory 248476 kb
Host smart-c334fabf-7c43-4167-b6b6-b2b57c3baabf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1157963371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1157963371
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.680591774
Short name T687
Test name
Test status
Simulation time 13733124637 ps
CPU time 68.3 seconds
Started Mar 12 01:39:30 PM PDT 24
Finished Mar 12 01:40:41 PM PDT 24
Peak memory 255876 kb
Host smart-9e8813a4-aa8e-4346-88d2-92492140c04b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68059
1774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.680591774
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.3606909316
Short name T377
Test name
Test status
Simulation time 105947398 ps
CPU time 14.59 seconds
Started Mar 12 01:39:28 PM PDT 24
Finished Mar 12 01:39:43 PM PDT 24
Peak memory 247912 kb
Host smart-da3faab3-946f-411b-bd48-06e98575f891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36069
09316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.3606909316
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.1880863901
Short name T285
Test name
Test status
Simulation time 97123360797 ps
CPU time 1819.77 seconds
Started Mar 12 01:39:37 PM PDT 24
Finished Mar 12 02:09:57 PM PDT 24
Peak memory 272744 kb
Host smart-2ef9855d-ff73-4400-b69d-f41a6e0afec9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880863901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.1880863901
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.441967220
Short name T88
Test name
Test status
Simulation time 26389878100 ps
CPU time 1239.79 seconds
Started Mar 12 01:39:39 PM PDT 24
Finished Mar 12 02:00:19 PM PDT 24
Peak memory 286108 kb
Host smart-ceac27e5-55de-4e46-a1ea-6be540f09866
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441967220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.441967220
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.2288194319
Short name T556
Test name
Test status
Simulation time 7809646938 ps
CPU time 337.28 seconds
Started Mar 12 01:39:26 PM PDT 24
Finished Mar 12 01:45:04 PM PDT 24
Peak memory 254652 kb
Host smart-d7681bd9-d306-4312-8eff-7aaa0fb8efe4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288194319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.2288194319
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.3364104124
Short name T645
Test name
Test status
Simulation time 1349256003 ps
CPU time 32.71 seconds
Started Mar 12 01:39:27 PM PDT 24
Finished Mar 12 01:40:00 PM PDT 24
Peak memory 254716 kb
Host smart-7b647d4c-367d-4e0b-8e4f-0fd82bb5072c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33641
04124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.3364104124
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.2140236638
Short name T228
Test name
Test status
Simulation time 868630556 ps
CPU time 33.2 seconds
Started Mar 12 01:39:28 PM PDT 24
Finished Mar 12 01:40:02 PM PDT 24
Peak memory 247892 kb
Host smart-64582569-bee3-40dd-beb4-2bb3d5ebe788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21402
36638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.2140236638
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.1577257506
Short name T562
Test name
Test status
Simulation time 8085088299 ps
CPU time 63.04 seconds
Started Mar 12 01:39:30 PM PDT 24
Finished Mar 12 01:40:33 PM PDT 24
Peak memory 248576 kb
Host smart-841b7ee2-0c95-40a7-b637-c85d0c3e0446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15772
57506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.1577257506
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.1763753779
Short name T64
Test name
Test status
Simulation time 3322660521 ps
CPU time 58.07 seconds
Started Mar 12 01:39:28 PM PDT 24
Finished Mar 12 01:40:26 PM PDT 24
Peak memory 248588 kb
Host smart-e7d808a6-bb89-45aa-925d-6d86711416d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17637
53779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.1763753779
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.1718857054
Short name T678
Test name
Test status
Simulation time 328023603 ps
CPU time 43.28 seconds
Started Mar 12 01:39:38 PM PDT 24
Finished Mar 12 01:40:22 PM PDT 24
Peak memory 255020 kb
Host smart-2a988803-d8c3-45fd-ac37-ee6b88838c19
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718857054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.1718857054
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.3558971897
Short name T518
Test name
Test status
Simulation time 11789508084 ps
CPU time 1436.8 seconds
Started Mar 12 01:39:36 PM PDT 24
Finished Mar 12 02:03:34 PM PDT 24
Peak memory 289156 kb
Host smart-af6c5a0a-e4a3-4342-b079-d4eb1eeadfb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558971897 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.3558971897
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.3156553681
Short name T206
Test name
Test status
Simulation time 140429126 ps
CPU time 3.65 seconds
Started Mar 12 01:39:55 PM PDT 24
Finished Mar 12 01:40:00 PM PDT 24
Peak memory 248660 kb
Host smart-6bcfbab7-5b09-4dbc-962d-1ac05baaf119
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3156553681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.3156553681
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.2002829922
Short name T497
Test name
Test status
Simulation time 8179524069 ps
CPU time 809.56 seconds
Started Mar 12 01:39:47 PM PDT 24
Finished Mar 12 01:53:18 PM PDT 24
Peak memory 272784 kb
Host smart-a1f8bc39-167f-45db-ad72-9c9866fd3267
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002829922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.2002829922
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.3921903625
Short name T593
Test name
Test status
Simulation time 1548663481 ps
CPU time 7.62 seconds
Started Mar 12 01:39:55 PM PDT 24
Finished Mar 12 01:40:04 PM PDT 24
Peak memory 240348 kb
Host smart-a85e40b5-ddc8-44f9-83b9-221f1f510f29
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3921903625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.3921903625
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.184223278
Short name T685
Test name
Test status
Simulation time 114201695 ps
CPU time 10.75 seconds
Started Mar 12 01:39:44 PM PDT 24
Finished Mar 12 01:39:55 PM PDT 24
Peak memory 248532 kb
Host smart-eb27e541-9adb-4e9c-a70c-658c141ef64f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18422
3278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.184223278
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.1242127370
Short name T397
Test name
Test status
Simulation time 200706223 ps
CPU time 7.67 seconds
Started Mar 12 01:39:47 PM PDT 24
Finished Mar 12 01:39:56 PM PDT 24
Peak memory 250248 kb
Host smart-da12d1eb-7e3e-41d8-bdfc-bbe2d3c3fc87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12421
27370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.1242127370
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.2948468067
Short name T313
Test name
Test status
Simulation time 26496174351 ps
CPU time 1006.77 seconds
Started Mar 12 01:39:46 PM PDT 24
Finished Mar 12 01:56:35 PM PDT 24
Peak memory 272716 kb
Host smart-cb531269-8d43-4bf8-92a9-b26f576054f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948468067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.2948468067
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.3722762321
Short name T634
Test name
Test status
Simulation time 36625018217 ps
CPU time 1738.58 seconds
Started Mar 12 01:39:54 PM PDT 24
Finished Mar 12 02:08:54 PM PDT 24
Peak memory 288548 kb
Host smart-64a5f3a1-e26f-4bac-8ec6-da8f1008a557
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722762321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.3722762321
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.1599205537
Short name T585
Test name
Test status
Simulation time 71252237 ps
CPU time 7.68 seconds
Started Mar 12 01:39:47 PM PDT 24
Finished Mar 12 01:39:56 PM PDT 24
Peak memory 252196 kb
Host smart-0fd98cb6-7522-4310-8ec9-d5ece6e48525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15992
05537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.1599205537
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.3986381543
Short name T644
Test name
Test status
Simulation time 1206490121 ps
CPU time 19.58 seconds
Started Mar 12 01:39:47 PM PDT 24
Finished Mar 12 01:40:07 PM PDT 24
Peak memory 254732 kb
Host smart-6815fae1-7d00-4652-9b3f-836bcebccb02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39863
81543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.3986381543
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.561061221
Short name T67
Test name
Test status
Simulation time 166243068 ps
CPU time 6.01 seconds
Started Mar 12 01:39:48 PM PDT 24
Finished Mar 12 01:39:54 PM PDT 24
Peak memory 248520 kb
Host smart-f41ded87-80ba-455b-91c8-ed8a6983d5f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56106
1221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.561061221
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.1220585615
Short name T414
Test name
Test status
Simulation time 376312415 ps
CPU time 31.94 seconds
Started Mar 12 01:39:53 PM PDT 24
Finished Mar 12 01:40:25 PM PDT 24
Peak memory 248540 kb
Host smart-37042bb7-3cf8-485d-8d2a-f112ae44c9c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12205
85615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.1220585615
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.618158308
Short name T216
Test name
Test status
Simulation time 70575792 ps
CPU time 3.59 seconds
Started Mar 12 01:40:14 PM PDT 24
Finished Mar 12 01:40:18 PM PDT 24
Peak memory 248652 kb
Host smart-8b7a58b6-df20-4b18-80b4-f27b329861e3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=618158308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.618158308
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.324088067
Short name T364
Test name
Test status
Simulation time 183617362 ps
CPU time 10.97 seconds
Started Mar 12 01:40:04 PM PDT 24
Finished Mar 12 01:40:15 PM PDT 24
Peak memory 248520 kb
Host smart-a51ae71f-c615-4786-ba8d-1d0a56ad884c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=324088067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.324088067
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.1766884054
Short name T492
Test name
Test status
Simulation time 3871365844 ps
CPU time 241.25 seconds
Started Mar 12 01:39:54 PM PDT 24
Finished Mar 12 01:43:57 PM PDT 24
Peak memory 256288 kb
Host smart-55e5b847-b619-4432-9bda-984d97c27ee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17668
84054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.1766884054
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.1155048908
Short name T575
Test name
Test status
Simulation time 643668976 ps
CPU time 9.26 seconds
Started Mar 12 01:39:54 PM PDT 24
Finished Mar 12 01:40:04 PM PDT 24
Peak memory 249424 kb
Host smart-628f7c43-08e5-4d8f-bb9e-768a8f8539bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11550
48908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.1155048908
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.3849994800
Short name T475
Test name
Test status
Simulation time 147417860306 ps
CPU time 2137.96 seconds
Started Mar 12 01:40:12 PM PDT 24
Finished Mar 12 02:15:51 PM PDT 24
Peak memory 281844 kb
Host smart-3115c590-3d8f-4d03-98c1-f52148c719f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849994800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.3849994800
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.3820223888
Short name T28
Test name
Test status
Simulation time 175949801 ps
CPU time 16.93 seconds
Started Mar 12 01:39:55 PM PDT 24
Finished Mar 12 01:40:13 PM PDT 24
Peak memory 248512 kb
Host smart-affc9b3a-671a-4034-8f23-7d10868c053c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38202
23888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.3820223888
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.2370309829
Short name T27
Test name
Test status
Simulation time 962805115 ps
CPU time 29.38 seconds
Started Mar 12 01:39:54 PM PDT 24
Finished Mar 12 01:40:25 PM PDT 24
Peak memory 254888 kb
Host smart-566b2d39-d24b-4a83-9355-c12bbfdf0ab7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23703
09829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.2370309829
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.525951208
Short name T263
Test name
Test status
Simulation time 1027772538 ps
CPU time 69.85 seconds
Started Mar 12 01:39:55 PM PDT 24
Finished Mar 12 01:41:06 PM PDT 24
Peak memory 254728 kb
Host smart-c227d721-0222-40f3-8bd3-f111d8169b3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52595
1208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.525951208
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.1163821002
Short name T587
Test name
Test status
Simulation time 4884945693 ps
CPU time 42.3 seconds
Started Mar 12 01:39:54 PM PDT 24
Finished Mar 12 01:40:37 PM PDT 24
Peak memory 248596 kb
Host smart-2db5ed9f-1f61-4fd3-93b6-c1c4bae44f1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11638
21002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.1163821002
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.4206551780
Short name T269
Test name
Test status
Simulation time 115752425134 ps
CPU time 3274.72 seconds
Started Mar 12 01:40:04 PM PDT 24
Finished Mar 12 02:34:39 PM PDT 24
Peak memory 289100 kb
Host smart-7bf78ed3-e8dc-4516-94aa-12cf07dc36a6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206551780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.4206551780
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.4043209749
Short name T217
Test name
Test status
Simulation time 38548705 ps
CPU time 3.49 seconds
Started Mar 12 01:39:15 PM PDT 24
Finished Mar 12 01:39:23 PM PDT 24
Peak memory 248692 kb
Host smart-a6af71fc-76c6-4e17-a637-20d08cbb649a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4043209749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.4043209749
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.953699412
Short name T434
Test name
Test status
Simulation time 33673269644 ps
CPU time 527.09 seconds
Started Mar 12 01:39:15 PM PDT 24
Finished Mar 12 01:48:06 PM PDT 24
Peak memory 271108 kb
Host smart-86321da2-fdff-45ef-bb33-3e00ebe54721
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953699412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.953699412
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.626935577
Short name T378
Test name
Test status
Simulation time 913141603 ps
CPU time 12.88 seconds
Started Mar 12 01:38:53 PM PDT 24
Finished Mar 12 01:39:07 PM PDT 24
Peak memory 240288 kb
Host smart-03945369-c8a7-4a39-8a54-6eee6c823feb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=626935577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.626935577
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.1056564965
Short name T367
Test name
Test status
Simulation time 4852403603 ps
CPU time 94.44 seconds
Started Mar 12 01:39:13 PM PDT 24
Finished Mar 12 01:40:47 PM PDT 24
Peak memory 255888 kb
Host smart-906442f2-2d3c-46da-ac6a-a3304ad20886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10565
64965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.1056564965
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.1338669247
Short name T405
Test name
Test status
Simulation time 1036041453 ps
CPU time 35.79 seconds
Started Mar 12 01:38:30 PM PDT 24
Finished Mar 12 01:39:06 PM PDT 24
Peak memory 254756 kb
Host smart-76a29c26-dfd2-47e4-bb93-bb22906bc57d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13386
69247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.1338669247
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.3394134483
Short name T329
Test name
Test status
Simulation time 169941293605 ps
CPU time 2491.3 seconds
Started Mar 12 01:39:04 PM PDT 24
Finished Mar 12 02:20:35 PM PDT 24
Peak memory 285864 kb
Host smart-700a16f0-69fd-456b-b374-cefbe9946984
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394134483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.3394134483
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.2911464530
Short name T610
Test name
Test status
Simulation time 29847688711 ps
CPU time 976.13 seconds
Started Mar 12 01:39:12 PM PDT 24
Finished Mar 12 01:55:28 PM PDT 24
Peak memory 289132 kb
Host smart-63a2265d-ddb7-475c-a9bf-815aeaf72c4b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911464530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.2911464530
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.2822346590
Short name T304
Test name
Test status
Simulation time 3238447176 ps
CPU time 136.13 seconds
Started Mar 12 01:39:12 PM PDT 24
Finished Mar 12 01:41:28 PM PDT 24
Peak memory 248472 kb
Host smart-ff5073ad-1b1d-4626-8186-fdc3616750f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822346590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.2822346590
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.3432285563
Short name T366
Test name
Test status
Simulation time 237392377 ps
CPU time 24.9 seconds
Started Mar 12 01:39:08 PM PDT 24
Finished Mar 12 01:39:33 PM PDT 24
Peak memory 248496 kb
Host smart-790096d9-e161-4a5b-a8e1-c3fd3b6f683e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34322
85563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.3432285563
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.1527768816
Short name T446
Test name
Test status
Simulation time 4966505932 ps
CPU time 81.28 seconds
Started Mar 12 01:39:07 PM PDT 24
Finished Mar 12 01:40:29 PM PDT 24
Peak memory 254976 kb
Host smart-c880f7ac-e068-4d31-821e-8870eef5593f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15277
68816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.1527768816
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.115714794
Short name T648
Test name
Test status
Simulation time 118710103 ps
CPU time 8.12 seconds
Started Mar 12 01:39:07 PM PDT 24
Finished Mar 12 01:39:15 PM PDT 24
Peak memory 249972 kb
Host smart-86b65d43-f4b7-4648-8367-98b41879688e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11571
4794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.115714794
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.2153053382
Short name T530
Test name
Test status
Simulation time 646302486 ps
CPU time 25.24 seconds
Started Mar 12 01:39:09 PM PDT 24
Finished Mar 12 01:39:35 PM PDT 24
Peak memory 248628 kb
Host smart-bf1ac265-e4bb-4767-b183-240f95973d9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21530
53382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.2153053382
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.2912853260
Short name T394
Test name
Test status
Simulation time 20125293954 ps
CPU time 226.74 seconds
Started Mar 12 01:38:43 PM PDT 24
Finished Mar 12 01:42:30 PM PDT 24
Peak memory 256760 kb
Host smart-edd0a8f8-e2c1-43f5-900f-acc8c6f78e9d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912853260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.2912853260
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.3773029560
Short name T101
Test name
Test status
Simulation time 38726086386 ps
CPU time 2664 seconds
Started Mar 12 01:40:14 PM PDT 24
Finished Mar 12 02:24:39 PM PDT 24
Peak memory 288696 kb
Host smart-2d46d20e-7a06-4e6b-adef-32bfb9e5acfe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773029560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.3773029560
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.3367670859
Short name T500
Test name
Test status
Simulation time 7037123324 ps
CPU time 118.44 seconds
Started Mar 12 01:40:04 PM PDT 24
Finished Mar 12 01:42:03 PM PDT 24
Peak memory 256724 kb
Host smart-110023ad-b642-4231-9987-960012c508c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33676
70859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.3367670859
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.726454349
Short name T599
Test name
Test status
Simulation time 580077439 ps
CPU time 26.77 seconds
Started Mar 12 01:40:14 PM PDT 24
Finished Mar 12 01:40:40 PM PDT 24
Peak memory 254828 kb
Host smart-15dd7f34-f31f-4b4c-94f0-c099068563bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72645
4349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.726454349
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.3354632426
Short name T184
Test name
Test status
Simulation time 54840762032 ps
CPU time 1573.75 seconds
Started Mar 12 01:40:14 PM PDT 24
Finished Mar 12 02:06:28 PM PDT 24
Peak memory 270952 kb
Host smart-0a220979-9f5d-4cac-a3d4-5f60a60e433d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354632426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.3354632426
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.1698151553
Short name T623
Test name
Test status
Simulation time 56546697053 ps
CPU time 1610.29 seconds
Started Mar 12 01:40:05 PM PDT 24
Finished Mar 12 02:06:56 PM PDT 24
Peak memory 272160 kb
Host smart-294eba0e-4e6f-4bab-8a6b-76cb028f09c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698151553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.1698151553
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.39723391
Short name T528
Test name
Test status
Simulation time 26810114119 ps
CPU time 279.93 seconds
Started Mar 12 01:40:02 PM PDT 24
Finished Mar 12 01:44:43 PM PDT 24
Peak memory 247360 kb
Host smart-fc5f23e6-fd1e-4994-a5d0-9f546d7199e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39723391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.39723391
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.139227326
Short name T387
Test name
Test status
Simulation time 325471602 ps
CPU time 13.36 seconds
Started Mar 12 01:40:12 PM PDT 24
Finished Mar 12 01:40:26 PM PDT 24
Peak memory 248468 kb
Host smart-2db62c6a-2f73-4359-b39d-3d128bb75db0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13922
7326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.139227326
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.1836906177
Short name T443
Test name
Test status
Simulation time 756871504 ps
CPU time 23.55 seconds
Started Mar 12 01:40:02 PM PDT 24
Finished Mar 12 01:40:27 PM PDT 24
Peak memory 246840 kb
Host smart-f0b553b0-b25d-411c-83f9-963f79bf19de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18369
06177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.1836906177
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.3692747505
Short name T254
Test name
Test status
Simulation time 7276590555 ps
CPU time 60.04 seconds
Started Mar 12 01:40:12 PM PDT 24
Finished Mar 12 01:41:12 PM PDT 24
Peak memory 248596 kb
Host smart-188cf7bb-238d-4917-b92e-509199f9a8ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36927
47505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.3692747505
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.2428345614
Short name T494
Test name
Test status
Simulation time 429237867 ps
CPU time 15.57 seconds
Started Mar 12 01:40:04 PM PDT 24
Finished Mar 12 01:40:20 PM PDT 24
Peak memory 248548 kb
Host smart-d49355f8-2fd9-4e84-8e39-9a6d666d0509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24283
45614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.2428345614
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.102050671
Short name T441
Test name
Test status
Simulation time 62363667727 ps
CPU time 2994.13 seconds
Started Mar 12 01:40:12 PM PDT 24
Finished Mar 12 02:30:06 PM PDT 24
Peak memory 287804 kb
Host smart-e009f32d-44fd-4698-9ebe-bd7235cd919e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102050671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.102050671
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.2370863339
Short name T448
Test name
Test status
Simulation time 2409865251 ps
CPU time 170.68 seconds
Started Mar 12 01:40:14 PM PDT 24
Finished Mar 12 01:43:05 PM PDT 24
Peak memory 255860 kb
Host smart-a55790b8-1e01-455e-93e6-03790473b003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23708
63339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.2370863339
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.1539977503
Short name T477
Test name
Test status
Simulation time 467897170 ps
CPU time 35.36 seconds
Started Mar 12 01:40:12 PM PDT 24
Finished Mar 12 01:40:47 PM PDT 24
Peak memory 254932 kb
Host smart-9654c105-8565-4408-8443-f9c1da5ec42e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15399
77503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.1539977503
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.3454003351
Short name T549
Test name
Test status
Simulation time 31424752144 ps
CPU time 1784.6 seconds
Started Mar 12 01:40:06 PM PDT 24
Finished Mar 12 02:09:51 PM PDT 24
Peak memory 272816 kb
Host smart-b5ebc607-1934-42a8-9966-d8cd9a1f605d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454003351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.3454003351
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.2026072293
Short name T291
Test name
Test status
Simulation time 35562124016 ps
CPU time 183.86 seconds
Started Mar 12 01:40:05 PM PDT 24
Finished Mar 12 01:43:09 PM PDT 24
Peak memory 247224 kb
Host smart-75df4ca7-5bf4-49a1-9194-e40526b90c50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026072293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.2026072293
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.2196212300
Short name T614
Test name
Test status
Simulation time 792445574 ps
CPU time 63.85 seconds
Started Mar 12 01:40:02 PM PDT 24
Finished Mar 12 01:41:07 PM PDT 24
Peak memory 248476 kb
Host smart-739a316a-8e2e-4b74-a96f-3ea3c8d18d7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21962
12300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.2196212300
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.34863721
Short name T541
Test name
Test status
Simulation time 3847661250 ps
CPU time 59.78 seconds
Started Mar 12 01:40:12 PM PDT 24
Finished Mar 12 01:41:12 PM PDT 24
Peak memory 254968 kb
Host smart-27c8a461-42f7-4b27-9561-5d4cdfc4aba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34863
721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.34863721
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.3924070575
Short name T355
Test name
Test status
Simulation time 1852409813 ps
CPU time 59.98 seconds
Started Mar 12 01:40:02 PM PDT 24
Finished Mar 12 01:41:03 PM PDT 24
Peak memory 248576 kb
Host smart-3359267b-9aaf-43e8-91ee-82f3c72d50c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39240
70575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.3924070575
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.4278338800
Short name T258
Test name
Test status
Simulation time 172489736300 ps
CPU time 3051.72 seconds
Started Mar 12 01:40:08 PM PDT 24
Finished Mar 12 02:31:01 PM PDT 24
Peak memory 288048 kb
Host smart-504ad391-2be3-46ea-bacb-7ae5c94edc71
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278338800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.4278338800
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.3645490115
Short name T65
Test name
Test status
Simulation time 2062697025 ps
CPU time 118.81 seconds
Started Mar 12 01:40:10 PM PDT 24
Finished Mar 12 01:42:09 PM PDT 24
Peak memory 256172 kb
Host smart-376b1145-2408-4739-ab87-e6158e5f9efc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36454
90115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.3645490115
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.3692927671
Short name T409
Test name
Test status
Simulation time 358198188 ps
CPU time 30.91 seconds
Started Mar 12 01:40:12 PM PDT 24
Finished Mar 12 01:40:43 PM PDT 24
Peak memory 254932 kb
Host smart-eb2979d1-d635-46f4-961f-2919ec1acd41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36929
27671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.3692927671
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.713919770
Short name T328
Test name
Test status
Simulation time 120977080754 ps
CPU time 2111.32 seconds
Started Mar 12 01:40:11 PM PDT 24
Finished Mar 12 02:15:23 PM PDT 24
Peak memory 272464 kb
Host smart-2d83b1e4-7fe2-4c4f-8bf6-89de0675e03f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713919770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.713919770
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.2469753623
Short name T278
Test name
Test status
Simulation time 21538874917 ps
CPU time 1373.82 seconds
Started Mar 12 01:40:11 PM PDT 24
Finished Mar 12 02:03:06 PM PDT 24
Peak memory 273160 kb
Host smart-c1dff12c-61ba-4942-b437-e3ef0d740f79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469753623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.2469753623
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.3556341253
Short name T512
Test name
Test status
Simulation time 34037073440 ps
CPU time 508.74 seconds
Started Mar 12 01:40:02 PM PDT 24
Finished Mar 12 01:48:32 PM PDT 24
Peak memory 247228 kb
Host smart-6d7aac25-0b8c-4569-9230-bd0528bb95b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556341253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.3556341253
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.3784843680
Short name T379
Test name
Test status
Simulation time 238121096 ps
CPU time 4.3 seconds
Started Mar 12 01:40:06 PM PDT 24
Finished Mar 12 01:40:10 PM PDT 24
Peak memory 240280 kb
Host smart-3e42f5c9-e660-4e4a-8755-a816b5cce777
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37848
43680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.3784843680
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.4014182354
Short name T68
Test name
Test status
Simulation time 2201109360 ps
CPU time 47.29 seconds
Started Mar 12 01:40:08 PM PDT 24
Finished Mar 12 01:40:55 PM PDT 24
Peak memory 247252 kb
Host smart-8ce421db-ea32-4886-8d95-d8ace90fb56c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40141
82354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.4014182354
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.1086435653
Short name T633
Test name
Test status
Simulation time 46416589 ps
CPU time 4.39 seconds
Started Mar 12 01:40:13 PM PDT 24
Finished Mar 12 01:40:18 PM PDT 24
Peak memory 238552 kb
Host smart-e931d7c7-d153-4f3f-a631-b563c5f61b20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10864
35653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.1086435653
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.218296846
Short name T631
Test name
Test status
Simulation time 1298791632 ps
CPU time 36.78 seconds
Started Mar 12 01:40:13 PM PDT 24
Finished Mar 12 01:40:50 PM PDT 24
Peak memory 248468 kb
Host smart-91d61fd3-32bf-40e7-95d0-50424d0a3ba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21829
6846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.218296846
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.1851392786
Short name T455
Test name
Test status
Simulation time 37274871893 ps
CPU time 2256.16 seconds
Started Mar 12 01:40:03 PM PDT 24
Finished Mar 12 02:17:40 PM PDT 24
Peak memory 289160 kb
Host smart-9e478845-0217-47c4-83cd-e5aeae9ee1ee
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851392786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.1851392786
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.2620874085
Short name T99
Test name
Test status
Simulation time 19488468257 ps
CPU time 1050.17 seconds
Started Mar 12 01:40:07 PM PDT 24
Finished Mar 12 01:57:38 PM PDT 24
Peak memory 283188 kb
Host smart-7c18bd7a-7eae-4256-895b-9df9d5cb0fa9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620874085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2620874085
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.3798856304
Short name T243
Test name
Test status
Simulation time 5475594507 ps
CPU time 173.83 seconds
Started Mar 12 01:40:02 PM PDT 24
Finished Mar 12 01:42:57 PM PDT 24
Peak memory 256072 kb
Host smart-9df4bf15-a5b6-4458-9e1a-9bded923540e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37988
56304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.3798856304
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.2250343363
Short name T252
Test name
Test status
Simulation time 241856588 ps
CPU time 31.82 seconds
Started Mar 12 01:40:12 PM PDT 24
Finished Mar 12 01:40:44 PM PDT 24
Peak memory 254988 kb
Host smart-a9323c9e-0bd3-42b3-8f8c-2616db62d21c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22503
43363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.2250343363
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.1588260781
Short name T310
Test name
Test status
Simulation time 58825230703 ps
CPU time 1458.49 seconds
Started Mar 12 01:40:14 PM PDT 24
Finished Mar 12 02:04:33 PM PDT 24
Peak memory 272972 kb
Host smart-7ff12e1c-8ad0-4940-b356-08c1012d5d83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588260781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.1588260781
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.1910052814
Short name T332
Test name
Test status
Simulation time 108578087827 ps
CPU time 3194.52 seconds
Started Mar 12 01:40:13 PM PDT 24
Finished Mar 12 02:33:28 PM PDT 24
Peak memory 288400 kb
Host smart-4b6622d3-e42a-472c-8543-002ca3dc4246
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910052814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.1910052814
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.3845063018
Short name T227
Test name
Test status
Simulation time 9560015837 ps
CPU time 99.98 seconds
Started Mar 12 01:40:09 PM PDT 24
Finished Mar 12 01:41:49 PM PDT 24
Peak memory 247560 kb
Host smart-5429faef-deb9-44bc-b05b-863874c15524
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845063018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3845063018
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.1866918141
Short name T222
Test name
Test status
Simulation time 899963939 ps
CPU time 19.95 seconds
Started Mar 12 01:40:06 PM PDT 24
Finished Mar 12 01:40:27 PM PDT 24
Peak memory 248408 kb
Host smart-16a73b42-c1c8-4fec-bccc-dad7272bd506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18669
18141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.1866918141
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.1061563614
Short name T381
Test name
Test status
Simulation time 2550690614 ps
CPU time 58.53 seconds
Started Mar 12 01:40:04 PM PDT 24
Finished Mar 12 01:41:03 PM PDT 24
Peak memory 248108 kb
Host smart-8258985e-302f-405f-9cb6-77221a164cbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10615
63614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.1061563614
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.1886552497
Short name T109
Test name
Test status
Simulation time 2055928157 ps
CPU time 40.49 seconds
Started Mar 12 01:40:12 PM PDT 24
Finished Mar 12 01:40:53 PM PDT 24
Peak memory 248544 kb
Host smart-815935ab-11e6-4bb2-8b73-9e9b3d90c0fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18865
52497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.1886552497
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.4006596108
Short name T619
Test name
Test status
Simulation time 71584122977 ps
CPU time 1647.18 seconds
Started Mar 12 01:40:04 PM PDT 24
Finished Mar 12 02:07:32 PM PDT 24
Peak memory 289540 kb
Host smart-5a4092af-6b11-443f-8284-5e2f98e2fa65
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006596108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.4006596108
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.1017762787
Short name T490
Test name
Test status
Simulation time 44300901650 ps
CPU time 4315.13 seconds
Started Mar 12 01:40:10 PM PDT 24
Finished Mar 12 02:52:06 PM PDT 24
Peak memory 332604 kb
Host smart-cbfbdeb9-8127-4f1a-b46d-1b044d33ce6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017762787 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.1017762787
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.2968786480
Short name T522
Test name
Test status
Simulation time 33450874832 ps
CPU time 1751.31 seconds
Started Mar 12 01:40:08 PM PDT 24
Finished Mar 12 02:09:20 PM PDT 24
Peak memory 289400 kb
Host smart-ee47caea-aed4-4418-bc08-126206592a0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968786480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.2968786480
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.1647247695
Short name T382
Test name
Test status
Simulation time 1128773472 ps
CPU time 114.7 seconds
Started Mar 12 01:40:14 PM PDT 24
Finished Mar 12 01:42:08 PM PDT 24
Peak memory 256256 kb
Host smart-921a3e20-0408-4c39-8482-8a3a2e3cb15d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16472
47695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.1647247695
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.1937240791
Short name T482
Test name
Test status
Simulation time 362372912 ps
CPU time 37.35 seconds
Started Mar 12 01:40:10 PM PDT 24
Finished Mar 12 01:40:48 PM PDT 24
Peak memory 254756 kb
Host smart-1682f6a8-a9f7-4431-9308-f7fdf00d49a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19372
40791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.1937240791
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.304088357
Short name T622
Test name
Test status
Simulation time 60149619689 ps
CPU time 3318.68 seconds
Started Mar 12 01:40:13 PM PDT 24
Finished Mar 12 02:35:32 PM PDT 24
Peak memory 288552 kb
Host smart-61833aaf-950b-4820-841e-006e2a0900ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304088357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.304088357
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.3706142339
Short name T681
Test name
Test status
Simulation time 38934046319 ps
CPU time 2471.6 seconds
Started Mar 12 01:40:13 PM PDT 24
Finished Mar 12 02:21:25 PM PDT 24
Peak memory 273084 kb
Host smart-e82af00a-dc5e-4ac9-8a97-447b1268eb70
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706142339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.3706142339
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.1361595932
Short name T221
Test name
Test status
Simulation time 1413385864 ps
CPU time 27.33 seconds
Started Mar 12 01:40:03 PM PDT 24
Finished Mar 12 01:40:31 PM PDT 24
Peak memory 256692 kb
Host smart-f418874e-0ffa-4816-b08c-ed31b54cb148
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13615
95932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.1361595932
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.2389976626
Short name T467
Test name
Test status
Simulation time 1343631656 ps
CPU time 45.52 seconds
Started Mar 12 01:40:11 PM PDT 24
Finished Mar 12 01:40:57 PM PDT 24
Peak memory 247100 kb
Host smart-7c4f6a2d-612a-4e96-b7f4-fc8af6bb18d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23899
76626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2389976626
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.2891403919
Short name T372
Test name
Test status
Simulation time 956842274 ps
CPU time 34.38 seconds
Started Mar 12 01:40:14 PM PDT 24
Finished Mar 12 01:40:49 PM PDT 24
Peak memory 255224 kb
Host smart-eff2d821-80f1-40eb-83d2-e2caffb3f18f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28914
03919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.2891403919
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.863618874
Short name T484
Test name
Test status
Simulation time 892174514 ps
CPU time 58.07 seconds
Started Mar 12 01:40:05 PM PDT 24
Finished Mar 12 01:41:03 PM PDT 24
Peak memory 248524 kb
Host smart-ea0c1f09-fb0f-49fd-af1f-7e4c1c9567d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86361
8874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.863618874
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.3689430281
Short name T408
Test name
Test status
Simulation time 33884019358 ps
CPU time 1476 seconds
Started Mar 12 01:40:13 PM PDT 24
Finished Mar 12 02:04:49 PM PDT 24
Peak memory 289336 kb
Host smart-71efcdbb-275f-4560-a71e-1bef2104740c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689430281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.3689430281
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.2102379073
Short name T369
Test name
Test status
Simulation time 43826228805 ps
CPU time 1581.27 seconds
Started Mar 12 01:40:11 PM PDT 24
Finished Mar 12 02:06:33 PM PDT 24
Peak memory 272148 kb
Host smart-5f84fb10-5676-4d2e-b5f2-375ae5853083
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102379073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.2102379073
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.1838187622
Short name T424
Test name
Test status
Simulation time 5054603534 ps
CPU time 279.76 seconds
Started Mar 12 01:40:09 PM PDT 24
Finished Mar 12 01:44:49 PM PDT 24
Peak memory 256388 kb
Host smart-427a1afd-8383-421a-918d-bcd3f701c350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18381
87622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.1838187622
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.812868700
Short name T598
Test name
Test status
Simulation time 3324591727 ps
CPU time 53.42 seconds
Started Mar 12 01:40:10 PM PDT 24
Finished Mar 12 01:41:04 PM PDT 24
Peak memory 255220 kb
Host smart-05edd334-8f0f-489a-a3eb-69f5743619c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81286
8700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.812868700
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.1283731656
Short name T701
Test name
Test status
Simulation time 58328395805 ps
CPU time 1081.58 seconds
Started Mar 12 01:40:15 PM PDT 24
Finished Mar 12 01:58:17 PM PDT 24
Peak memory 272808 kb
Host smart-185b5678-afb0-450d-8986-6fc9137d0d21
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283731656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.1283731656
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.3985799167
Short name T673
Test name
Test status
Simulation time 41805027238 ps
CPU time 2494.33 seconds
Started Mar 12 01:40:14 PM PDT 24
Finished Mar 12 02:21:48 PM PDT 24
Peak memory 272184 kb
Host smart-316e1df8-8b16-4afc-9c1b-2b68cc830b8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985799167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.3985799167
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.1171517395
Short name T306
Test name
Test status
Simulation time 31481239033 ps
CPU time 186 seconds
Started Mar 12 01:40:10 PM PDT 24
Finished Mar 12 01:43:17 PM PDT 24
Peak memory 247184 kb
Host smart-e5495431-6b0e-4f47-bb10-6c0b3295ecce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171517395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.1171517395
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.3019545421
Short name T435
Test name
Test status
Simulation time 3372153826 ps
CPU time 48.73 seconds
Started Mar 12 01:40:04 PM PDT 24
Finished Mar 12 01:40:53 PM PDT 24
Peak memory 256792 kb
Host smart-ae09893a-12f2-4f51-a02d-acc82ac4e0da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30195
45421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.3019545421
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.1238591900
Short name T357
Test name
Test status
Simulation time 1274358225 ps
CPU time 22.13 seconds
Started Mar 12 01:40:15 PM PDT 24
Finished Mar 12 01:40:37 PM PDT 24
Peak memory 253140 kb
Host smart-cfad89d7-5e3e-41a5-8ad6-c5f40913fb1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12385
91900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.1238591900
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.1328829736
Short name T584
Test name
Test status
Simulation time 332909893 ps
CPU time 29.16 seconds
Started Mar 12 01:40:09 PM PDT 24
Finished Mar 12 01:40:39 PM PDT 24
Peak memory 246896 kb
Host smart-5f7107e6-52e6-4c3e-bb66-0611c6791ac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13288
29736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.1328829736
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.3958855198
Short name T438
Test name
Test status
Simulation time 1760265060 ps
CPU time 34.64 seconds
Started Mar 12 01:40:13 PM PDT 24
Finished Mar 12 01:40:48 PM PDT 24
Peak memory 248548 kb
Host smart-c1bf8ced-4955-492c-a2a0-88a1a19cf08f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39588
55198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.3958855198
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.550713758
Short name T540
Test name
Test status
Simulation time 45258612729 ps
CPU time 4383.95 seconds
Started Mar 12 01:40:11 PM PDT 24
Finished Mar 12 02:53:15 PM PDT 24
Peak memory 313856 kb
Host smart-90d4fd70-dc60-4f11-b32f-f9ef8dc5b61e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550713758 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.550713758
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.525801259
Short name T527
Test name
Test status
Simulation time 696758284954 ps
CPU time 2066.36 seconds
Started Mar 12 01:40:14 PM PDT 24
Finished Mar 12 02:14:41 PM PDT 24
Peak memory 284844 kb
Host smart-6bd4d183-ca49-493b-83d2-b70f08121a58
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525801259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.525801259
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.357285472
Short name T680
Test name
Test status
Simulation time 651344985 ps
CPU time 4.87 seconds
Started Mar 12 01:40:09 PM PDT 24
Finished Mar 12 01:40:15 PM PDT 24
Peak memory 250384 kb
Host smart-351d9a4e-3ba0-45a7-b819-ebe7adf2a942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35728
5472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.357285472
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.360588299
Short name T388
Test name
Test status
Simulation time 1351245663 ps
CPU time 46.3 seconds
Started Mar 12 01:40:12 PM PDT 24
Finished Mar 12 01:40:59 PM PDT 24
Peak memory 254908 kb
Host smart-f4dc3aca-8847-4b6a-992e-88f4a595d3f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36058
8299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.360588299
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.2529833013
Short name T283
Test name
Test status
Simulation time 57352200663 ps
CPU time 1644.08 seconds
Started Mar 12 01:40:12 PM PDT 24
Finished Mar 12 02:07:37 PM PDT 24
Peak memory 289520 kb
Host smart-546a7df0-0f78-4f83-a590-171514d07bba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529833013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.2529833013
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.3575205116
Short name T274
Test name
Test status
Simulation time 210044322640 ps
CPU time 3161.46 seconds
Started Mar 12 01:40:12 PM PDT 24
Finished Mar 12 02:32:54 PM PDT 24
Peak memory 288988 kb
Host smart-0b56d767-db4d-4cf9-b761-cf377e2f0452
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575205116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.3575205116
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.2724297685
Short name T311
Test name
Test status
Simulation time 19950311017 ps
CPU time 388.45 seconds
Started Mar 12 01:40:11 PM PDT 24
Finished Mar 12 01:46:40 PM PDT 24
Peak memory 248752 kb
Host smart-6b29e18d-f1d4-496a-ada9-30a835a0c0cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724297685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.2724297685
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.708047901
Short name T588
Test name
Test status
Simulation time 51284201 ps
CPU time 7 seconds
Started Mar 12 01:40:17 PM PDT 24
Finished Mar 12 01:40:24 PM PDT 24
Peak memory 253480 kb
Host smart-09c6a8d0-b8d8-4144-b9b7-ab1527d7e688
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70804
7901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.708047901
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.1182089692
Short name T570
Test name
Test status
Simulation time 339594422 ps
CPU time 26.32 seconds
Started Mar 12 01:40:11 PM PDT 24
Finished Mar 12 01:40:38 PM PDT 24
Peak memory 255164 kb
Host smart-9448b1ae-4f37-460d-ba6c-d275d0be5024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11820
89692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.1182089692
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.3608901948
Short name T22
Test name
Test status
Simulation time 681627298 ps
CPU time 21.7 seconds
Started Mar 12 01:40:10 PM PDT 24
Finished Mar 12 01:40:32 PM PDT 24
Peak memory 248540 kb
Host smart-9db63c66-4e62-4ee9-be12-a9b0c53aa373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36089
01948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.3608901948
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.1574106349
Short name T660
Test name
Test status
Simulation time 1199674202 ps
CPU time 32.65 seconds
Started Mar 12 01:40:11 PM PDT 24
Finished Mar 12 01:40:44 PM PDT 24
Peak memory 248532 kb
Host smart-e95f02cc-6ca4-4107-8de6-85e0a142dce8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15741
06349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.1574106349
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.2007233198
Short name T429
Test name
Test status
Simulation time 37947812634 ps
CPU time 2622.3 seconds
Started Mar 12 01:40:15 PM PDT 24
Finished Mar 12 02:23:58 PM PDT 24
Peak memory 289480 kb
Host smart-acb4750a-b6fb-49f7-b8f5-216331608181
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007233198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.2007233198
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.581883261
Short name T480
Test name
Test status
Simulation time 3585551171 ps
CPU time 106.24 seconds
Started Mar 12 01:40:19 PM PDT 24
Finished Mar 12 01:42:05 PM PDT 24
Peak memory 256204 kb
Host smart-68e3cd8f-daca-4ccc-adc4-35ef0c98bbb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58188
3261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.581883261
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.2227541724
Short name T603
Test name
Test status
Simulation time 1023870390 ps
CPU time 28.3 seconds
Started Mar 12 01:40:22 PM PDT 24
Finished Mar 12 01:40:50 PM PDT 24
Peak memory 248220 kb
Host smart-f32157f5-7267-47eb-97bc-c3d5b7b82930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22275
41724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2227541724
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.26812359
Short name T4
Test name
Test status
Simulation time 10095831396 ps
CPU time 1450.86 seconds
Started Mar 12 01:40:19 PM PDT 24
Finished Mar 12 02:04:30 PM PDT 24
Peak memory 289428 kb
Host smart-0e590ce5-3046-46e8-baef-c335ec5a92e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26812359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.26812359
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.3760994733
Short name T292
Test name
Test status
Simulation time 10188323243 ps
CPU time 436.81 seconds
Started Mar 12 01:40:21 PM PDT 24
Finished Mar 12 01:47:38 PM PDT 24
Peak memory 247188 kb
Host smart-6aa12779-b022-4c6d-b9e1-1e0d4c754c05
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760994733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.3760994733
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.2775914005
Short name T436
Test name
Test status
Simulation time 231005657 ps
CPU time 16.12 seconds
Started Mar 12 01:40:20 PM PDT 24
Finished Mar 12 01:40:36 PM PDT 24
Peak memory 248520 kb
Host smart-9b69f7fa-3fae-4a8e-9edc-4d76b3c30dfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27759
14005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.2775914005
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.2473186267
Short name T35
Test name
Test status
Simulation time 2389742560 ps
CPU time 23.19 seconds
Started Mar 12 01:40:20 PM PDT 24
Finished Mar 12 01:40:43 PM PDT 24
Peak memory 253812 kb
Host smart-f0ddd097-7e27-4496-82ec-a88739fd3445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24731
86267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.2473186267
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.1640078460
Short name T63
Test name
Test status
Simulation time 162807582 ps
CPU time 16.52 seconds
Started Mar 12 01:40:11 PM PDT 24
Finished Mar 12 01:40:28 PM PDT 24
Peak memory 248512 kb
Host smart-26a360bc-30e2-41f0-8255-b3946b4c40fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16400
78460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.1640078460
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.3630701896
Short name T281
Test name
Test status
Simulation time 103712046864 ps
CPU time 1690.64 seconds
Started Mar 12 01:40:33 PM PDT 24
Finished Mar 12 02:08:44 PM PDT 24
Peak memory 281300 kb
Host smart-c510067c-5cb7-45f8-a6d9-184b249bdaed
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630701896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.3630701896
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.2723397919
Short name T286
Test name
Test status
Simulation time 164182252662 ps
CPU time 4482.14 seconds
Started Mar 12 01:40:23 PM PDT 24
Finished Mar 12 02:55:06 PM PDT 24
Peak memory 338188 kb
Host smart-29478cb8-6a18-44eb-8807-8f28bb1fdc49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723397919 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.2723397919
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.2774963818
Short name T100
Test name
Test status
Simulation time 18507652034 ps
CPU time 1400.96 seconds
Started Mar 12 01:40:20 PM PDT 24
Finished Mar 12 02:03:42 PM PDT 24
Peak memory 289396 kb
Host smart-649dadcc-8396-4623-99df-226f27f9f4fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774963818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.2774963818
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.2876996602
Short name T419
Test name
Test status
Simulation time 2822195101 ps
CPU time 116.65 seconds
Started Mar 12 01:40:20 PM PDT 24
Finished Mar 12 01:42:17 PM PDT 24
Peak memory 256492 kb
Host smart-266a0fc1-5127-40ad-a62b-b525a229c5b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28769
96602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.2876996602
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.1090403319
Short name T82
Test name
Test status
Simulation time 2503404622 ps
CPU time 72.08 seconds
Started Mar 12 01:40:21 PM PDT 24
Finished Mar 12 01:41:33 PM PDT 24
Peak memory 255036 kb
Host smart-d28a9a09-740b-48d7-a2ce-8e95495519a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10904
03319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.1090403319
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.3800834588
Short name T13
Test name
Test status
Simulation time 48660910274 ps
CPU time 1380.14 seconds
Started Mar 12 01:40:33 PM PDT 24
Finished Mar 12 02:03:33 PM PDT 24
Peak memory 283336 kb
Host smart-374dc9a9-1b7f-4b17-b9ee-6297655b5402
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800834588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.3800834588
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.3515575849
Short name T579
Test name
Test status
Simulation time 79132825399 ps
CPU time 2651.94 seconds
Started Mar 12 01:40:20 PM PDT 24
Finished Mar 12 02:24:33 PM PDT 24
Peak memory 288952 kb
Host smart-8a14e3d2-a816-4d60-a8b1-8f544638646b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515575849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.3515575849
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.2751324410
Short name T461
Test name
Test status
Simulation time 21274013326 ps
CPU time 215.41 seconds
Started Mar 12 01:40:33 PM PDT 24
Finished Mar 12 01:44:08 PM PDT 24
Peak memory 248300 kb
Host smart-6ba00e57-8949-428f-b48f-54985c14cd92
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751324410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.2751324410
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.3508966032
Short name T353
Test name
Test status
Simulation time 1567794991 ps
CPU time 55.89 seconds
Started Mar 12 01:40:33 PM PDT 24
Finished Mar 12 01:41:29 PM PDT 24
Peak memory 255092 kb
Host smart-ad741458-b006-41bf-a286-1571c1a2813e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35089
66032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.3508966032
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.233217267
Short name T105
Test name
Test status
Simulation time 439791319 ps
CPU time 40.6 seconds
Started Mar 12 01:40:18 PM PDT 24
Finished Mar 12 01:40:59 PM PDT 24
Peak memory 248124 kb
Host smart-a8045702-327f-4358-ab62-43f026e2c1af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23321
7267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.233217267
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.3690168798
Short name T83
Test name
Test status
Simulation time 770214294 ps
CPU time 12.39 seconds
Started Mar 12 01:40:20 PM PDT 24
Finished Mar 12 01:40:32 PM PDT 24
Peak memory 251332 kb
Host smart-c8d29a32-63e3-438a-8640-0a15f58fd3fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36901
68798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.3690168798
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.2555586539
Short name T630
Test name
Test status
Simulation time 4914239547 ps
CPU time 74.76 seconds
Started Mar 12 01:40:19 PM PDT 24
Finished Mar 12 01:41:34 PM PDT 24
Peak memory 248588 kb
Host smart-9c064b7a-cf18-4ba6-86d1-57ba2ab0be68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25555
86539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.2555586539
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.1763409444
Short name T679
Test name
Test status
Simulation time 41842149041 ps
CPU time 2175.93 seconds
Started Mar 12 01:40:29 PM PDT 24
Finished Mar 12 02:16:46 PM PDT 24
Peak memory 289180 kb
Host smart-150eddcf-c921-4f94-9ab0-d7e9b11873c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763409444 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.1763409444
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.507289368
Short name T636
Test name
Test status
Simulation time 22875775834 ps
CPU time 1523.87 seconds
Started Mar 12 01:40:25 PM PDT 24
Finished Mar 12 02:05:50 PM PDT 24
Peak memory 272232 kb
Host smart-8d905b73-d151-46bf-b8bb-3c5b7d6f49cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507289368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.507289368
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.292691153
Short name T464
Test name
Test status
Simulation time 954182806 ps
CPU time 41.96 seconds
Started Mar 12 01:40:29 PM PDT 24
Finished Mar 12 01:41:11 PM PDT 24
Peak memory 255904 kb
Host smart-dd9bd64f-989f-4011-96c7-bc6d72fe990f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29269
1153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.292691153
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.87996192
Short name T594
Test name
Test status
Simulation time 318151594 ps
CPU time 23.48 seconds
Started Mar 12 01:40:29 PM PDT 24
Finished Mar 12 01:40:52 PM PDT 24
Peak memory 254204 kb
Host smart-3504203e-31e1-42ab-be9f-ad44829d9136
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87996
192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.87996192
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.31425275
Short name T510
Test name
Test status
Simulation time 151995554982 ps
CPU time 2384.38 seconds
Started Mar 12 01:40:28 PM PDT 24
Finished Mar 12 02:20:13 PM PDT 24
Peak memory 288960 kb
Host smart-3dfee38b-58e5-4bdc-b3a5-af8c885e4928
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31425275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.31425275
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.803797389
Short name T308
Test name
Test status
Simulation time 20546913221 ps
CPU time 145.84 seconds
Started Mar 12 01:40:25 PM PDT 24
Finished Mar 12 01:42:51 PM PDT 24
Peak memory 246544 kb
Host smart-a02aa5ad-8132-4981-b194-f7c208e2956f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803797389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.803797389
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.1179028666
Short name T552
Test name
Test status
Simulation time 3400637809 ps
CPU time 64.96 seconds
Started Mar 12 01:40:27 PM PDT 24
Finished Mar 12 01:41:32 PM PDT 24
Peak memory 248504 kb
Host smart-34bcb12a-c282-4abb-96cb-a6643b33c0f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11790
28666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.1179028666
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.1933043065
Short name T230
Test name
Test status
Simulation time 522090016 ps
CPU time 35.05 seconds
Started Mar 12 01:40:31 PM PDT 24
Finished Mar 12 01:41:06 PM PDT 24
Peak memory 254048 kb
Host smart-eb758aec-a59a-411c-afcd-ac55e0aa0553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19330
43065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.1933043065
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.2879354209
Short name T18
Test name
Test status
Simulation time 394822870 ps
CPU time 29.45 seconds
Started Mar 12 01:40:29 PM PDT 24
Finished Mar 12 01:40:59 PM PDT 24
Peak memory 247892 kb
Host smart-589c1cfc-46d2-4155-a5af-d1ef498bc3ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28793
54209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.2879354209
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.82372812
Short name T569
Test name
Test status
Simulation time 619366115 ps
CPU time 45.96 seconds
Started Mar 12 01:40:26 PM PDT 24
Finished Mar 12 01:41:12 PM PDT 24
Peak memory 255268 kb
Host smart-d3ea67ed-14d3-4a8a-9760-86b9b8a25280
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82372
812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.82372812
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.2653980057
Short name T113
Test name
Test status
Simulation time 46623901 ps
CPU time 3.92 seconds
Started Mar 12 01:39:07 PM PDT 24
Finished Mar 12 01:39:11 PM PDT 24
Peak memory 248672 kb
Host smart-7e72a16e-134a-46fa-acd6-049de0c60668
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2653980057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.2653980057
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.2913066978
Short name T97
Test name
Test status
Simulation time 38730766606 ps
CPU time 1391.6 seconds
Started Mar 12 01:38:55 PM PDT 24
Finished Mar 12 02:02:07 PM PDT 24
Peak memory 267296 kb
Host smart-abc8df6c-c3e9-4c0a-800d-59852f4637a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913066978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.2913066978
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.4071266283
Short name T635
Test name
Test status
Simulation time 1447020622 ps
CPU time 58.47 seconds
Started Mar 12 01:38:52 PM PDT 24
Finished Mar 12 01:39:50 PM PDT 24
Peak memory 240236 kb
Host smart-3e2a0d52-455b-42d6-8ed0-7fdc4c191dc9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4071266283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.4071266283
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.557531767
Short name T277
Test name
Test status
Simulation time 21044315663 ps
CPU time 301.44 seconds
Started Mar 12 01:39:15 PM PDT 24
Finished Mar 12 01:44:19 PM PDT 24
Peak memory 256248 kb
Host smart-43da9418-9ea2-44fe-9e10-6b858ad6e10e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55753
1767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.557531767
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.3130422080
Short name T574
Test name
Test status
Simulation time 103901275 ps
CPU time 11.33 seconds
Started Mar 12 01:38:36 PM PDT 24
Finished Mar 12 01:38:48 PM PDT 24
Peak memory 254076 kb
Host smart-a9c33057-be84-4121-8d73-03dfb651f844
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31304
22080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.3130422080
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.2094300431
Short name T471
Test name
Test status
Simulation time 84416492737 ps
CPU time 1982.63 seconds
Started Mar 12 01:38:37 PM PDT 24
Finished Mar 12 02:11:40 PM PDT 24
Peak memory 289004 kb
Host smart-bf985663-7895-48ef-9f08-36248ebaa064
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094300431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.2094300431
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.1588409718
Short name T38
Test name
Test status
Simulation time 85792110703 ps
CPU time 1980.44 seconds
Started Mar 12 01:39:15 PM PDT 24
Finished Mar 12 02:12:20 PM PDT 24
Peak memory 272504 kb
Host smart-ac7924d3-c72f-4f54-a4df-994ab0f7f433
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588409718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.1588409718
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.1745640986
Short name T506
Test name
Test status
Simulation time 11624010955 ps
CPU time 463.71 seconds
Started Mar 12 01:38:55 PM PDT 24
Finished Mar 12 01:46:39 PM PDT 24
Peak memory 246436 kb
Host smart-c32c638e-cf3f-435d-bebd-a04bd47bab1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745640986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.1745640986
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.686379769
Short name T37
Test name
Test status
Simulation time 479531528 ps
CPU time 34.85 seconds
Started Mar 12 01:39:14 PM PDT 24
Finished Mar 12 01:39:51 PM PDT 24
Peak memory 255328 kb
Host smart-aef3c31e-b7e5-477c-8794-7612480fcdea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68637
9769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.686379769
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.99286071
Short name T275
Test name
Test status
Simulation time 4013926651 ps
CPU time 63.94 seconds
Started Mar 12 01:38:57 PM PDT 24
Finished Mar 12 01:40:01 PM PDT 24
Peak memory 248580 kb
Host smart-447f81d6-fe7f-468c-a65f-9397983e2f6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99286
071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.99286071
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.1969051376
Short name T8
Test name
Test status
Simulation time 1770221037 ps
CPU time 24.68 seconds
Started Mar 12 01:39:15 PM PDT 24
Finished Mar 12 01:39:41 PM PDT 24
Peak memory 274128 kb
Host smart-bf37ab99-eb6d-422e-9db7-e61fdf6c10c7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1969051376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.1969051376
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.399731847
Short name T609
Test name
Test status
Simulation time 249686325 ps
CPU time 14.73 seconds
Started Mar 12 01:39:08 PM PDT 24
Finished Mar 12 01:39:24 PM PDT 24
Peak memory 248540 kb
Host smart-2fa99412-8a02-465f-b56b-b732513f02e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39973
1847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.399731847
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.789833546
Short name T361
Test name
Test status
Simulation time 712216866 ps
CPU time 44.32 seconds
Started Mar 12 01:39:06 PM PDT 24
Finished Mar 12 01:39:51 PM PDT 24
Peak memory 248540 kb
Host smart-beaad511-9b31-43fa-b8ed-b32e0de32cba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78983
3546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.789833546
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.3812557091
Short name T80
Test name
Test status
Simulation time 23565584709 ps
CPU time 1353.06 seconds
Started Mar 12 01:39:16 PM PDT 24
Finished Mar 12 02:01:53 PM PDT 24
Peak memory 271700 kb
Host smart-c7818b00-1497-4406-84e7-ddd5c0d9c1e7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812557091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.3812557091
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.2238816001
Short name T608
Test name
Test status
Simulation time 65806474910 ps
CPU time 2088.92 seconds
Started Mar 12 01:40:31 PM PDT 24
Finished Mar 12 02:15:20 PM PDT 24
Peak memory 289448 kb
Host smart-37029ebf-0212-4e77-bdb1-d6fd1db02c04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238816001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.2238816001
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.3802728118
Short name T16
Test name
Test status
Simulation time 4231600806 ps
CPU time 52.05 seconds
Started Mar 12 01:40:27 PM PDT 24
Finished Mar 12 01:41:19 PM PDT 24
Peak memory 256072 kb
Host smart-170739dc-89b7-41de-bd7e-42222eeab508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38027
28118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.3802728118
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.3650157705
Short name T418
Test name
Test status
Simulation time 2737822335 ps
CPU time 51.36 seconds
Started Mar 12 01:40:28 PM PDT 24
Finished Mar 12 01:41:19 PM PDT 24
Peak memory 256228 kb
Host smart-3f903725-eff5-47ac-8549-28a057dbe7ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36501
57705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.3650157705
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.4239307472
Short name T287
Test name
Test status
Simulation time 39300614203 ps
CPU time 865.88 seconds
Started Mar 12 01:40:35 PM PDT 24
Finished Mar 12 01:55:01 PM PDT 24
Peak memory 272552 kb
Host smart-a5fe205c-0f5f-41d5-951a-390a98203fa5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239307472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.4239307472
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.2090800869
Short name T447
Test name
Test status
Simulation time 27477349295 ps
CPU time 1809.39 seconds
Started Mar 12 01:40:36 PM PDT 24
Finished Mar 12 02:10:46 PM PDT 24
Peak memory 288908 kb
Host smart-bab3aa91-219d-4259-87f4-fee4cfff5fb3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090800869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.2090800869
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.2815352229
Short name T620
Test name
Test status
Simulation time 6487395601 ps
CPU time 145.31 seconds
Started Mar 12 01:40:29 PM PDT 24
Finished Mar 12 01:42:55 PM PDT 24
Peak memory 246420 kb
Host smart-bb22b106-7a58-4cd0-94fc-4dcb1c7eca54
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815352229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.2815352229
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.4126439812
Short name T487
Test name
Test status
Simulation time 337850639 ps
CPU time 13.66 seconds
Started Mar 12 01:40:27 PM PDT 24
Finished Mar 12 01:40:41 PM PDT 24
Peak memory 248544 kb
Host smart-8beb077b-c636-4b49-83e6-760328ad8549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41264
39812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.4126439812
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.2487854011
Short name T449
Test name
Test status
Simulation time 470035266 ps
CPU time 27.14 seconds
Started Mar 12 01:40:27 PM PDT 24
Finished Mar 12 01:40:55 PM PDT 24
Peak memory 254660 kb
Host smart-40d7c915-9d47-45df-9272-985a27ad570d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24878
54011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.2487854011
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.2588399447
Short name T683
Test name
Test status
Simulation time 40063663 ps
CPU time 6.74 seconds
Started Mar 12 01:40:27 PM PDT 24
Finished Mar 12 01:40:34 PM PDT 24
Peak memory 249908 kb
Host smart-5432d6b7-178b-401d-bfbd-6bb84581f235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25883
99447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.2588399447
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.2106228941
Short name T347
Test name
Test status
Simulation time 1119934253 ps
CPU time 22.65 seconds
Started Mar 12 01:40:28 PM PDT 24
Finished Mar 12 01:40:51 PM PDT 24
Peak memory 248540 kb
Host smart-6d686146-0950-4402-af68-f10dad1a3faa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21062
28941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.2106228941
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.1998734515
Short name T561
Test name
Test status
Simulation time 29012657940 ps
CPU time 514.04 seconds
Started Mar 12 01:40:30 PM PDT 24
Finished Mar 12 01:49:05 PM PDT 24
Peak memory 252908 kb
Host smart-0a7728ce-3497-4d64-89b7-622992a02024
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998734515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.1998734515
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.2898167647
Short name T265
Test name
Test status
Simulation time 41971533274 ps
CPU time 1758.59 seconds
Started Mar 12 01:40:31 PM PDT 24
Finished Mar 12 02:09:50 PM PDT 24
Peak memory 304672 kb
Host smart-1816f427-1745-4b41-9b98-bd7bde3bb7e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898167647 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.2898167647
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.682594395
Short name T454
Test name
Test status
Simulation time 56478407318 ps
CPU time 1182.14 seconds
Started Mar 12 01:40:34 PM PDT 24
Finished Mar 12 02:00:17 PM PDT 24
Peak memory 288976 kb
Host smart-1705a5ad-3fef-475b-ad4f-05797276c30d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682594395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.682594395
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.2578533697
Short name T637
Test name
Test status
Simulation time 5338693792 ps
CPU time 114.87 seconds
Started Mar 12 01:40:35 PM PDT 24
Finished Mar 12 01:42:30 PM PDT 24
Peak memory 256076 kb
Host smart-a7ccd8b1-fdc6-4498-bbf1-9ce204a627b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25785
33697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.2578533697
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.1298153219
Short name T515
Test name
Test status
Simulation time 1111628849 ps
CPU time 7.42 seconds
Started Mar 12 01:40:34 PM PDT 24
Finished Mar 12 01:40:42 PM PDT 24
Peak memory 249044 kb
Host smart-900e4ee8-fd39-4957-9d27-3336e76d3be9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12981
53219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.1298153219
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.2264167827
Short name T89
Test name
Test status
Simulation time 8009352150 ps
CPU time 700.7 seconds
Started Mar 12 01:40:37 PM PDT 24
Finished Mar 12 01:52:18 PM PDT 24
Peak memory 271352 kb
Host smart-8ca2accb-af11-47f6-97fa-f4ddc5ea8d35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264167827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.2264167827
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.1695105925
Short name T612
Test name
Test status
Simulation time 48314261678 ps
CPU time 2793.63 seconds
Started Mar 12 01:40:32 PM PDT 24
Finished Mar 12 02:27:06 PM PDT 24
Peak memory 288920 kb
Host smart-40ae2cda-5a65-421d-881f-c2fdbef5642d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695105925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.1695105925
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.530976618
Short name T297
Test name
Test status
Simulation time 35401099437 ps
CPU time 210.88 seconds
Started Mar 12 01:40:35 PM PDT 24
Finished Mar 12 01:44:06 PM PDT 24
Peak memory 247388 kb
Host smart-def1b65e-defc-4925-8a48-33b6ba1fe8de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530976618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.530976618
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.1074181514
Short name T245
Test name
Test status
Simulation time 149435377 ps
CPU time 13.25 seconds
Started Mar 12 01:40:29 PM PDT 24
Finished Mar 12 01:40:42 PM PDT 24
Peak memory 248524 kb
Host smart-ac5d3ab7-a7eb-4a70-8d20-c9301fae862c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10741
81514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.1074181514
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.1166562434
Short name T640
Test name
Test status
Simulation time 5027178039 ps
CPU time 62.3 seconds
Started Mar 12 01:40:29 PM PDT 24
Finished Mar 12 01:41:32 PM PDT 24
Peak memory 255556 kb
Host smart-f6604ec2-7494-41ac-97e2-ba3d19ad60b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11665
62434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.1166562434
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.1427292535
Short name T389
Test name
Test status
Simulation time 1896497546 ps
CPU time 39.18 seconds
Started Mar 12 01:40:34 PM PDT 24
Finished Mar 12 01:41:13 PM PDT 24
Peak memory 246876 kb
Host smart-19303195-cd73-4f9c-9620-57de08c65756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14272
92535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.1427292535
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.3399830465
Short name T595
Test name
Test status
Simulation time 90717003 ps
CPU time 10.65 seconds
Started Mar 12 01:40:31 PM PDT 24
Finished Mar 12 01:40:42 PM PDT 24
Peak memory 254072 kb
Host smart-e3bb6ce9-fa2d-40d6-9ce3-fdad73d8f4cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33998
30465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.3399830465
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.3510134260
Short name T48
Test name
Test status
Simulation time 78477469316 ps
CPU time 1746.44 seconds
Started Mar 12 01:40:36 PM PDT 24
Finished Mar 12 02:09:43 PM PDT 24
Peak memory 298552 kb
Host smart-51c26b6b-7cd0-4f91-be0a-e65a52b71644
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510134260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.3510134260
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.2296220663
Short name T92
Test name
Test status
Simulation time 14533625902 ps
CPU time 1490.89 seconds
Started Mar 12 01:40:36 PM PDT 24
Finished Mar 12 02:05:27 PM PDT 24
Peak memory 281328 kb
Host smart-34710c59-a453-4aea-bad6-0016eb8abff0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296220663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.2296220663
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.4025822871
Short name T370
Test name
Test status
Simulation time 1607436033 ps
CPU time 57.4 seconds
Started Mar 12 01:40:34 PM PDT 24
Finished Mar 12 01:41:32 PM PDT 24
Peak memory 248320 kb
Host smart-223b3ca9-68f3-4770-9a27-2a0e5e307b71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40258
22871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.4025822871
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.3981841174
Short name T69
Test name
Test status
Simulation time 577487141 ps
CPU time 12.6 seconds
Started Mar 12 01:40:36 PM PDT 24
Finished Mar 12 01:40:49 PM PDT 24
Peak memory 254108 kb
Host smart-381c26e2-fe2a-4705-9127-438f5bc73bcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39818
41174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.3981841174
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.3741682432
Short name T469
Test name
Test status
Simulation time 32823172181 ps
CPU time 601.97 seconds
Started Mar 12 01:40:36 PM PDT 24
Finished Mar 12 01:50:38 PM PDT 24
Peak memory 265024 kb
Host smart-52da1b19-2f4c-4c56-a3ce-551c817f129f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741682432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.3741682432
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.651907045
Short name T426
Test name
Test status
Simulation time 204444477739 ps
CPU time 3109.5 seconds
Started Mar 12 01:40:42 PM PDT 24
Finished Mar 12 02:32:32 PM PDT 24
Peak memory 286936 kb
Host smart-be08302f-8158-4d85-9589-53c780c79d04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651907045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.651907045
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.1530892940
Short name T294
Test name
Test status
Simulation time 46330894708 ps
CPU time 436.93 seconds
Started Mar 12 01:40:34 PM PDT 24
Finished Mar 12 01:47:51 PM PDT 24
Peak memory 247252 kb
Host smart-e22d4fab-38aa-4178-899e-702975116d59
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530892940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.1530892940
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.1719030993
Short name T692
Test name
Test status
Simulation time 140021313 ps
CPU time 21.44 seconds
Started Mar 12 01:40:33 PM PDT 24
Finished Mar 12 01:40:55 PM PDT 24
Peak memory 255124 kb
Host smart-5e9bdd55-e7f2-4358-9ea4-0fc1ac1cd8a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17190
30993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.1719030993
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.3104042665
Short name T271
Test name
Test status
Simulation time 726946718 ps
CPU time 25.92 seconds
Started Mar 12 01:40:36 PM PDT 24
Finished Mar 12 01:41:02 PM PDT 24
Peak memory 254264 kb
Host smart-20fb413d-aa44-45c8-8fc2-30b4c1a10cbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31040
42665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.3104042665
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.3888782997
Short name T589
Test name
Test status
Simulation time 521040715 ps
CPU time 31.5 seconds
Started Mar 12 01:40:37 PM PDT 24
Finished Mar 12 01:41:08 PM PDT 24
Peak memory 255200 kb
Host smart-edc1617f-9345-40df-9e88-33884120220a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38887
82997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.3888782997
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.1621611306
Short name T677
Test name
Test status
Simulation time 60598831 ps
CPU time 4.55 seconds
Started Mar 12 01:40:38 PM PDT 24
Finished Mar 12 01:40:42 PM PDT 24
Peak memory 240300 kb
Host smart-d0803534-9453-4c2e-ba33-e137acd3ca5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16216
11306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.1621611306
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.845972435
Short name T70
Test name
Test status
Simulation time 32528937631 ps
CPU time 1788.01 seconds
Started Mar 12 01:40:43 PM PDT 24
Finished Mar 12 02:10:31 PM PDT 24
Peak memory 273132 kb
Host smart-79a3d376-a91c-46a3-a0e0-a02bfc7e1aea
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845972435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_han
dler_stress_all.845972435
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.1474705419
Short name T577
Test name
Test status
Simulation time 137040284574 ps
CPU time 3732 seconds
Started Mar 12 01:40:40 PM PDT 24
Finished Mar 12 02:42:52 PM PDT 24
Peak memory 337568 kb
Host smart-31b5ec17-6d33-4866-9305-03ea5187ae03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474705419 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.1474705419
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.836684798
Short name T50
Test name
Test status
Simulation time 155492551704 ps
CPU time 2340.6 seconds
Started Mar 12 01:40:41 PM PDT 24
Finished Mar 12 02:19:42 PM PDT 24
Peak memory 285344 kb
Host smart-75d3e5ec-4146-425d-b6ad-db2853866b14
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836684798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.836684798
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.3232475543
Short name T195
Test name
Test status
Simulation time 835935647 ps
CPU time 94.16 seconds
Started Mar 12 01:40:42 PM PDT 24
Finished Mar 12 01:42:16 PM PDT 24
Peak memory 255864 kb
Host smart-28a10fcc-b8a5-4732-afb8-0c2acfb2b2ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32324
75543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.3232475543
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.3060491312
Short name T393
Test name
Test status
Simulation time 3879086546 ps
CPU time 67.76 seconds
Started Mar 12 01:40:41 PM PDT 24
Finished Mar 12 01:41:49 PM PDT 24
Peak memory 254896 kb
Host smart-2883dac9-6ea5-40db-bef4-0af9fb4bd8b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30604
91312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.3060491312
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.3828527840
Short name T327
Test name
Test status
Simulation time 107722331856 ps
CPU time 1429.53 seconds
Started Mar 12 01:40:48 PM PDT 24
Finished Mar 12 02:04:38 PM PDT 24
Peak memory 272676 kb
Host smart-2c19e109-b7ae-4fe9-a8a6-7ebf88a57941
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828527840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.3828527840
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.630732922
Short name T363
Test name
Test status
Simulation time 14517063400 ps
CPU time 1536.38 seconds
Started Mar 12 01:40:48 PM PDT 24
Finished Mar 12 02:06:25 PM PDT 24
Peak memory 281372 kb
Host smart-c7c2abe9-29a6-481b-b133-58f1da795f11
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630732922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.630732922
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.3366500625
Short name T653
Test name
Test status
Simulation time 681864568 ps
CPU time 37.68 seconds
Started Mar 12 01:40:43 PM PDT 24
Finished Mar 12 01:41:21 PM PDT 24
Peak memory 255412 kb
Host smart-03425fac-b523-42cc-ad04-d55129f2c2ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33665
00625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.3366500625
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.3305159053
Short name T375
Test name
Test status
Simulation time 99645712 ps
CPU time 7.3 seconds
Started Mar 12 01:40:41 PM PDT 24
Finished Mar 12 01:40:48 PM PDT 24
Peak memory 250992 kb
Host smart-cf47a3aa-b66b-4e70-9e26-890dc7146d15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33051
59053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.3305159053
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.2167320461
Short name T516
Test name
Test status
Simulation time 3934490167 ps
CPU time 28.87 seconds
Started Mar 12 01:40:42 PM PDT 24
Finished Mar 12 01:41:11 PM PDT 24
Peak memory 247560 kb
Host smart-ae7cc1b4-db2b-4783-93cd-fa0d9c7d8a8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21673
20461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.2167320461
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.316846708
Short name T654
Test name
Test status
Simulation time 494601818 ps
CPU time 35.96 seconds
Started Mar 12 01:40:41 PM PDT 24
Finished Mar 12 01:41:17 PM PDT 24
Peak memory 255080 kb
Host smart-c6fec044-d39b-4147-8c76-b4a7286fe167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31684
6708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.316846708
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.1279379194
Short name T233
Test name
Test status
Simulation time 2443212015 ps
CPU time 225.66 seconds
Started Mar 12 01:40:48 PM PDT 24
Finished Mar 12 01:44:34 PM PDT 24
Peak memory 256712 kb
Host smart-eb268b05-3ebf-4759-a509-397135531662
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279379194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.1279379194
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.326015587
Short name T651
Test name
Test status
Simulation time 26483969310 ps
CPU time 1496.82 seconds
Started Mar 12 01:40:58 PM PDT 24
Finished Mar 12 02:05:55 PM PDT 24
Peak memory 273112 kb
Host smart-43907712-62bc-42c0-9f7c-f106483ddc67
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326015587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.326015587
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.2286016959
Short name T473
Test name
Test status
Simulation time 4486937396 ps
CPU time 86.86 seconds
Started Mar 12 01:40:49 PM PDT 24
Finished Mar 12 01:42:16 PM PDT 24
Peak memory 256192 kb
Host smart-5e669178-920d-4f1a-aa7c-5bccc129491c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22860
16959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.2286016959
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.3607533649
Short name T638
Test name
Test status
Simulation time 1554640182 ps
CPU time 46.67 seconds
Started Mar 12 01:40:49 PM PDT 24
Finished Mar 12 01:41:36 PM PDT 24
Peak memory 254876 kb
Host smart-3e1a0667-8363-4079-86c3-6ec805fb7c12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36075
33649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.3607533649
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.2063226207
Short name T229
Test name
Test status
Simulation time 16666477646 ps
CPU time 802.44 seconds
Started Mar 12 01:40:58 PM PDT 24
Finished Mar 12 01:54:20 PM PDT 24
Peak memory 272512 kb
Host smart-2febef4a-0957-4bea-bca2-924b07baa1e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063226207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.2063226207
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.1054964209
Short name T652
Test name
Test status
Simulation time 30211292248 ps
CPU time 929.68 seconds
Started Mar 12 01:40:58 PM PDT 24
Finished Mar 12 01:56:28 PM PDT 24
Peak memory 264956 kb
Host smart-98d41df7-0293-43a4-a7bf-6bde630e4167
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054964209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1054964209
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.1417610184
Short name T305
Test name
Test status
Simulation time 5516681587 ps
CPU time 246.06 seconds
Started Mar 12 01:40:57 PM PDT 24
Finished Mar 12 01:45:03 PM PDT 24
Peak memory 247232 kb
Host smart-40103f90-0cff-4f6d-8a28-5776d046a661
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417610184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.1417610184
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.2368081978
Short name T46
Test name
Test status
Simulation time 4244244842 ps
CPU time 27.02 seconds
Started Mar 12 01:40:51 PM PDT 24
Finished Mar 12 01:41:19 PM PDT 24
Peak memory 248560 kb
Host smart-3d8c655b-5d7a-4152-9367-f9401fd73f54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23680
81978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.2368081978
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.1749164567
Short name T616
Test name
Test status
Simulation time 804337329 ps
CPU time 20.47 seconds
Started Mar 12 01:40:51 PM PDT 24
Finished Mar 12 01:41:12 PM PDT 24
Peak memory 255852 kb
Host smart-2800a04c-45a1-4cd1-8aa4-dc720aa6783c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17491
64567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.1749164567
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.4275868860
Short name T261
Test name
Test status
Simulation time 580573206 ps
CPU time 18.79 seconds
Started Mar 12 01:40:57 PM PDT 24
Finished Mar 12 01:41:17 PM PDT 24
Peak memory 255172 kb
Host smart-b1273dac-44ff-42a3-b368-9a37436f4e1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42758
68860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.4275868860
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.2299309580
Short name T626
Test name
Test status
Simulation time 1021496048 ps
CPU time 21.66 seconds
Started Mar 12 01:40:52 PM PDT 24
Finished Mar 12 01:41:13 PM PDT 24
Peak memory 256684 kb
Host smart-871a3978-42bc-4234-85ea-51b92a37e289
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22993
09580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.2299309580
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.1630055332
Short name T417
Test name
Test status
Simulation time 2390240605 ps
CPU time 24.07 seconds
Started Mar 12 01:40:57 PM PDT 24
Finished Mar 12 01:41:21 PM PDT 24
Peak memory 254296 kb
Host smart-44cd610f-f0f1-40a8-9bb6-3979c941f1f8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630055332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.1630055332
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.279886770
Short name T55
Test name
Test status
Simulation time 74533935180 ps
CPU time 8163.6 seconds
Started Mar 12 01:40:59 PM PDT 24
Finished Mar 12 03:57:03 PM PDT 24
Peak memory 391972 kb
Host smart-ffa07213-4465-44eb-9be7-8c11368da4c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279886770 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.279886770
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.1628712058
Short name T557
Test name
Test status
Simulation time 206546634793 ps
CPU time 1497.02 seconds
Started Mar 12 01:41:04 PM PDT 24
Finished Mar 12 02:06:02 PM PDT 24
Peak memory 282856 kb
Host smart-2f33cc0b-3ba9-4aa2-80b8-6e7269609873
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628712058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.1628712058
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.137432196
Short name T483
Test name
Test status
Simulation time 18385902812 ps
CPU time 126.46 seconds
Started Mar 12 01:40:57 PM PDT 24
Finished Mar 12 01:43:04 PM PDT 24
Peak memory 256236 kb
Host smart-2b17bf4f-163a-415e-9355-5535918dd2d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13743
2196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.137432196
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.345683906
Short name T386
Test name
Test status
Simulation time 888521571 ps
CPU time 12.87 seconds
Started Mar 12 01:40:57 PM PDT 24
Finished Mar 12 01:41:11 PM PDT 24
Peak memory 254812 kb
Host smart-7acbbd26-467b-4fa3-a139-069822cd9f3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34568
3906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.345683906
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.2549152734
Short name T442
Test name
Test status
Simulation time 42745892549 ps
CPU time 1150.24 seconds
Started Mar 12 01:41:05 PM PDT 24
Finished Mar 12 02:00:17 PM PDT 24
Peak memory 272504 kb
Host smart-7c2ce6b3-861f-4134-ab0a-e6d9f7b37dbf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549152734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.2549152734
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.83158981
Short name T560
Test name
Test status
Simulation time 8498933516 ps
CPU time 853.19 seconds
Started Mar 12 01:41:17 PM PDT 24
Finished Mar 12 01:55:30 PM PDT 24
Peak memory 272736 kb
Host smart-2c198c48-100b-4aed-a54d-d7041f6a5b39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83158981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.83158981
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.3982936259
Short name T318
Test name
Test status
Simulation time 1877267742 ps
CPU time 77.59 seconds
Started Mar 12 01:41:05 PM PDT 24
Finished Mar 12 01:42:24 PM PDT 24
Peak memory 246588 kb
Host smart-1fe1eb71-b212-442b-98d7-7eb398abd5bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982936259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.3982936259
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.975049723
Short name T666
Test name
Test status
Simulation time 1219637375 ps
CPU time 82.34 seconds
Started Mar 12 01:40:57 PM PDT 24
Finished Mar 12 01:42:20 PM PDT 24
Peak memory 256584 kb
Host smart-7fd27304-3637-4e47-bfb5-305237540ffa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97504
9723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.975049723
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.440793996
Short name T94
Test name
Test status
Simulation time 286744285 ps
CPU time 20.83 seconds
Started Mar 12 01:40:57 PM PDT 24
Finished Mar 12 01:41:18 PM PDT 24
Peak memory 248540 kb
Host smart-03c5fdd4-c854-4057-9540-529aeeef0297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44079
3996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.440793996
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.2537376283
Short name T458
Test name
Test status
Simulation time 125392508 ps
CPU time 9.1 seconds
Started Mar 12 01:41:08 PM PDT 24
Finished Mar 12 01:41:19 PM PDT 24
Peak memory 246644 kb
Host smart-3bb6b8f4-8aa9-4b62-8207-3913799109b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25373
76283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.2537376283
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.1321938427
Short name T641
Test name
Test status
Simulation time 207208468 ps
CPU time 8.92 seconds
Started Mar 12 01:40:57 PM PDT 24
Finished Mar 12 01:41:07 PM PDT 24
Peak memory 248544 kb
Host smart-42b5e46c-ed69-47db-9be2-cc9c4b0b140b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13219
38427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.1321938427
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.2332312853
Short name T373
Test name
Test status
Simulation time 14083527081 ps
CPU time 443.01 seconds
Started Mar 12 01:41:04 PM PDT 24
Finished Mar 12 01:48:29 PM PDT 24
Peak memory 256752 kb
Host smart-d83cfd0c-098a-498a-b8fb-3c569493a16a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332312853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.2332312853
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.591467634
Short name T592
Test name
Test status
Simulation time 35068485772 ps
CPU time 945.23 seconds
Started Mar 12 01:41:07 PM PDT 24
Finished Mar 12 01:56:54 PM PDT 24
Peak memory 288724 kb
Host smart-d7bfdd1a-62f8-4ab7-ac1f-8c07982a7f55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591467634 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.591467634
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.1189844998
Short name T474
Test name
Test status
Simulation time 72173561303 ps
CPU time 2153.39 seconds
Started Mar 12 01:41:05 PM PDT 24
Finished Mar 12 02:16:59 PM PDT 24
Peak memory 272268 kb
Host smart-e6124826-8d07-4eba-904d-a24744f5092d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189844998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.1189844998
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.3354501933
Short name T412
Test name
Test status
Simulation time 1105465375 ps
CPU time 66.94 seconds
Started Mar 12 01:41:05 PM PDT 24
Finished Mar 12 01:42:13 PM PDT 24
Peak memory 256108 kb
Host smart-49872969-114c-4aba-b507-4c2d0659a39c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33545
01933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.3354501933
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.222377943
Short name T537
Test name
Test status
Simulation time 788003074 ps
CPU time 44.54 seconds
Started Mar 12 01:41:09 PM PDT 24
Finished Mar 12 01:41:54 PM PDT 24
Peak memory 254420 kb
Host smart-45dbfb75-7ee7-43d6-891c-0165a4313328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22237
7943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.222377943
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.1934647052
Short name T324
Test name
Test status
Simulation time 494735491875 ps
CPU time 2870.2 seconds
Started Mar 12 01:41:06 PM PDT 24
Finished Mar 12 02:28:57 PM PDT 24
Peak memory 281720 kb
Host smart-17914629-f14d-4054-a6a0-fcbee52c397a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934647052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.1934647052
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.2010002511
Short name T498
Test name
Test status
Simulation time 32511426962 ps
CPU time 2054.6 seconds
Started Mar 12 01:41:11 PM PDT 24
Finished Mar 12 02:15:26 PM PDT 24
Peak memory 273144 kb
Host smart-e5611d47-1498-41ba-8a37-2099eee36503
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010002511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.2010002511
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.1351166047
Short name T621
Test name
Test status
Simulation time 112712263 ps
CPU time 11.39 seconds
Started Mar 12 01:41:03 PM PDT 24
Finished Mar 12 01:41:16 PM PDT 24
Peak memory 248556 kb
Host smart-d86c0569-4513-4b93-98f4-574ecda4e82c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13511
66047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.1351166047
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.3482798210
Short name T503
Test name
Test status
Simulation time 439180234 ps
CPU time 32.01 seconds
Started Mar 12 01:41:11 PM PDT 24
Finished Mar 12 01:41:43 PM PDT 24
Peak memory 253260 kb
Host smart-d1b4f002-f0c3-4aba-b5f5-9056db5300b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34827
98210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3482798210
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.3870139628
Short name T427
Test name
Test status
Simulation time 163306431 ps
CPU time 13.98 seconds
Started Mar 12 01:41:05 PM PDT 24
Finished Mar 12 01:41:21 PM PDT 24
Peak memory 252288 kb
Host smart-b94e0872-f737-45af-8413-2951c7e572bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38701
39628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.3870139628
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.3183972472
Short name T590
Test name
Test status
Simulation time 164031128 ps
CPU time 14.82 seconds
Started Mar 12 01:41:08 PM PDT 24
Finished Mar 12 01:41:25 PM PDT 24
Peak memory 248532 kb
Host smart-a843524b-08f3-43f0-9174-78d38f8308b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31839
72472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.3183972472
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.3733265113
Short name T421
Test name
Test status
Simulation time 121108425200 ps
CPU time 1955.76 seconds
Started Mar 12 01:41:11 PM PDT 24
Finished Mar 12 02:13:47 PM PDT 24
Peak memory 273108 kb
Host smart-79739b46-1fca-4c72-9bd5-dba9b73e3216
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733265113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.3733265113
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.922789032
Short name T257
Test name
Test status
Simulation time 59201520286 ps
CPU time 3997.25 seconds
Started Mar 12 01:41:12 PM PDT 24
Finished Mar 12 02:47:50 PM PDT 24
Peak memory 306036 kb
Host smart-5a1b7706-05b1-469e-99e1-d6d3f40fe283
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922789032 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.922789032
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.136569332
Short name T96
Test name
Test status
Simulation time 36643844466 ps
CPU time 958.65 seconds
Started Mar 12 01:41:11 PM PDT 24
Finished Mar 12 01:57:10 PM PDT 24
Peak memory 272248 kb
Host smart-a7b90d3a-1b7f-4917-aab2-6ba067ef9362
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136569332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.136569332
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.2271204031
Short name T456
Test name
Test status
Simulation time 3998918065 ps
CPU time 102.16 seconds
Started Mar 12 01:41:12 PM PDT 24
Finished Mar 12 01:42:54 PM PDT 24
Peak memory 256588 kb
Host smart-78780120-cd5a-4018-9226-9fbe83e4a935
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22712
04031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.2271204031
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1745941337
Short name T358
Test name
Test status
Simulation time 1741648541 ps
CPU time 33.23 seconds
Started Mar 12 01:41:12 PM PDT 24
Finished Mar 12 01:41:45 PM PDT 24
Peak memory 254976 kb
Host smart-6fba5312-d392-4f6a-9cac-714413cb71bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17459
41337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1745941337
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.2821896851
Short name T29
Test name
Test status
Simulation time 273113827211 ps
CPU time 1589.79 seconds
Started Mar 12 01:41:17 PM PDT 24
Finished Mar 12 02:07:47 PM PDT 24
Peak memory 272964 kb
Host smart-07f085ef-6af7-4e9c-a069-2c586a9635c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821896851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.2821896851
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.4075971279
Short name T307
Test name
Test status
Simulation time 8579799115 ps
CPU time 337.06 seconds
Started Mar 12 01:41:17 PM PDT 24
Finished Mar 12 01:46:55 PM PDT 24
Peak memory 247464 kb
Host smart-d749bc04-4ffe-496c-899f-8ae678f14fdf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075971279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.4075971279
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.1310789160
Short name T613
Test name
Test status
Simulation time 405360473 ps
CPU time 15.92 seconds
Started Mar 12 01:41:16 PM PDT 24
Finished Mar 12 01:41:32 PM PDT 24
Peak memory 248536 kb
Host smart-541e7d6b-8507-4c5c-920e-8c80b68d826d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13107
89160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.1310789160
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.3444514874
Short name T368
Test name
Test status
Simulation time 6577686396 ps
CPU time 37.37 seconds
Started Mar 12 01:41:13 PM PDT 24
Finished Mar 12 01:41:51 PM PDT 24
Peak memory 247748 kb
Host smart-1b6fb2e4-ac17-4e57-b109-b319c6a69073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34445
14874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.3444514874
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.3444830102
Short name T657
Test name
Test status
Simulation time 356944944 ps
CPU time 20.99 seconds
Started Mar 12 01:41:12 PM PDT 24
Finished Mar 12 01:41:33 PM PDT 24
Peak memory 254880 kb
Host smart-1577d85b-d050-406e-8c8b-04674780444d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34448
30102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.3444830102
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.979731766
Short name T350
Test name
Test status
Simulation time 358950412 ps
CPU time 32.58 seconds
Started Mar 12 01:41:16 PM PDT 24
Finished Mar 12 01:41:49 PM PDT 24
Peak memory 248548 kb
Host smart-634d0266-4d43-456a-a770-4d79ae14f42e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97973
1766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.979731766
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.2985139117
Short name T399
Test name
Test status
Simulation time 553091635261 ps
CPU time 2868.63 seconds
Started Mar 12 01:41:16 PM PDT 24
Finished Mar 12 02:29:05 PM PDT 24
Peak memory 281344 kb
Host smart-00c608f2-f9c6-4cff-bbb3-a6805c5d74f2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985139117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.2985139117
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.2891906987
Short name T98
Test name
Test status
Simulation time 14807324923 ps
CPU time 1738.81 seconds
Started Mar 12 01:41:17 PM PDT 24
Finished Mar 12 02:10:16 PM PDT 24
Peak memory 305380 kb
Host smart-731fcde7-35f7-4b13-ae9b-e5561f9aeff5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891906987 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.2891906987
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.3431365240
Short name T93
Test name
Test status
Simulation time 41187043594 ps
CPU time 2665.86 seconds
Started Mar 12 01:41:21 PM PDT 24
Finished Mar 12 02:25:48 PM PDT 24
Peak memory 289396 kb
Host smart-72404f0a-5979-4e16-afdd-c3aef5f0fe1f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431365240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.3431365240
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.3069852433
Short name T349
Test name
Test status
Simulation time 3067435193 ps
CPU time 193.1 seconds
Started Mar 12 01:41:19 PM PDT 24
Finished Mar 12 01:44:32 PM PDT 24
Peak memory 255872 kb
Host smart-25f4521e-c9c8-4427-bab2-b681a372bec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30698
52433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.3069852433
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.1070502409
Short name T704
Test name
Test status
Simulation time 1637877270 ps
CPU time 23.14 seconds
Started Mar 12 01:41:17 PM PDT 24
Finished Mar 12 01:41:40 PM PDT 24
Peak memory 254180 kb
Host smart-ee4ff8cd-9139-4a08-aa38-8cc24b2bef84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10705
02409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.1070502409
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.3028285842
Short name T326
Test name
Test status
Simulation time 242411295033 ps
CPU time 2379.79 seconds
Started Mar 12 01:41:18 PM PDT 24
Finished Mar 12 02:20:59 PM PDT 24
Peak memory 282188 kb
Host smart-35237052-9736-4fe8-82cc-591b6a2fb618
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028285842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.3028285842
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.1019770062
Short name T384
Test name
Test status
Simulation time 50001229641 ps
CPU time 1737.26 seconds
Started Mar 12 01:41:19 PM PDT 24
Finished Mar 12 02:10:16 PM PDT 24
Peak memory 273164 kb
Host smart-d8dda36e-5496-4bdc-ade2-de997f1f1c91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019770062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.1019770062
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.3643591722
Short name T315
Test name
Test status
Simulation time 52969675042 ps
CPU time 270.24 seconds
Started Mar 12 01:41:18 PM PDT 24
Finished Mar 12 01:45:48 PM PDT 24
Peak memory 246372 kb
Host smart-d3b381c4-06b1-409d-a3a4-c7bd5f25b448
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643591722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.3643591722
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.2905046059
Short name T362
Test name
Test status
Simulation time 261851974 ps
CPU time 17.19 seconds
Started Mar 12 01:41:21 PM PDT 24
Finished Mar 12 01:41:39 PM PDT 24
Peak memory 248512 kb
Host smart-9020c730-efb5-4a3d-af8c-ac781b28cce9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29050
46059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.2905046059
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.2582025160
Short name T700
Test name
Test status
Simulation time 4859363141 ps
CPU time 49.61 seconds
Started Mar 12 01:41:17 PM PDT 24
Finished Mar 12 01:42:07 PM PDT 24
Peak memory 255260 kb
Host smart-26c8937d-d775-497a-b00c-511501e5b9e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25820
25160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.2582025160
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.3438349524
Short name T486
Test name
Test status
Simulation time 1148520160 ps
CPU time 20.8 seconds
Started Mar 12 01:41:18 PM PDT 24
Finished Mar 12 01:41:39 PM PDT 24
Peak memory 246920 kb
Host smart-b6285990-b758-4f2b-9b3a-d3fb7f896be6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34383
49524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3438349524
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.16070431
Short name T466
Test name
Test status
Simulation time 257783693 ps
CPU time 9.05 seconds
Started Mar 12 01:41:19 PM PDT 24
Finished Mar 12 01:41:29 PM PDT 24
Peak memory 248544 kb
Host smart-bc9a0940-abdb-4d8a-8857-a33f8d375465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16070
431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.16070431
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.1040035023
Short name T58
Test name
Test status
Simulation time 125849978322 ps
CPU time 2839.8 seconds
Started Mar 12 01:41:18 PM PDT 24
Finished Mar 12 02:28:38 PM PDT 24
Peak memory 297476 kb
Host smart-660965bc-d20d-4cdc-a1b1-5d0451278cee
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040035023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.1040035023
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.2856364829
Short name T108
Test name
Test status
Simulation time 36610706399 ps
CPU time 1138.4 seconds
Started Mar 12 01:41:26 PM PDT 24
Finished Mar 12 02:00:25 PM PDT 24
Peak memory 283080 kb
Host smart-f352c46f-27bb-4b89-9ba1-275ecde6c16e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856364829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.2856364829
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.2367558289
Short name T242
Test name
Test status
Simulation time 16848887143 ps
CPU time 241.73 seconds
Started Mar 12 01:41:25 PM PDT 24
Finished Mar 12 01:45:27 PM PDT 24
Peak memory 250620 kb
Host smart-40755c35-bf88-458c-a4ac-be6fff8760ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23675
58289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2367558289
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.500656549
Short name T496
Test name
Test status
Simulation time 1473917558 ps
CPU time 22.89 seconds
Started Mar 12 01:41:24 PM PDT 24
Finished Mar 12 01:41:47 PM PDT 24
Peak memory 254816 kb
Host smart-17311b24-bee4-4e8e-ad94-c9574b9c2c75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50065
6549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.500656549
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.2047329762
Short name T416
Test name
Test status
Simulation time 31894589936 ps
CPU time 1019.85 seconds
Started Mar 12 01:41:23 PM PDT 24
Finished Mar 12 01:58:24 PM PDT 24
Peak memory 273064 kb
Host smart-7253cd57-cefb-43ca-8599-ce52be1aba6c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047329762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.2047329762
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.704467057
Short name T200
Test name
Test status
Simulation time 39829903743 ps
CPU time 1308.34 seconds
Started Mar 12 01:41:25 PM PDT 24
Finished Mar 12 02:03:13 PM PDT 24
Peak memory 281336 kb
Host smart-2e26aab8-0613-4ffb-a93d-474a8262c4e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704467057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.704467057
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.2746794945
Short name T295
Test name
Test status
Simulation time 16908119099 ps
CPU time 483.08 seconds
Started Mar 12 01:41:25 PM PDT 24
Finished Mar 12 01:49:28 PM PDT 24
Peak memory 247380 kb
Host smart-7173a9c7-26af-4144-827f-cf4f1a790ea0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746794945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.2746794945
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.1799074666
Short name T407
Test name
Test status
Simulation time 768095334 ps
CPU time 38.71 seconds
Started Mar 12 01:41:25 PM PDT 24
Finished Mar 12 01:42:04 PM PDT 24
Peak memory 255376 kb
Host smart-eeec713c-1a2a-40fe-8637-dd2540e1ab61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17990
74666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.1799074666
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.3298892147
Short name T90
Test name
Test status
Simulation time 825125159 ps
CPU time 38.78 seconds
Started Mar 12 01:41:25 PM PDT 24
Finished Mar 12 01:42:03 PM PDT 24
Peak memory 246680 kb
Host smart-aefcbdec-a36a-4640-a5ce-ee9e68046c9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32988
92147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.3298892147
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.1974554370
Short name T81
Test name
Test status
Simulation time 111131797 ps
CPU time 14.82 seconds
Started Mar 12 01:41:28 PM PDT 24
Finished Mar 12 01:41:43 PM PDT 24
Peak memory 246816 kb
Host smart-fe39cf1a-36cf-4e0a-a54c-1f395f5f0b9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19745
54370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.1974554370
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.4259142260
Short name T606
Test name
Test status
Simulation time 568768403 ps
CPU time 15.94 seconds
Started Mar 12 01:41:27 PM PDT 24
Finished Mar 12 01:41:43 PM PDT 24
Peak memory 248536 kb
Host smart-a7dc530f-6c1b-4bf1-a263-f3acce67e662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42591
42260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.4259142260
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.87263084
Short name T670
Test name
Test status
Simulation time 21859070754 ps
CPU time 460.69 seconds
Started Mar 12 01:41:25 PM PDT 24
Finished Mar 12 01:49:06 PM PDT 24
Peak memory 268604 kb
Host smart-9265a5ba-b2da-43eb-9694-5d2ca4ad8b98
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87263084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_hand
ler_stress_all.87263084
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.4175024438
Short name T211
Test name
Test status
Simulation time 17310328 ps
CPU time 2.86 seconds
Started Mar 12 01:38:54 PM PDT 24
Finished Mar 12 01:38:57 PM PDT 24
Peak memory 248712 kb
Host smart-1e2c1791-e058-4a92-a4c4-7fb688cea880
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4175024438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.4175024438
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.975816695
Short name T415
Test name
Test status
Simulation time 5313340654 ps
CPU time 632.41 seconds
Started Mar 12 01:39:14 PM PDT 24
Finished Mar 12 01:49:48 PM PDT 24
Peak memory 264980 kb
Host smart-05233e90-4b64-4b5c-a3a3-7489edb91dd7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975816695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.975816695
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.2659621455
Short name T403
Test name
Test status
Simulation time 1089461770 ps
CPU time 25.81 seconds
Started Mar 12 01:39:16 PM PDT 24
Finished Mar 12 01:39:47 PM PDT 24
Peak memory 240352 kb
Host smart-d165d286-0e22-46ff-9b26-99d777954caf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2659621455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.2659621455
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.3602358844
Short name T231
Test name
Test status
Simulation time 14169613047 ps
CPU time 245.17 seconds
Started Mar 12 01:39:04 PM PDT 24
Finished Mar 12 01:43:09 PM PDT 24
Peak memory 256320 kb
Host smart-8ebe4186-6b63-4ae7-aeb0-cedde8485296
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36023
58844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.3602358844
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.3314000050
Short name T31
Test name
Test status
Simulation time 1909728870 ps
CPU time 26.04 seconds
Started Mar 12 01:39:09 PM PDT 24
Finished Mar 12 01:39:36 PM PDT 24
Peak memory 254748 kb
Host smart-ceffe7e4-538c-4333-92bb-8d8c102a160c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33140
00050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.3314000050
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.863357335
Short name T187
Test name
Test status
Simulation time 129038819153 ps
CPU time 1758.47 seconds
Started Mar 12 01:39:14 PM PDT 24
Finished Mar 12 02:08:33 PM PDT 24
Peak memory 271460 kb
Host smart-35701009-3d0b-49b7-b518-3341ed9897b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863357335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.863357335
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.3845118037
Short name T316
Test name
Test status
Simulation time 1535868525 ps
CPU time 64.17 seconds
Started Mar 12 01:39:12 PM PDT 24
Finished Mar 12 01:40:16 PM PDT 24
Peak memory 246520 kb
Host smart-3470961b-f639-4c0c-ad70-511812168ce0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845118037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.3845118037
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.1693437393
Short name T445
Test name
Test status
Simulation time 1417456740 ps
CPU time 33.39 seconds
Started Mar 12 01:39:17 PM PDT 24
Finished Mar 12 01:39:55 PM PDT 24
Peak memory 248548 kb
Host smart-cb58dffb-4373-4c20-b70e-fcac909aafac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16934
37393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.1693437393
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.1292246927
Short name T106
Test name
Test status
Simulation time 2295006959 ps
CPU time 62.54 seconds
Started Mar 12 01:39:15 PM PDT 24
Finished Mar 12 01:40:22 PM PDT 24
Peak memory 248060 kb
Host smart-db88f2c4-59ca-4bfc-8152-a453e9831c32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12922
46927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.1292246927
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.3139624662
Short name T32
Test name
Test status
Simulation time 668632433 ps
CPU time 32.64 seconds
Started Mar 12 01:39:19 PM PDT 24
Finished Mar 12 01:39:55 PM PDT 24
Peak memory 274728 kb
Host smart-c35bf4ab-117e-49df-acdb-b5c5c43b61e0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3139624662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.3139624662
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.3655039672
Short name T533
Test name
Test status
Simulation time 751701635 ps
CPU time 44.49 seconds
Started Mar 12 01:38:52 PM PDT 24
Finished Mar 12 01:39:37 PM PDT 24
Peak memory 248456 kb
Host smart-f2627030-1d1d-471e-ac5c-9de202be5ed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36550
39672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.3655039672
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.160243610
Short name T410
Test name
Test status
Simulation time 143411210 ps
CPU time 5.21 seconds
Started Mar 12 01:39:13 PM PDT 24
Finished Mar 12 01:39:19 PM PDT 24
Peak memory 240320 kb
Host smart-e8a07a35-0831-45d8-bb0b-dd316c4f1cc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16024
3610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.160243610
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.3825797050
Short name T266
Test name
Test status
Simulation time 243608921729 ps
CPU time 1586.65 seconds
Started Mar 12 01:39:00 PM PDT 24
Finished Mar 12 02:05:26 PM PDT 24
Peak memory 289540 kb
Host smart-a5a6b047-b4cd-4bee-8672-36daa7b18a51
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825797050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.3825797050
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.3511909114
Short name T545
Test name
Test status
Simulation time 25641665295 ps
CPU time 587.34 seconds
Started Mar 12 01:41:33 PM PDT 24
Finished Mar 12 01:51:21 PM PDT 24
Peak memory 264968 kb
Host smart-0d596602-56fa-40ca-8232-1f62635f7147
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511909114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.3511909114
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.348412643
Short name T244
Test name
Test status
Simulation time 1080397468 ps
CPU time 25.66 seconds
Started Mar 12 01:41:31 PM PDT 24
Finished Mar 12 01:41:57 PM PDT 24
Peak memory 256180 kb
Host smart-25563cb3-f4af-48b3-912d-93b8e85e5a8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34841
2643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.348412643
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.1116630022
Short name T523
Test name
Test status
Simulation time 35539567 ps
CPU time 5.42 seconds
Started Mar 12 01:41:31 PM PDT 24
Finished Mar 12 01:41:37 PM PDT 24
Peak memory 250368 kb
Host smart-99333cfa-fee1-4b21-873a-233f4076bf8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11166
30022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.1116630022
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.4198112461
Short name T299
Test name
Test status
Simulation time 19176522650 ps
CPU time 1264.56 seconds
Started Mar 12 01:41:32 PM PDT 24
Finished Mar 12 02:02:37 PM PDT 24
Peak memory 264976 kb
Host smart-9e84850b-aaea-4e11-8355-5553f0b26d2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198112461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.4198112461
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.733994144
Short name T646
Test name
Test status
Simulation time 50988135332 ps
CPU time 2025.21 seconds
Started Mar 12 01:41:34 PM PDT 24
Finished Mar 12 02:15:20 PM PDT 24
Peak memory 283216 kb
Host smart-1c625f33-a3d4-4d35-92e8-0001e4972f68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733994144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.733994144
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.1715371846
Short name T705
Test name
Test status
Simulation time 25779434108 ps
CPU time 509.14 seconds
Started Mar 12 01:41:31 PM PDT 24
Finished Mar 12 01:50:01 PM PDT 24
Peak memory 247240 kb
Host smart-fc60fcbe-8c57-47e4-950f-853c4219a491
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715371846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.1715371846
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.555338822
Short name T451
Test name
Test status
Simulation time 1075855111 ps
CPU time 21.25 seconds
Started Mar 12 01:41:27 PM PDT 24
Finished Mar 12 01:41:48 PM PDT 24
Peak memory 248544 kb
Host smart-efce81ff-c51e-4969-8147-a18d6398753d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55533
8822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.555338822
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.1144896842
Short name T558
Test name
Test status
Simulation time 1141923512 ps
CPU time 9.71 seconds
Started Mar 12 01:41:32 PM PDT 24
Finished Mar 12 01:41:42 PM PDT 24
Peak memory 246500 kb
Host smart-4ba64822-1b81-4165-8f7b-ea8b2db3af83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11448
96842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.1144896842
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.39480492
Short name T72
Test name
Test status
Simulation time 1043951550 ps
CPU time 61.97 seconds
Started Mar 12 01:41:31 PM PDT 24
Finished Mar 12 01:42:33 PM PDT 24
Peak memory 254876 kb
Host smart-3c9adc53-9cd4-46ad-9d45-fbff1ec8b474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39480
492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.39480492
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.3873998870
Short name T398
Test name
Test status
Simulation time 702179108 ps
CPU time 18.29 seconds
Started Mar 12 01:41:27 PM PDT 24
Finished Mar 12 01:41:45 PM PDT 24
Peak memory 248532 kb
Host smart-b5f9faf4-ddda-47f1-93c7-20bf908ec3ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38739
98870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.3873998870
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.3304919996
Short name T84
Test name
Test status
Simulation time 14968031151 ps
CPU time 1362.34 seconds
Started Mar 12 01:41:39 PM PDT 24
Finished Mar 12 02:04:24 PM PDT 24
Peak memory 289380 kb
Host smart-406aa43c-19d6-4c4e-857a-b0840615a163
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304919996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.3304919996
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.2757640419
Short name T457
Test name
Test status
Simulation time 4492984064 ps
CPU time 112.45 seconds
Started Mar 12 01:41:39 PM PDT 24
Finished Mar 12 01:43:34 PM PDT 24
Peak memory 256728 kb
Host smart-623f195f-8ead-44e0-a783-a7a83d051dd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27576
40419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.2757640419
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.2810354103
Short name T383
Test name
Test status
Simulation time 274650447 ps
CPU time 26.4 seconds
Started Mar 12 01:41:39 PM PDT 24
Finished Mar 12 01:42:08 PM PDT 24
Peak memory 247088 kb
Host smart-e1f9c812-083d-4c84-99b5-c6372fa6ec66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28103
54103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.2810354103
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.2353090396
Short name T365
Test name
Test status
Simulation time 62276113828 ps
CPU time 850.74 seconds
Started Mar 12 01:41:39 PM PDT 24
Finished Mar 12 01:55:51 PM PDT 24
Peak memory 272172 kb
Host smart-4145f8c9-713a-4446-a55b-dfb74453a266
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353090396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.2353090396
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.3898251380
Short name T296
Test name
Test status
Simulation time 51535803177 ps
CPU time 505.3 seconds
Started Mar 12 01:41:39 PM PDT 24
Finished Mar 12 01:50:07 PM PDT 24
Peak memory 248560 kb
Host smart-f912486b-8073-4f70-a87e-916fec75da69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898251380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.3898251380
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.1382802041
Short name T564
Test name
Test status
Simulation time 1990725853 ps
CPU time 26.67 seconds
Started Mar 12 01:41:39 PM PDT 24
Finished Mar 12 01:42:09 PM PDT 24
Peak memory 254804 kb
Host smart-4ac28e42-26f7-438d-a2f1-11d334910622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13828
02041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.1382802041
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.3815293529
Short name T220
Test name
Test status
Simulation time 521811535 ps
CPU time 12.9 seconds
Started Mar 12 01:41:41 PM PDT 24
Finished Mar 12 01:41:55 PM PDT 24
Peak memory 246800 kb
Host smart-dea94e3a-d079-46ea-9e49-898c9822e7a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38152
93529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.3815293529
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.706208499
Short name T432
Test name
Test status
Simulation time 927704181 ps
CPU time 54.5 seconds
Started Mar 12 01:41:43 PM PDT 24
Finished Mar 12 01:42:38 PM PDT 24
Peak memory 248552 kb
Host smart-3f251d47-c5f3-4fbe-8d3d-6de7c2afdc9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70620
8499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.706208499
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.3466856431
Short name T112
Test name
Test status
Simulation time 617826108 ps
CPU time 32.85 seconds
Started Mar 12 01:41:38 PM PDT 24
Finished Mar 12 01:42:14 PM PDT 24
Peak memory 248540 kb
Host smart-1f475386-e24f-45d3-acce-f2a58058a050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34668
56431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.3466856431
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.3604606253
Short name T255
Test name
Test status
Simulation time 287910788924 ps
CPU time 3019.07 seconds
Started Mar 12 01:41:41 PM PDT 24
Finished Mar 12 02:32:01 PM PDT 24
Peak memory 305196 kb
Host smart-303e4cca-4545-4aeb-8f2e-ddefdcf258f5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604606253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.3604606253
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.3416839982
Short name T578
Test name
Test status
Simulation time 9082982112 ps
CPU time 1084.33 seconds
Started Mar 12 01:41:39 PM PDT 24
Finished Mar 12 01:59:46 PM PDT 24
Peak memory 286856 kb
Host smart-286b0b08-b2b8-4cb1-b978-7a26029ff696
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416839982 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.3416839982
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.1845683643
Short name T536
Test name
Test status
Simulation time 41210150386 ps
CPU time 2724.68 seconds
Started Mar 12 01:41:45 PM PDT 24
Finished Mar 12 02:27:12 PM PDT 24
Peak memory 288456 kb
Host smart-8eb4d623-c80d-440c-8d84-8517f3fd5e9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845683643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.1845683643
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.1818568376
Short name T655
Test name
Test status
Simulation time 16981887651 ps
CPU time 236.84 seconds
Started Mar 12 01:41:46 PM PDT 24
Finished Mar 12 01:45:44 PM PDT 24
Peak memory 255908 kb
Host smart-bd011080-42a9-48f5-bd8b-75e07696b80e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18185
68376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.1818568376
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.3336562533
Short name T694
Test name
Test status
Simulation time 735810361 ps
CPU time 50.32 seconds
Started Mar 12 01:41:47 PM PDT 24
Finished Mar 12 01:42:38 PM PDT 24
Peak memory 254540 kb
Host smart-f23de778-3a53-417c-8fd1-7397d47041fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33365
62533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.3336562533
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.2633364718
Short name T667
Test name
Test status
Simulation time 81531490801 ps
CPU time 1423.56 seconds
Started Mar 12 01:41:44 PM PDT 24
Finished Mar 12 02:05:28 PM PDT 24
Peak memory 288840 kb
Host smart-dcae7110-42f7-44c3-b57c-0b023f0e9d48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633364718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.2633364718
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.1108364030
Short name T360
Test name
Test status
Simulation time 21097714176 ps
CPU time 674.9 seconds
Started Mar 12 01:41:48 PM PDT 24
Finished Mar 12 01:53:03 PM PDT 24
Peak memory 272812 kb
Host smart-b03810f4-569a-4fd8-abfc-7aa1e5811864
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108364030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.1108364030
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.731262031
Short name T226
Test name
Test status
Simulation time 5387442113 ps
CPU time 221.28 seconds
Started Mar 12 01:41:48 PM PDT 24
Finished Mar 12 01:45:30 PM PDT 24
Peak memory 247260 kb
Host smart-f7169dff-f204-4b10-8e8b-c3d125dffb9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731262031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.731262031
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.989412822
Short name T607
Test name
Test status
Simulation time 707442684 ps
CPU time 44.39 seconds
Started Mar 12 01:41:38 PM PDT 24
Finished Mar 12 01:42:26 PM PDT 24
Peak memory 255492 kb
Host smart-50b5609a-db49-4a26-9634-8e952c74e53e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98941
2822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.989412822
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.568475613
Short name T15
Test name
Test status
Simulation time 516292463 ps
CPU time 32.75 seconds
Started Mar 12 01:41:40 PM PDT 24
Finished Mar 12 01:42:15 PM PDT 24
Peak memory 255284 kb
Host smart-80eb910c-929a-443a-b34a-6dc9fec4e3fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56847
5613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.568475613
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.3658554937
Short name T17
Test name
Test status
Simulation time 65780529 ps
CPU time 5.33 seconds
Started Mar 12 01:41:47 PM PDT 24
Finished Mar 12 01:41:53 PM PDT 24
Peak memory 238428 kb
Host smart-4cf7967f-73ba-47c0-badd-cf56578bedfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36585
54937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.3658554937
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.1648495833
Short name T514
Test name
Test status
Simulation time 872481566 ps
CPU time 31.46 seconds
Started Mar 12 01:41:38 PM PDT 24
Finished Mar 12 01:42:10 PM PDT 24
Peak memory 248548 kb
Host smart-c1f63441-4c73-4717-a4e1-c2814b90a309
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16484
95833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.1648495833
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.1914862172
Short name T686
Test name
Test status
Simulation time 49336367256 ps
CPU time 283.58 seconds
Started Mar 12 01:41:46 PM PDT 24
Finished Mar 12 01:46:30 PM PDT 24
Peak memory 255948 kb
Host smart-97cd1bec-7d4c-490a-b46a-502a27ef383c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914862172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.1914862172
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.702549591
Short name T91
Test name
Test status
Simulation time 23507348374 ps
CPU time 1484.55 seconds
Started Mar 12 01:41:54 PM PDT 24
Finished Mar 12 02:06:39 PM PDT 24
Peak memory 289312 kb
Host smart-03c159de-fa44-4203-9381-28d0bf8f74d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702549591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.702549591
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.1278134320
Short name T554
Test name
Test status
Simulation time 14988352803 ps
CPU time 232.29 seconds
Started Mar 12 01:41:55 PM PDT 24
Finished Mar 12 01:45:47 PM PDT 24
Peak memory 249564 kb
Host smart-584050aa-74a5-4474-b596-c0d78922f18b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12781
34320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.1278134320
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.3687232298
Short name T223
Test name
Test status
Simulation time 412290182 ps
CPU time 25.48 seconds
Started Mar 12 01:41:53 PM PDT 24
Finished Mar 12 01:42:19 PM PDT 24
Peak memory 254836 kb
Host smart-ab07bc67-4d6a-4730-a939-bda2b2c58edf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36872
32298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.3687232298
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.2712015190
Short name T319
Test name
Test status
Simulation time 147886164903 ps
CPU time 2425.15 seconds
Started Mar 12 01:41:55 PM PDT 24
Finished Mar 12 02:22:21 PM PDT 24
Peak memory 282804 kb
Host smart-ee9a02aa-0f65-45b5-8612-abac73b88157
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712015190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.2712015190
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.2315610721
Short name T639
Test name
Test status
Simulation time 129271298250 ps
CPU time 1248.11 seconds
Started Mar 12 01:41:54 PM PDT 24
Finished Mar 12 02:02:43 PM PDT 24
Peak memory 288932 kb
Host smart-f02faa67-7d24-418e-adda-65f1c6308130
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315610721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.2315610721
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.3308658673
Short name T298
Test name
Test status
Simulation time 9168190308 ps
CPU time 305.14 seconds
Started Mar 12 01:41:53 PM PDT 24
Finished Mar 12 01:46:58 PM PDT 24
Peak memory 247472 kb
Host smart-b01065f2-2fd8-46a0-892f-c6b09f490475
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308658673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.3308658673
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.1623114110
Short name T219
Test name
Test status
Simulation time 843215697 ps
CPU time 17.44 seconds
Started Mar 12 01:41:55 PM PDT 24
Finished Mar 12 01:42:12 PM PDT 24
Peak memory 248520 kb
Host smart-5afadd82-511c-438a-8a7a-630bc92fa2c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16231
14110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.1623114110
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.114516230
Short name T618
Test name
Test status
Simulation time 557023330 ps
CPU time 9.77 seconds
Started Mar 12 01:41:54 PM PDT 24
Finished Mar 12 01:42:03 PM PDT 24
Peak memory 248152 kb
Host smart-454df83e-5f59-46b0-8c3c-0e8b599d2f0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11451
6230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.114516230
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.188911931
Short name T232
Test name
Test status
Simulation time 188054243 ps
CPU time 22.7 seconds
Started Mar 12 01:41:53 PM PDT 24
Finished Mar 12 01:42:16 PM PDT 24
Peak memory 248560 kb
Host smart-204e8660-7d54-4746-8c58-96c1ea024397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18891
1931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.188911931
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.4209484326
Short name T601
Test name
Test status
Simulation time 629459124 ps
CPU time 44.06 seconds
Started Mar 12 01:41:46 PM PDT 24
Finished Mar 12 01:42:30 PM PDT 24
Peak memory 248504 kb
Host smart-8d6fab4c-ca99-40ac-9ef1-ca42a0f03246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42094
84326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.4209484326
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.961538591
Short name T196
Test name
Test status
Simulation time 35991145867 ps
CPU time 2358.68 seconds
Started Mar 12 01:42:02 PM PDT 24
Finished Mar 12 02:21:21 PM PDT 24
Peak memory 289520 kb
Host smart-1e354c48-f28b-4acb-92ab-a04ac221bec2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961538591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_han
dler_stress_all.961538591
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.3685227524
Short name T42
Test name
Test status
Simulation time 235710361531 ps
CPU time 5014.73 seconds
Started Mar 12 01:42:04 PM PDT 24
Finished Mar 12 03:05:39 PM PDT 24
Peak memory 305480 kb
Host smart-08927c38-f2e2-45a4-9dcc-78e736dd3668
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685227524 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.3685227524
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.1310801817
Short name T396
Test name
Test status
Simulation time 104670470950 ps
CPU time 2409.71 seconds
Started Mar 12 01:42:12 PM PDT 24
Finished Mar 12 02:22:22 PM PDT 24
Peak memory 288736 kb
Host smart-7d3de4d4-d81a-429a-a358-f132c8abeaee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310801817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.1310801817
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.1784328812
Short name T659
Test name
Test status
Simulation time 6836787953 ps
CPU time 214.79 seconds
Started Mar 12 01:42:04 PM PDT 24
Finished Mar 12 01:45:38 PM PDT 24
Peak memory 256612 kb
Host smart-81e999d7-13a0-4d05-bf25-fc2edfb1d0bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17843
28812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.1784328812
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.1210568327
Short name T519
Test name
Test status
Simulation time 681644369 ps
CPU time 43.45 seconds
Started Mar 12 01:42:01 PM PDT 24
Finished Mar 12 01:42:45 PM PDT 24
Peak memory 254084 kb
Host smart-f0d8e34e-a151-4748-ae86-9e32c7e65d4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12105
68327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.1210568327
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.4147697422
Short name T433
Test name
Test status
Simulation time 19669720556 ps
CPU time 1539.91 seconds
Started Mar 12 01:42:10 PM PDT 24
Finished Mar 12 02:07:50 PM PDT 24
Peak memory 288828 kb
Host smart-6202e247-be47-4b0f-8701-0c8ed5ef6042
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147697422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.4147697422
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.1604812353
Short name T439
Test name
Test status
Simulation time 94119188281 ps
CPU time 1665.58 seconds
Started Mar 12 01:42:10 PM PDT 24
Finished Mar 12 02:09:56 PM PDT 24
Peak memory 273012 kb
Host smart-ecdc5827-98b9-4043-b5bb-6bba2e32cf75
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604812353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.1604812353
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.1918033287
Short name T663
Test name
Test status
Simulation time 4958898713 ps
CPU time 216.78 seconds
Started Mar 12 01:42:11 PM PDT 24
Finished Mar 12 01:45:48 PM PDT 24
Peak memory 247468 kb
Host smart-f021f099-3a35-461a-9ea4-bd45346a4135
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918033287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.1918033287
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.1662842101
Short name T571
Test name
Test status
Simulation time 1942312436 ps
CPU time 61.57 seconds
Started Mar 12 01:42:04 PM PDT 24
Finished Mar 12 01:43:06 PM PDT 24
Peak memory 248596 kb
Host smart-a4bd3a39-de34-4fb7-ab1b-dea02f872ca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16628
42101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.1662842101
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.3773486028
Short name T45
Test name
Test status
Simulation time 6572082457 ps
CPU time 52.17 seconds
Started Mar 12 01:42:02 PM PDT 24
Finished Mar 12 01:42:55 PM PDT 24
Peak memory 254880 kb
Host smart-26317852-0fe0-4464-826e-ceae95652e21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37734
86028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.3773486028
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.2743700015
Short name T453
Test name
Test status
Simulation time 4101329886 ps
CPU time 47.12 seconds
Started Mar 12 01:42:01 PM PDT 24
Finished Mar 12 01:42:48 PM PDT 24
Peak memory 254968 kb
Host smart-cdc6f599-b87a-41de-ba30-5c5b8aa442a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27437
00015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.2743700015
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.2621668278
Short name T489
Test name
Test status
Simulation time 857237295 ps
CPU time 17.68 seconds
Started Mar 12 01:42:03 PM PDT 24
Finished Mar 12 01:42:21 PM PDT 24
Peak memory 248512 kb
Host smart-ced4f0e8-f3a9-414c-a454-ff007e50af84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26216
68278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.2621668278
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.2780475373
Short name T499
Test name
Test status
Simulation time 11453469821 ps
CPU time 771.97 seconds
Started Mar 12 01:42:11 PM PDT 24
Finished Mar 12 01:55:03 PM PDT 24
Peak memory 272788 kb
Host smart-2e86a15d-2187-439c-894e-1bbb817cfb00
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780475373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.2780475373
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.3936192181
Short name T559
Test name
Test status
Simulation time 1668822618 ps
CPU time 87.33 seconds
Started Mar 12 01:42:10 PM PDT 24
Finished Mar 12 01:43:37 PM PDT 24
Peak memory 249556 kb
Host smart-92a9adae-96e4-4535-8f84-f348cc0d0374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39361
92181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.3936192181
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.2235993824
Short name T691
Test name
Test status
Simulation time 1157286871 ps
CPU time 71.35 seconds
Started Mar 12 01:42:10 PM PDT 24
Finished Mar 12 01:43:22 PM PDT 24
Peak memory 254392 kb
Host smart-3d051390-181a-45ee-857c-6b496473d3f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22359
93824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.2235993824
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.4072744821
Short name T11
Test name
Test status
Simulation time 56995289264 ps
CPU time 2590.03 seconds
Started Mar 12 01:42:18 PM PDT 24
Finished Mar 12 02:25:28 PM PDT 24
Peak memory 289228 kb
Host smart-841fe5e9-8749-4d50-90c7-900e7b63da32
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072744821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.4072744821
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.3504504030
Short name T116
Test name
Test status
Simulation time 119605064189 ps
CPU time 2036.97 seconds
Started Mar 12 01:42:19 PM PDT 24
Finished Mar 12 02:16:16 PM PDT 24
Peak memory 273152 kb
Host smart-3cbc77f3-693b-4707-baf9-a730e16887fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504504030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.3504504030
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.433660300
Short name T568
Test name
Test status
Simulation time 64377997393 ps
CPU time 542.3 seconds
Started Mar 12 01:42:11 PM PDT 24
Finished Mar 12 01:51:13 PM PDT 24
Peak memory 247476 kb
Host smart-7a6dbd7e-aa72-4afb-be65-45bbce18ac7b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433660300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.433660300
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.2545382398
Short name T359
Test name
Test status
Simulation time 713722059 ps
CPU time 30.18 seconds
Started Mar 12 01:42:09 PM PDT 24
Finished Mar 12 01:42:40 PM PDT 24
Peak memory 248548 kb
Host smart-4674a252-ee44-47e8-b2a5-474b3a56ddce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25453
82398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.2545382398
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.898518
Short name T413
Test name
Test status
Simulation time 206806366 ps
CPU time 18.19 seconds
Started Mar 12 01:42:10 PM PDT 24
Finished Mar 12 01:42:28 PM PDT 24
Peak memory 247084 kb
Host smart-6aaf08de-55b0-4223-a5cd-20ff6d5d06a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89851
8 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.898518
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.3364339093
Short name T371
Test name
Test status
Simulation time 63757765 ps
CPU time 3.37 seconds
Started Mar 12 01:42:09 PM PDT 24
Finished Mar 12 01:42:13 PM PDT 24
Peak memory 240364 kb
Host smart-a3cb2e88-31a4-4eab-9938-ddd4db3676ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33643
39093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.3364339093
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.902763401
Short name T463
Test name
Test status
Simulation time 584378207 ps
CPU time 39.6 seconds
Started Mar 12 01:42:12 PM PDT 24
Finished Mar 12 01:42:52 PM PDT 24
Peak memory 248676 kb
Host smart-4068594c-5f7e-490e-9feb-34a121831ab9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90276
3401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.902763401
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.1231398101
Short name T422
Test name
Test status
Simulation time 9078846533 ps
CPU time 248.79 seconds
Started Mar 12 01:42:18 PM PDT 24
Finished Mar 12 01:46:27 PM PDT 24
Peak memory 253724 kb
Host smart-aede25a6-b654-45a1-b302-631e5adb1e66
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231398101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.1231398101
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.160329554
Short name T452
Test name
Test status
Simulation time 42232970676 ps
CPU time 1553.96 seconds
Started Mar 12 01:42:17 PM PDT 24
Finished Mar 12 02:08:11 PM PDT 24
Peak memory 273136 kb
Host smart-b9156a94-55e4-4f3c-af11-929bfb5a77c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160329554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.160329554
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.343467891
Short name T348
Test name
Test status
Simulation time 3750146758 ps
CPU time 52.08 seconds
Started Mar 12 01:42:20 PM PDT 24
Finished Mar 12 01:43:12 PM PDT 24
Peak memory 255496 kb
Host smart-2bcc28d8-807d-44d8-8bbd-f5577fe397a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34346
7891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.343467891
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.4285422940
Short name T465
Test name
Test status
Simulation time 2675618142 ps
CPU time 38.25 seconds
Started Mar 12 01:42:19 PM PDT 24
Finished Mar 12 01:42:57 PM PDT 24
Peak memory 254376 kb
Host smart-eb290cb8-8ee5-4e21-8754-125157757a62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42854
22940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.4285422940
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.356479176
Short name T650
Test name
Test status
Simulation time 124923320255 ps
CPU time 828.2 seconds
Started Mar 12 01:42:26 PM PDT 24
Finished Mar 12 01:56:15 PM PDT 24
Peak memory 273088 kb
Host smart-8f73a905-5945-43d8-b8fe-6e65e6127215
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356479176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.356479176
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.2353666473
Short name T546
Test name
Test status
Simulation time 12973720252 ps
CPU time 314.9 seconds
Started Mar 12 01:42:27 PM PDT 24
Finished Mar 12 01:47:42 PM PDT 24
Peak memory 254628 kb
Host smart-40b1e4a8-d3ba-4fa7-8f8b-8b70264d92a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353666473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.2353666473
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.1164864380
Short name T538
Test name
Test status
Simulation time 119003628 ps
CPU time 4.81 seconds
Started Mar 12 01:42:19 PM PDT 24
Finished Mar 12 01:42:24 PM PDT 24
Peak memory 240340 kb
Host smart-94458003-8eeb-42d8-b858-cf53d14bb429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11648
64380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.1164864380
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.3711045417
Short name T586
Test name
Test status
Simulation time 2963368244 ps
CPU time 52.34 seconds
Started Mar 12 01:42:18 PM PDT 24
Finished Mar 12 01:43:11 PM PDT 24
Peak memory 255616 kb
Host smart-4efddc66-134d-4feb-8f58-4b77fbd046a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37110
45417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.3711045417
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.4208968568
Short name T425
Test name
Test status
Simulation time 963678892 ps
CPU time 57.18 seconds
Started Mar 12 01:42:18 PM PDT 24
Finished Mar 12 01:43:15 PM PDT 24
Peak memory 255860 kb
Host smart-9d689acb-83f8-4350-84e0-23ff41907945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42089
68568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.4208968568
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.2491156124
Short name T423
Test name
Test status
Simulation time 312366499 ps
CPU time 5.91 seconds
Started Mar 12 01:42:18 PM PDT 24
Finished Mar 12 01:42:24 PM PDT 24
Peak memory 240352 kb
Host smart-d8593d8d-2ed5-403d-aaac-ef2903d3222e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24911
56124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.2491156124
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.2263719735
Short name T420
Test name
Test status
Simulation time 77866009032 ps
CPU time 2268.41 seconds
Started Mar 12 01:42:28 PM PDT 24
Finished Mar 12 02:20:17 PM PDT 24
Peak memory 282192 kb
Host smart-4a637353-eec3-4b7b-bb9b-238aad4b165f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263719735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.2263719735
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.409561833
Short name T566
Test name
Test status
Simulation time 16614658589 ps
CPU time 1441.88 seconds
Started Mar 12 01:42:33 PM PDT 24
Finished Mar 12 02:06:36 PM PDT 24
Peak memory 284668 kb
Host smart-97a22795-f4ad-49a0-a0e6-b97bd6025658
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409561833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.409561833
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.3048546210
Short name T103
Test name
Test status
Simulation time 7003849096 ps
CPU time 78.99 seconds
Started Mar 12 01:42:29 PM PDT 24
Finished Mar 12 01:43:48 PM PDT 24
Peak memory 256344 kb
Host smart-7a42999d-2f98-469e-ad4b-debb11e87d8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30485
46210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.3048546210
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.1170127537
Short name T460
Test name
Test status
Simulation time 358888993 ps
CPU time 20.79 seconds
Started Mar 12 01:42:28 PM PDT 24
Finished Mar 12 01:42:49 PM PDT 24
Peak memory 254336 kb
Host smart-9c8a7c27-a711-43f1-b29f-a1712e64e8ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11701
27537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.1170127537
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.3602416276
Short name T86
Test name
Test status
Simulation time 16893557933 ps
CPU time 970.79 seconds
Started Mar 12 01:42:33 PM PDT 24
Finished Mar 12 01:58:45 PM PDT 24
Peak memory 288928 kb
Host smart-a32be76f-772d-48e1-96f6-31806f9cfbf6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602416276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3602416276
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.2337512778
Short name T643
Test name
Test status
Simulation time 10721390817 ps
CPU time 473.68 seconds
Started Mar 12 01:42:35 PM PDT 24
Finished Mar 12 01:50:29 PM PDT 24
Peak memory 247372 kb
Host smart-0a46a25c-0ce0-450a-abfb-a0af0a54ff4e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337512778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.2337512778
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.122764559
Short name T504
Test name
Test status
Simulation time 287370889 ps
CPU time 27.32 seconds
Started Mar 12 01:42:26 PM PDT 24
Finished Mar 12 01:42:54 PM PDT 24
Peak memory 248508 kb
Host smart-7962ef80-a736-4800-bcf1-8ed93c28b29f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12276
4559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.122764559
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.358017492
Short name T60
Test name
Test status
Simulation time 52299177 ps
CPU time 7.74 seconds
Started Mar 12 01:42:27 PM PDT 24
Finished Mar 12 01:42:35 PM PDT 24
Peak memory 254996 kb
Host smart-53c18a9c-5088-45ae-b19b-39011ca73700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35801
7492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.358017492
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.2953542453
Short name T57
Test name
Test status
Simulation time 1524086537 ps
CPU time 53.54 seconds
Started Mar 12 01:42:27 PM PDT 24
Finished Mar 12 01:43:21 PM PDT 24
Peak memory 254932 kb
Host smart-03686c64-2e68-4458-94ce-437155d01e78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29535
42453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.2953542453
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.938578391
Short name T395
Test name
Test status
Simulation time 882115230 ps
CPU time 16.63 seconds
Started Mar 12 01:42:26 PM PDT 24
Finished Mar 12 01:42:43 PM PDT 24
Peak memory 253948 kb
Host smart-f99bd633-2e6d-40b4-a8d3-09711a57d6b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93857
8391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.938578391
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.3144187550
Short name T544
Test name
Test status
Simulation time 130783252251 ps
CPU time 1261.55 seconds
Started Mar 12 01:42:32 PM PDT 24
Finished Mar 12 02:03:34 PM PDT 24
Peak memory 272808 kb
Host smart-ec790d57-8989-4f9c-96bb-a62662826581
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144187550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.3144187550
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.1220217049
Short name T534
Test name
Test status
Simulation time 14727372819 ps
CPU time 1370.2 seconds
Started Mar 12 01:42:43 PM PDT 24
Finished Mar 12 02:05:34 PM PDT 24
Peak memory 289392 kb
Host smart-96a8d633-3e9f-415d-a640-7eab9fa27b5e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220217049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.1220217049
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.1535054070
Short name T535
Test name
Test status
Simulation time 372788141 ps
CPU time 27.59 seconds
Started Mar 12 01:42:46 PM PDT 24
Finished Mar 12 01:43:14 PM PDT 24
Peak memory 255460 kb
Host smart-8c72bb3a-79b3-4d05-8585-61427117096d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15350
54070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.1535054070
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.1663169023
Short name T354
Test name
Test status
Simulation time 331827838 ps
CPU time 35.66 seconds
Started Mar 12 01:42:42 PM PDT 24
Finished Mar 12 01:43:18 PM PDT 24
Peak memory 255128 kb
Host smart-499a3b96-9a9e-44a6-984e-35b2c5b6c507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16631
69023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.1663169023
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2990626998
Short name T117
Test name
Test status
Simulation time 163250534512 ps
CPU time 1333.67 seconds
Started Mar 12 01:42:42 PM PDT 24
Finished Mar 12 02:04:56 PM PDT 24
Peak memory 264940 kb
Host smart-00a6d245-6196-424e-ae1d-9f0aec230030
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990626998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2990626998
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.2001714760
Short name T520
Test name
Test status
Simulation time 163832526 ps
CPU time 11.34 seconds
Started Mar 12 01:42:35 PM PDT 24
Finished Mar 12 01:42:47 PM PDT 24
Peak memory 251432 kb
Host smart-2f0807c4-3028-464f-af61-2262319e580b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20017
14760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.2001714760
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.3405701872
Short name T235
Test name
Test status
Simulation time 316752910 ps
CPU time 19.45 seconds
Started Mar 12 01:42:41 PM PDT 24
Finished Mar 12 01:43:01 PM PDT 24
Peak memory 246784 kb
Host smart-37ce2343-ee05-43f4-bcf5-176c314e7276
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34057
01872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.3405701872
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.1870408475
Short name T478
Test name
Test status
Simulation time 628829508 ps
CPU time 25.06 seconds
Started Mar 12 01:42:43 PM PDT 24
Finished Mar 12 01:43:09 PM PDT 24
Peak memory 255892 kb
Host smart-799863ba-820e-415a-ac73-1adbcb89873e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18704
08475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.1870408475
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.534881588
Short name T611
Test name
Test status
Simulation time 60634901 ps
CPU time 9.91 seconds
Started Mar 12 01:42:36 PM PDT 24
Finished Mar 12 01:42:46 PM PDT 24
Peak memory 248536 kb
Host smart-a29f22e9-a444-4f95-9b15-eaf92eeb1511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53488
1588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.534881588
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.2229794847
Short name T702
Test name
Test status
Simulation time 1590867401 ps
CPU time 29.01 seconds
Started Mar 12 01:42:48 PM PDT 24
Finished Mar 12 01:43:18 PM PDT 24
Peak memory 255384 kb
Host smart-c4f87269-5c65-400d-8ea5-c6f6293a70da
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229794847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.2229794847
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.359484147
Short name T52
Test name
Test status
Simulation time 787189174370 ps
CPU time 3250.57 seconds
Started Mar 12 01:42:50 PM PDT 24
Finished Mar 12 02:37:01 PM PDT 24
Peak memory 281360 kb
Host smart-1655822a-7455-49e2-ac96-e8beea3e115f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359484147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.359484147
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.3837912466
Short name T661
Test name
Test status
Simulation time 6621328888 ps
CPU time 188.67 seconds
Started Mar 12 01:42:48 PM PDT 24
Finished Mar 12 01:45:58 PM PDT 24
Peak memory 256076 kb
Host smart-d31d3ea1-5f10-432c-bd22-00fbce6a7386
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38379
12466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.3837912466
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.4213420001
Short name T502
Test name
Test status
Simulation time 124255035 ps
CPU time 10.77 seconds
Started Mar 12 01:42:47 PM PDT 24
Finished Mar 12 01:42:58 PM PDT 24
Peak memory 254296 kb
Host smart-d626bb1f-76eb-45d3-b15e-0dea741b412a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42134
20001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.4213420001
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.4111531145
Short name T576
Test name
Test status
Simulation time 50928305353 ps
CPU time 1490.23 seconds
Started Mar 12 01:42:48 PM PDT 24
Finished Mar 12 02:07:39 PM PDT 24
Peak memory 289528 kb
Host smart-d4a33b0d-9145-441c-a3d1-4b7be51ba558
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111531145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.4111531145
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.1137131986
Short name T312
Test name
Test status
Simulation time 8408489910 ps
CPU time 367.13 seconds
Started Mar 12 01:42:52 PM PDT 24
Finished Mar 12 01:49:00 PM PDT 24
Peak memory 247380 kb
Host smart-b004b9a0-6a1b-46ca-b881-c992f47b3f17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137131986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.1137131986
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.180172792
Short name T186
Test name
Test status
Simulation time 534150146 ps
CPU time 19.23 seconds
Started Mar 12 01:42:48 PM PDT 24
Finished Mar 12 01:43:08 PM PDT 24
Peak memory 253564 kb
Host smart-2cbaa20f-2d20-4a43-86b1-88730748b93d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18017
2792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.180172792
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.1605262883
Short name T532
Test name
Test status
Simulation time 3054603867 ps
CPU time 35.18 seconds
Started Mar 12 01:42:47 PM PDT 24
Finished Mar 12 01:43:23 PM PDT 24
Peak memory 254788 kb
Host smart-4b772fe9-bbd9-4598-989f-963d01567879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16052
62883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.1605262883
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.2950620489
Short name T604
Test name
Test status
Simulation time 166510820 ps
CPU time 18.18 seconds
Started Mar 12 01:42:48 PM PDT 24
Finished Mar 12 01:43:07 PM PDT 24
Peak memory 254016 kb
Host smart-cc0638a5-6dcf-4d3b-a791-d9cc22a23e28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29506
20489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.2950620489
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.802828991
Short name T185
Test name
Test status
Simulation time 2205586198 ps
CPU time 10.17 seconds
Started Mar 12 01:42:48 PM PDT 24
Finished Mar 12 01:42:59 PM PDT 24
Peak memory 248792 kb
Host smart-bcabece4-8ae9-4ec3-9897-ad52702ec55c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80282
8991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.802828991
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.2984692613
Short name T563
Test name
Test status
Simulation time 6711106219 ps
CPU time 359.34 seconds
Started Mar 12 01:42:49 PM PDT 24
Finished Mar 12 01:48:49 PM PDT 24
Peak memory 255180 kb
Host smart-39172901-41a5-436b-aa0f-09d5a0963f4e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984692613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.2984692613
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.2806420486
Short name T203
Test name
Test status
Simulation time 114458873 ps
CPU time 3.44 seconds
Started Mar 12 01:39:11 PM PDT 24
Finished Mar 12 01:39:15 PM PDT 24
Peak memory 248668 kb
Host smart-7b301403-20f4-4356-bb54-48320ade6e77
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2806420486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.2806420486
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.597210871
Short name T402
Test name
Test status
Simulation time 212523350892 ps
CPU time 1878.74 seconds
Started Mar 12 01:39:14 PM PDT 24
Finished Mar 12 02:10:35 PM PDT 24
Peak memory 272464 kb
Host smart-54da2cc4-dbc7-4271-9bd5-89acccb94efe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597210871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.597210871
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.4186943657
Short name T199
Test name
Test status
Simulation time 186176562 ps
CPU time 10.46 seconds
Started Mar 12 01:38:17 PM PDT 24
Finished Mar 12 01:38:28 PM PDT 24
Peak memory 240300 kb
Host smart-f7f17e8c-45a5-4ddf-8016-80a2fb053a5d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4186943657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.4186943657
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.3173726652
Short name T597
Test name
Test status
Simulation time 1373306584 ps
CPU time 60.54 seconds
Started Mar 12 01:39:15 PM PDT 24
Finished Mar 12 01:40:18 PM PDT 24
Peak memory 256028 kb
Host smart-fe9e3bea-ba5f-48ad-9f5e-265faad026ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31737
26652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3173726652
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.2203223893
Short name T693
Test name
Test status
Simulation time 149855112 ps
CPU time 6.65 seconds
Started Mar 12 01:39:14 PM PDT 24
Finished Mar 12 01:39:23 PM PDT 24
Peak memory 249252 kb
Host smart-aba6ed13-2d8b-4d09-811f-79d4ea0229db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22032
23893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.2203223893
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.2887586939
Short name T309
Test name
Test status
Simulation time 95943327043 ps
CPU time 3221.59 seconds
Started Mar 12 01:39:12 PM PDT 24
Finished Mar 12 02:32:54 PM PDT 24
Peak memory 289172 kb
Host smart-63487933-f872-4c1f-9dfa-d1a2219e72dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887586939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2887586939
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.3179235380
Short name T380
Test name
Test status
Simulation time 34034678437 ps
CPU time 722.54 seconds
Started Mar 12 01:39:18 PM PDT 24
Finished Mar 12 01:51:25 PM PDT 24
Peak memory 273092 kb
Host smart-509995db-5ed7-4c1e-a37c-855988dbd87d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179235380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.3179235380
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.1880397358
Short name T505
Test name
Test status
Simulation time 7551038260 ps
CPU time 305.1 seconds
Started Mar 12 01:38:54 PM PDT 24
Finished Mar 12 01:44:00 PM PDT 24
Peak memory 247448 kb
Host smart-7eeff2a5-f5d2-4bf2-b386-6cc947d4e49c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880397358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.1880397358
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.1594580745
Short name T602
Test name
Test status
Simulation time 293133704 ps
CPU time 19.67 seconds
Started Mar 12 01:39:08 PM PDT 24
Finished Mar 12 01:39:29 PM PDT 24
Peak memory 255220 kb
Host smart-6f2002d0-f183-4987-978e-5d1b32849aef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15945
80745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1594580745
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.3454439275
Short name T665
Test name
Test status
Simulation time 3613469496 ps
CPU time 52.54 seconds
Started Mar 12 01:39:03 PM PDT 24
Finished Mar 12 01:39:56 PM PDT 24
Peak memory 254916 kb
Host smart-3c5d3e0e-d3a9-4432-8a4d-b9cab983a6cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34544
39275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.3454439275
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.734230679
Short name T39
Test name
Test status
Simulation time 3534227438 ps
CPU time 53.27 seconds
Started Mar 12 01:39:05 PM PDT 24
Finished Mar 12 01:39:58 PM PDT 24
Peak memory 255400 kb
Host smart-dfccdaf9-dc0f-47e6-ab6b-18ba407ce53a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73423
0679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.734230679
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.1574794922
Short name T406
Test name
Test status
Simulation time 379848813 ps
CPU time 26.02 seconds
Started Mar 12 01:39:16 PM PDT 24
Finished Mar 12 01:39:46 PM PDT 24
Peak memory 248628 kb
Host smart-96e40b7a-b627-4045-a33e-cb1d64539dc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15747
94922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.1574794922
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.2889629091
Short name T625
Test name
Test status
Simulation time 2814842471 ps
CPU time 141.72 seconds
Started Mar 12 01:39:15 PM PDT 24
Finished Mar 12 01:41:41 PM PDT 24
Peak memory 249988 kb
Host smart-ee982056-3ebb-4bf9-9b6c-fb04cec5539e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889629091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.2889629091
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.1678543067
Short name T218
Test name
Test status
Simulation time 58999256 ps
CPU time 4.23 seconds
Started Mar 12 01:39:01 PM PDT 24
Finished Mar 12 01:39:05 PM PDT 24
Peak memory 248704 kb
Host smart-4e4cc072-2c2e-453b-9c7b-e4a7640e6e89
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1678543067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.1678543067
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2599849811
Short name T279
Test name
Test status
Simulation time 170862593290 ps
CPU time 2646.84 seconds
Started Mar 12 01:39:14 PM PDT 24
Finished Mar 12 02:23:23 PM PDT 24
Peak memory 281372 kb
Host smart-9aff2208-f940-4e7b-afda-9c5eeb37f3fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599849811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2599849811
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.2278807523
Short name T627
Test name
Test status
Simulation time 612597983 ps
CPU time 27.21 seconds
Started Mar 12 01:39:15 PM PDT 24
Finished Mar 12 01:39:44 PM PDT 24
Peak memory 248516 kb
Host smart-2f82c1dd-14dc-4b9d-9a7c-7183fb6d47b9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2278807523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.2278807523
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.2415536991
Short name T699
Test name
Test status
Simulation time 14302487257 ps
CPU time 214.49 seconds
Started Mar 12 01:39:15 PM PDT 24
Finished Mar 12 01:42:52 PM PDT 24
Peak memory 256192 kb
Host smart-1cc2ed90-7741-44ad-b822-fe53733d6211
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24155
36991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.2415536991
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.2455159915
Short name T485
Test name
Test status
Simulation time 31407094 ps
CPU time 5.71 seconds
Started Mar 12 01:38:58 PM PDT 24
Finished Mar 12 01:39:04 PM PDT 24
Peak memory 250892 kb
Host smart-021cecb5-cd98-4212-a57b-c58d7bcefb6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24551
59915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.2455159915
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.3553967547
Short name T459
Test name
Test status
Simulation time 10092910833 ps
CPU time 938.6 seconds
Started Mar 12 01:39:12 PM PDT 24
Finished Mar 12 01:54:51 PM PDT 24
Peak memory 272808 kb
Host smart-76f6453e-ffba-45fd-ad15-45384e508f05
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553967547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.3553967547
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.1308424152
Short name T472
Test name
Test status
Simulation time 35470738275 ps
CPU time 2176.02 seconds
Started Mar 12 01:38:52 PM PDT 24
Finished Mar 12 02:15:08 PM PDT 24
Peak memory 273104 kb
Host smart-c447e97b-6a50-4a5d-9d51-010b5e641983
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308424152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.1308424152
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.794098784
Short name T582
Test name
Test status
Simulation time 20203123754 ps
CPU time 413.79 seconds
Started Mar 12 01:38:58 PM PDT 24
Finished Mar 12 01:45:52 PM PDT 24
Peak memory 247428 kb
Host smart-5fe3ca87-2624-4cdb-93ef-f0b097826014
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794098784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.794098784
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.2030479065
Short name T580
Test name
Test status
Simulation time 425645806 ps
CPU time 31.49 seconds
Started Mar 12 01:39:01 PM PDT 24
Finished Mar 12 01:39:32 PM PDT 24
Peak memory 248528 kb
Host smart-fc8b3612-b98e-4f0f-a2c4-770aa1c4af98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20304
79065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.2030479065
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.2151796147
Short name T61
Test name
Test status
Simulation time 242265171 ps
CPU time 21.54 seconds
Started Mar 12 01:39:15 PM PDT 24
Finished Mar 12 01:39:41 PM PDT 24
Peak memory 253848 kb
Host smart-270fdbdc-a828-4d3b-bd4f-28edc95fa932
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21517
96147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.2151796147
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.970190830
Short name T551
Test name
Test status
Simulation time 512885102 ps
CPU time 18.02 seconds
Started Mar 12 01:39:06 PM PDT 24
Finished Mar 12 01:39:25 PM PDT 24
Peak memory 253980 kb
Host smart-c30fd2ca-18c1-4a94-844d-cdaefaef8090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97019
0830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.970190830
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.3512215981
Short name T374
Test name
Test status
Simulation time 938872232 ps
CPU time 24.48 seconds
Started Mar 12 01:39:18 PM PDT 24
Finished Mar 12 01:39:47 PM PDT 24
Peak memory 248540 kb
Host smart-7db67ad2-99f0-422a-b4a0-28570d0123ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35122
15981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.3512215981
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.1236206610
Short name T567
Test name
Test status
Simulation time 33501164331 ps
CPU time 2270.5 seconds
Started Mar 12 01:39:15 PM PDT 24
Finished Mar 12 02:17:08 PM PDT 24
Peak memory 287312 kb
Host smart-96dd4c26-b32d-4e4c-a53a-861ae4a73ba8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236206610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.1236206610
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.2885012926
Short name T239
Test name
Test status
Simulation time 38427920799 ps
CPU time 1053.63 seconds
Started Mar 12 01:39:15 PM PDT 24
Finished Mar 12 01:56:53 PM PDT 24
Peak memory 267312 kb
Host smart-365861fb-e0c7-4b36-b49b-75b2c857bdf1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885012926 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.2885012926
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.3792728305
Short name T59
Test name
Test status
Simulation time 114405088 ps
CPU time 3.19 seconds
Started Mar 12 01:38:45 PM PDT 24
Finished Mar 12 01:38:48 PM PDT 24
Peak memory 248540 kb
Host smart-70c23f35-0d4f-4fcb-aaa4-bcb27186ce0d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3792728305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.3792728305
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.2784332063
Short name T224
Test name
Test status
Simulation time 769170537 ps
CPU time 12.76 seconds
Started Mar 12 01:39:18 PM PDT 24
Finished Mar 12 01:39:35 PM PDT 24
Peak memory 248480 kb
Host smart-bc310eac-783a-454f-b961-507467c89852
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2784332063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.2784332063
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.367762032
Short name T376
Test name
Test status
Simulation time 5853121315 ps
CPU time 124.27 seconds
Started Mar 12 01:39:10 PM PDT 24
Finished Mar 12 01:41:15 PM PDT 24
Peak memory 256728 kb
Host smart-ace93328-6d73-4015-829e-ff86368caac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36776
2032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.367762032
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.603027875
Short name T236
Test name
Test status
Simulation time 214932291 ps
CPU time 9.21 seconds
Started Mar 12 01:38:40 PM PDT 24
Finished Mar 12 01:38:50 PM PDT 24
Peak memory 253992 kb
Host smart-758213e7-5c09-4f31-a218-f1209740ba71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60302
7875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.603027875
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.106773830
Short name T531
Test name
Test status
Simulation time 112864789373 ps
CPU time 1916.47 seconds
Started Mar 12 01:38:59 PM PDT 24
Finished Mar 12 02:10:56 PM PDT 24
Peak memory 282884 kb
Host smart-18fc6aa6-c93c-44a9-8753-15f51510e331
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106773830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.106773830
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.984812165
Short name T194
Test name
Test status
Simulation time 33842613445 ps
CPU time 1655.5 seconds
Started Mar 12 01:39:16 PM PDT 24
Finished Mar 12 02:06:55 PM PDT 24
Peak memory 289160 kb
Host smart-f9c389f7-a019-4986-9a57-5d1ed221150c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984812165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.984812165
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.704779300
Short name T302
Test name
Test status
Simulation time 20994010285 ps
CPU time 217.9 seconds
Started Mar 12 01:39:18 PM PDT 24
Finished Mar 12 01:43:00 PM PDT 24
Peak memory 247468 kb
Host smart-aa233c62-063e-4038-ba96-6db344ab1d4e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704779300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.704779300
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.3687972531
Short name T47
Test name
Test status
Simulation time 1018816749 ps
CPU time 12.11 seconds
Started Mar 12 01:39:17 PM PDT 24
Finished Mar 12 01:39:34 PM PDT 24
Peak memory 248548 kb
Host smart-0813883a-c31c-41d3-9349-16b380486b1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36879
72531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3687972531
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.3106699917
Short name T107
Test name
Test status
Simulation time 1658820284 ps
CPU time 16.41 seconds
Started Mar 12 01:39:03 PM PDT 24
Finished Mar 12 01:39:20 PM PDT 24
Peak memory 254560 kb
Host smart-2bae8f7e-9b1b-42d0-b1f5-da2d19d4adcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31066
99917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.3106699917
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.1744342031
Short name T624
Test name
Test status
Simulation time 815662520 ps
CPU time 15.71 seconds
Started Mar 12 01:39:16 PM PDT 24
Finished Mar 12 01:39:37 PM PDT 24
Peak memory 255056 kb
Host smart-041cc801-259f-4415-8c72-a9940de7d270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17443
42031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.1744342031
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.827246957
Short name T553
Test name
Test status
Simulation time 1372715410 ps
CPU time 7.28 seconds
Started Mar 12 01:39:14 PM PDT 24
Finished Mar 12 01:39:23 PM PDT 24
Peak memory 248524 kb
Host smart-90e0dce7-14db-4f1c-bdf2-4bf4d53955ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82724
6957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.827246957
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.732701193
Short name T75
Test name
Test status
Simulation time 3196993883 ps
CPU time 240.71 seconds
Started Mar 12 01:38:48 PM PDT 24
Finished Mar 12 01:42:49 PM PDT 24
Peak memory 255260 kb
Host smart-b101852c-6b19-4bd6-884f-eae11d33c303
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732701193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_hand
ler_stress_all.732701193
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.3465278514
Short name T56
Test name
Test status
Simulation time 300799570589 ps
CPU time 6516.36 seconds
Started Mar 12 01:39:17 PM PDT 24
Finished Mar 12 03:27:59 PM PDT 24
Peak memory 322332 kb
Host smart-a358fd10-3717-4edd-b221-32a85e3eb436
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465278514 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.3465278514
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.471272336
Short name T210
Test name
Test status
Simulation time 79486547 ps
CPU time 4.48 seconds
Started Mar 12 01:39:17 PM PDT 24
Finished Mar 12 01:39:26 PM PDT 24
Peak memory 248696 kb
Host smart-5c7ccb74-ab96-4194-88d6-c0650b431803
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=471272336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.471272336
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.2916975902
Short name T513
Test name
Test status
Simulation time 106613954729 ps
CPU time 1361.36 seconds
Started Mar 12 01:39:17 PM PDT 24
Finished Mar 12 02:02:03 PM PDT 24
Peak memory 288268 kb
Host smart-fead9668-2e8e-41f5-80d4-fdfb88ce3076
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916975902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.2916975902
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.994300543
Short name T548
Test name
Test status
Simulation time 15214161064 ps
CPU time 38.69 seconds
Started Mar 12 01:38:49 PM PDT 24
Finished Mar 12 01:39:28 PM PDT 24
Peak memory 248556 kb
Host smart-3ee92c97-c7db-42bb-98d9-dc77a674e88a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=994300543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.994300543
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.3052061020
Short name T501
Test name
Test status
Simulation time 9173575258 ps
CPU time 174.45 seconds
Started Mar 12 01:38:44 PM PDT 24
Finished Mar 12 01:41:39 PM PDT 24
Peak memory 256784 kb
Host smart-e68b4c76-8818-487a-8db9-ace1a58725ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30520
61020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.3052061020
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.1272764555
Short name T658
Test name
Test status
Simulation time 40476399 ps
CPU time 6.26 seconds
Started Mar 12 01:39:03 PM PDT 24
Finished Mar 12 01:39:09 PM PDT 24
Peak memory 248552 kb
Host smart-8a6bdff7-c0a9-4918-9a86-370b4471ae89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12727
64555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.1272764555
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.2758453456
Short name T36
Test name
Test status
Simulation time 72358476167 ps
CPU time 1535.15 seconds
Started Mar 12 01:39:06 PM PDT 24
Finished Mar 12 02:04:42 PM PDT 24
Peak memory 289504 kb
Host smart-a4182048-1502-4640-bed0-cdf56f32de94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758453456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.2758453456
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.2564321925
Short name T581
Test name
Test status
Simulation time 30498100284 ps
CPU time 1675.79 seconds
Started Mar 12 01:39:14 PM PDT 24
Finished Mar 12 02:07:12 PM PDT 24
Peak memory 267024 kb
Host smart-a9ecfac9-3c06-424f-9b6b-edb3c2ee5de0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564321925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.2564321925
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.4263620497
Short name T6
Test name
Test status
Simulation time 3043070401 ps
CPU time 130.66 seconds
Started Mar 12 01:39:18 PM PDT 24
Finished Mar 12 01:41:33 PM PDT 24
Peak memory 247476 kb
Host smart-4d42a0ce-9482-4164-bba3-508c14678d67
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263620497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.4263620497
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.1251121084
Short name T404
Test name
Test status
Simulation time 434157583 ps
CPU time 28.54 seconds
Started Mar 12 01:38:40 PM PDT 24
Finished Mar 12 01:39:09 PM PDT 24
Peak memory 248500 kb
Host smart-6edaf849-e6b6-4458-af4c-e79bac56a547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12511
21084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.1251121084
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.637447119
Short name T695
Test name
Test status
Simulation time 366135194 ps
CPU time 17.6 seconds
Started Mar 12 01:39:03 PM PDT 24
Finished Mar 12 01:39:21 PM PDT 24
Peak memory 246660 kb
Host smart-33fac501-0826-4fb3-b984-019ff8f48c78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63744
7119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.637447119
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.288978973
Short name T428
Test name
Test status
Simulation time 167520769 ps
CPU time 20.43 seconds
Started Mar 12 01:39:10 PM PDT 24
Finished Mar 12 01:39:30 PM PDT 24
Peak memory 255320 kb
Host smart-215844b0-9164-4a3e-954c-0f07bf287e34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28897
8973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.288978973
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.2107408037
Short name T181
Test name
Test status
Simulation time 911082137 ps
CPU time 18.57 seconds
Started Mar 12 01:38:55 PM PDT 24
Finished Mar 12 01:39:14 PM PDT 24
Peak memory 248512 kb
Host smart-c740b0e0-4cb1-4a2f-8bdb-b050d9524f8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21074
08037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.2107408037
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.1410623165
Short name T213
Test name
Test status
Simulation time 26553282 ps
CPU time 2.66 seconds
Started Mar 12 01:39:14 PM PDT 24
Finished Mar 12 01:39:17 PM PDT 24
Peak memory 248680 kb
Host smart-fae49b80-3cdf-45a6-bc42-0292eb8375b8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1410623165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.1410623165
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.2798303457
Short name T703
Test name
Test status
Simulation time 100369237224 ps
CPU time 2980.63 seconds
Started Mar 12 01:39:07 PM PDT 24
Finished Mar 12 02:28:48 PM PDT 24
Peak memory 288148 kb
Host smart-92275f1b-915f-46c5-890a-86fa9e5e5a38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798303457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.2798303457
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.1351127615
Short name T542
Test name
Test status
Simulation time 7263315388 ps
CPU time 30.69 seconds
Started Mar 12 01:39:15 PM PDT 24
Finished Mar 12 01:39:50 PM PDT 24
Peak memory 240400 kb
Host smart-f9df306c-13f0-41c3-b6a2-78cadfcda341
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1351127615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.1351127615
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.4220342959
Short name T462
Test name
Test status
Simulation time 16710124474 ps
CPU time 276.35 seconds
Started Mar 12 01:39:14 PM PDT 24
Finished Mar 12 01:43:52 PM PDT 24
Peak memory 255916 kb
Host smart-ce2b888e-18cd-4396-aee9-19b080123365
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42203
42959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.4220342959
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.3948928111
Short name T19
Test name
Test status
Simulation time 839308983 ps
CPU time 12.98 seconds
Started Mar 12 01:38:42 PM PDT 24
Finished Mar 12 01:38:55 PM PDT 24
Peak memory 250968 kb
Host smart-76c20ded-1390-4775-aaf9-29b82b97e887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39489
28111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.3948928111
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.3936110238
Short name T182
Test name
Test status
Simulation time 66773011406 ps
CPU time 1476.22 seconds
Started Mar 12 01:39:12 PM PDT 24
Finished Mar 12 02:03:48 PM PDT 24
Peak memory 288716 kb
Host smart-76d91769-364e-431c-945c-a590a1e4b724
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936110238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.3936110238
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.2336024253
Short name T572
Test name
Test status
Simulation time 142117464392 ps
CPU time 2013.19 seconds
Started Mar 12 01:39:14 PM PDT 24
Finished Mar 12 02:12:50 PM PDT 24
Peak memory 285012 kb
Host smart-c44a5579-71dd-403d-b06b-0911f7f782de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336024253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2336024253
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.3593741382
Short name T293
Test name
Test status
Simulation time 43765193928 ps
CPU time 539.34 seconds
Started Mar 12 01:39:12 PM PDT 24
Finished Mar 12 01:48:12 PM PDT 24
Peak memory 247452 kb
Host smart-85f6ef84-207d-49da-ad6a-bfebe268b23c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593741382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.3593741382
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.3429132945
Short name T573
Test name
Test status
Simulation time 2810117744 ps
CPU time 38.59 seconds
Started Mar 12 01:39:11 PM PDT 24
Finished Mar 12 01:39:50 PM PDT 24
Peak memory 248612 kb
Host smart-4e59c587-9c68-4401-a92c-49541e440a17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34291
32945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.3429132945
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.3295895978
Short name T493
Test name
Test status
Simulation time 253331533 ps
CPU time 30.73 seconds
Started Mar 12 01:39:15 PM PDT 24
Finished Mar 12 01:39:50 PM PDT 24
Peak memory 254264 kb
Host smart-5b6700a3-4529-4c4c-8253-2638a05eadf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32958
95978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.3295895978
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.2152281005
Short name T76
Test name
Test status
Simulation time 117565686 ps
CPU time 8.59 seconds
Started Mar 12 01:39:07 PM PDT 24
Finished Mar 12 01:39:16 PM PDT 24
Peak memory 248508 kb
Host smart-22a72106-02f8-4acf-b7d1-f6f84eaca11c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21522
81005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.2152281005
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.1303403966
Short name T188
Test name
Test status
Simulation time 89381974 ps
CPU time 5.24 seconds
Started Mar 12 01:39:09 PM PDT 24
Finished Mar 12 01:39:15 PM PDT 24
Peak memory 248536 kb
Host smart-37095693-400a-410d-a85b-c566d6085351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13034
03966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.1303403966
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.2875312885
Short name T53
Test name
Test status
Simulation time 23972556538 ps
CPU time 1709.45 seconds
Started Mar 12 01:38:59 PM PDT 24
Finished Mar 12 02:07:29 PM PDT 24
Peak memory 272876 kb
Host smart-579c5d23-acd4-494d-9503-635a3d4e8b68
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875312885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.2875312885
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.1660154059
Short name T95
Test name
Test status
Simulation time 72198918348 ps
CPU time 2287.9 seconds
Started Mar 12 01:39:08 PM PDT 24
Finished Mar 12 02:17:18 PM PDT 24
Peak memory 289648 kb
Host smart-80490ab5-5b92-44a1-a7fb-47fcb49c6d6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660154059 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.1660154059
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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