Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	78992	1			T17	4		T7	7		T8	2
class_i[0x1]	60709	1			T17	6		T9	4		T31	1
class_i[0x2]	46135	1			T17	15		T7	4		T8	2
class_i[0x3]	49504	1			T1	9		T259	1		T31	2

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	61362	1			T1	6		T17	5		T7	5
alert[0x1]	57745	1			T1	1		T17	4		T9	2
alert[0x2]	58312	1			T1	1		T17	5		T7	1
alert[0x3]	57921	1			T1	1		T17	11		T7	5

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

235029

1

T1

9

T17

25

T7

6

esc_ping_fail

311

1

T7

5

T8

2

T9

5

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	61260	1			T1	6		T17	5		T7	2
esc_integrity_fail	alert[0x1]	57671	1			T1	1		T17	4		T100	8
esc_integrity_fail	alert[0x2]	58240	1			T1	1		T17	5		T31	1
esc_integrity_fail	alert[0x3]	57858	1			T1	1		T17	11		T7	4
esc_ping_fail	alert[0x0]	102	1			T7	3		T8	1		T9	1
esc_ping_fail	alert[0x1]	74	1			T9	2		T259	2		T91	1
esc_ping_fail	alert[0x2]	72	1			T7	1		T9	2		T259	1
esc_ping_fail	alert[0x3]	63	1			T7	1		T8	1		T259	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	78899	1			T17	4		T7	6		T259	1
esc_integrity_fail	class_i[0x1]	60639	1			T17	6		T31	1		T63	3
esc_integrity_fail	class_i[0x2]	46077	1			T17	15		T8	2		T100	8
esc_integrity_fail	class_i[0x3]	49414	1			T1	9		T259	1		T31	2
esc_ping_fail	class_i[0x0]	93	1			T7	1		T8	2		T93	7
esc_ping_fail	class_i[0x1]	70	1			T9	4		T99	1		T137	1
esc_ping_fail	class_i[0x2]	58	1			T7	4		T9	1		T259	7
esc_ping_fail	class_i[0x3]	90	1			T91	2		T96	9		T99	1