Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.31	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	1	43	97.73

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	1	43	97.73	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	135	1			T3	1		T22	1		T46	1
index[0x1]	168	1			T17	1		T15	1		T48	3
index[0x2]	137	1			T3	1		T17	1		T6	3
index[0x3]	192	1			T4	1		T5	1		T6	4

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	207	1			T3	1		T4	1		T17	2
lens_less_than_1000[1]	127	1			T6	1		T15	1		T31	1
lens_less_than_1000[2]	94	1			T3	1		T5	1		T6	4
lens_less_than_1000[3]	52	1			T6	2		T31	1		T139	1
lens_less_than_1000[4]	62	1			T22	1		T66	1		T69	1
lens_less_than_1000[5]	31	1			T67	1		T69	1		T72	1
lens_less_than_1000[6]	30	1			T46	1		T291	1		T216	1
lens_less_than_1000[7]	12	1			T88	1		T292	1		T293	1
lens_less_than_1000[8]	7	1			T294	1		T295	1		T274	1
lens_less_than_1000[9]	4	1			T61	1		T109	1		T296	1
len_2	6	1			T59	4		T297	1		T298	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	1	43	97.73	1

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x2]]	[len_2]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	48	1			T65	1		T67	1		T25	1
index[0x0]	lens_less_than_1000[1]	27	1			T25	2		T72	3		T124	2
index[0x0]	lens_less_than_1000[2]	20	1			T3	1		T46	1		T54	1
index[0x0]	lens_less_than_1000[3]	13	1			T299	1		T300	1		T87	1
index[0x0]	lens_less_than_1000[4]	15	1			T22	1		T66	1		T124	1
index[0x0]	lens_less_than_1000[5]	4	1			T50	1		T89	1		T301	1
index[0x0]	lens_less_than_1000[6]	1	1			T302	1		-	-		-	-
index[0x0]	lens_less_than_1000[7]	2	1			T303	1		T304	1		-	-
index[0x0]	lens_less_than_1000[8]	3	1			T295	1		T271	1		T305	1
index[0x0]	lens_less_than_1000[9]	1	1			T109	1		-	-		-	-
index[0x0]	len_2	1	1			T297	1		-	-		-	-
index[0x1]	lens_less_than_1000[0]	59	1			T17	1		T31	1		T25	2
index[0x1]	lens_less_than_1000[1]	34	1			T15	1		T31	1		T124	1
index[0x1]	lens_less_than_1000[2]	20	1			T48	3		T66	1		T213	1
index[0x1]	lens_less_than_1000[3]	13	1			T41	1		T306	2		T132	1
index[0x1]	lens_less_than_1000[4]	19	1			T27	1		T307	1		T308	1
index[0x1]	lens_less_than_1000[5]	5	1			T106	1		T34	1		T309	1
index[0x1]	lens_less_than_1000[6]	12	1			T291	1		T109	5		T310	3
index[0x1]	lens_less_than_1000[7]	3	1			T260	1		T262	1		T311	1
index[0x1]	lens_less_than_1000[8]	1	1			T274	1		-	-		-	-
index[0x1]	lens_less_than_1000[9]	1	1			T312	1		-	-		-	-
index[0x1]	len_2	1	1			T298	1		-	-		-	-
index[0x2]	lens_less_than_1000[0]	39	1			T3	1		T17	1		T51	1
index[0x2]	lens_less_than_1000[1]	29	1			T6	1		T52	1		T54	1
index[0x2]	lens_less_than_1000[2]	19	1			T100	1		T213	1		T300	1
index[0x2]	lens_less_than_1000[3]	11	1			T6	2		T31	1		T76	1
index[0x2]	lens_less_than_1000[4]	13	1			T69	1		T62	1		T313	1
index[0x2]	lens_less_than_1000[5]	10	1			T69	1		T52	3		T314	1
index[0x2]	lens_less_than_1000[6]	12	1			T46	1		T216	1		T132	1
index[0x2]	lens_less_than_1000[7]	2	1			T88	1		T292	1		-	-
index[0x2]	lens_less_than_1000[8]	1	1			T229	1		-	-		-	-
index[0x2]	lens_less_than_1000[9]	1	1			T61	1		-	-		-	-
index[0x3]	lens_less_than_1000[0]	61	1			T4	1		T46	1		T65	1
index[0x3]	lens_less_than_1000[1]	37	1			T25	2		T52	1		T315	1
index[0x3]	lens_less_than_1000[2]	35	1			T5	1		T6	4		T92	2
index[0x3]	lens_less_than_1000[3]	15	1			T139	1		T141	1		T28	1
index[0x3]	lens_less_than_1000[4]	15	1			T71	1		T52	1		T316	1
index[0x3]	lens_less_than_1000[5]	12	1			T67	1		T72	1		T50	1
index[0x3]	lens_less_than_1000[6]	5	1			T306	1		T109	1		T317	1
index[0x3]	lens_less_than_1000[7]	5	1			T293	1		T313	1		T229	1
index[0x3]	lens_less_than_1000[8]	2	1			T294	1		T263	1		-	-
index[0x3]	lens_less_than_1000[9]	1	1			T296	1		-	-		-	-
index[0x3]	len_2	4	1			T59	4		-	-		-	-