Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	3	37	92.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	3	37	92.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	65	1			T24	1		T25	1		T51	1
class_index[0x1]	50	1			T23	1		T32	2		T52	2
class_index[0x2]	55	1			T50	1		T73	1		T52	1
class_index[0x3]	45	1			T20	1		T52	2		T78	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	86	1			T20	1		T25	1		T50	1
intr_timeout_cnt[1]	53	1			T24	1		T32	2		T78	1
intr_timeout_cnt[2]	17	1			T23	1		T78	1		T83	1
intr_timeout_cnt[3]	8	1			T41	1		T56	2		T62	1
intr_timeout_cnt[4]	15	1			T52	1		T62	1		T110	3
intr_timeout_cnt[5]	10	1			T41	1		T126	1		T88	1
intr_timeout_cnt[6]	8	1			T126	1		T88	2		T58	1
intr_timeout_cnt[7]	5	1			T52	1		T88	1		T111	1
intr_timeout_cnt[8]	8	1			T51	1		T126	1		T143	1
intr_timeout_cnt[9]	5	1			T52	1		T28	1		T143	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	3	37	92.50	3

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[3]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[8]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[5]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	30	1			T25	1		T54	1		T84	2
class_index[0x0]	intr_timeout_cnt[1]	14	1			T24	1		T82	1		T29	1
class_index[0x0]	intr_timeout_cnt[2]	7	1			T83	1		T62	1		T109	1
class_index[0x0]	intr_timeout_cnt[4]	3	1			T272	1		T273	1		T274	1
class_index[0x0]	intr_timeout_cnt[5]	5	1			T41	1		T88	1		T275	2
class_index[0x0]	intr_timeout_cnt[6]	2	1			T126	1		T276	1		-	-
class_index[0x0]	intr_timeout_cnt[7]	1	1			T263	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[8]	1	1			T51	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[9]	2	1			T143	1		T277	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	17	1			T52	2		T54	1		T82	1
class_index[0x1]	intr_timeout_cnt[1]	14	1			T32	2		T278	1		T110	2
class_index[0x1]	intr_timeout_cnt[2]	3	1			T23	1		T279	2		-	-
class_index[0x1]	intr_timeout_cnt[3]	1	1			T260	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[4]	4	1			T62	1		T280	1		T277	1
class_index[0x1]	intr_timeout_cnt[5]	2	1			T260	1		T263	1		-	-
class_index[0x1]	intr_timeout_cnt[6]	3	1			T88	1		T58	1		T261	1
class_index[0x1]	intr_timeout_cnt[7]	1	1			T88	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	4	1			T281	1		T282	1		T283	1
class_index[0x1]	intr_timeout_cnt[9]	1	1			T28	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	24	1			T50	1		T73	1		T124	1
class_index[0x2]	intr_timeout_cnt[1]	15	1			T28	2		T125	1		T89	1
class_index[0x2]	intr_timeout_cnt[2]	4	1			T78	1		T260	1		T283	2
class_index[0x2]	intr_timeout_cnt[3]	3	1			T62	1		T109	1		T284	1
class_index[0x2]	intr_timeout_cnt[4]	3	1			T285	1		T113	1		T280	1
class_index[0x2]	intr_timeout_cnt[5]	3	1			T126	1		T209	1		T286	1
class_index[0x2]	intr_timeout_cnt[6]	1	1			T261	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[7]	1	1			T262	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[9]	1	1			T52	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	15	1			T20	1		T107	1		T30	1
class_index[0x3]	intr_timeout_cnt[1]	10	1			T78	1		T132	1		T133	1
class_index[0x3]	intr_timeout_cnt[2]	3	1			T126	1		T260	1		T287	1
class_index[0x3]	intr_timeout_cnt[3]	4	1			T41	1		T56	2		T288	1
class_index[0x3]	intr_timeout_cnt[4]	5	1			T52	1		T110	3		T289	1
class_index[0x3]	intr_timeout_cnt[6]	2	1			T88	1		T113	1		-	-
class_index[0x3]	intr_timeout_cnt[7]	2	1			T52	1		T111	1		-	-
class_index[0x3]	intr_timeout_cnt[8]	3	1			T126	1		T143	1		T290	1
class_index[0x3]	intr_timeout_cnt[9]	1	1			T109	1		-	-		-	-