Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	339816	1			T1	5		T2	7		T3	39
all_values[1]	339816	1			T1	5		T2	7		T3	39
all_values[2]	339816	1			T1	5		T2	7		T3	39
all_values[3]	339816	1			T1	5		T2	7		T3	39

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

674966

1

T1

12

T2

12

T3

80

auto[1]

684298

1

T1

8

T2

16

T3

76

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

802801

1

T1

7

T2

16

T3

80

auto[1]

556463

1

T1

13

T2

12

T3

76

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	95906	1			T1	2		T2	1		T3	9
all_values[0]	auto[0]	auto[1]	72919	1			T1	1		T2	1		T3	9
all_values[0]	auto[1]	auto[0]	97648	1			T1	1		T2	3		T3	11
all_values[0]	auto[1]	auto[1]	73343	1			T1	1		T2	2		T3	10
all_values[1]	auto[0]	auto[0]	99683	1			T1	1		T2	2		T3	10
all_values[1]	auto[0]	auto[1]	68626	1			T1	1		T2	1		T3	9
all_values[1]	auto[1]	auto[0]	102333	1			T2	2		T3	10		T4	255
all_values[1]	auto[1]	auto[1]	69174	1			T1	3		T2	2		T3	10
all_values[2]	auto[0]	auto[0]	100561	1			T1	2		T2	1		T3	6
all_values[2]	auto[0]	auto[1]	68275	1			T1	3		T2	1		T3	6
all_values[2]	auto[1]	auto[0]	102185	1			T2	3		T3	14		T4	232
all_values[2]	auto[1]	auto[1]	68795	1			T2	2		T3	13		T4	232
all_values[3]	auto[0]	auto[0]	101504	1			T1	1		T2	3		T3	16
all_values[3]	auto[0]	auto[1]	67492	1			T1	1		T2	2		T3	15
all_values[3]	auto[1]	auto[0]	102981	1			T2	1		T3	4		T4	236
all_values[3]	auto[1]	auto[1]	67839	1			T1	3		T2	1		T3	4