Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	339816	1			T1	5		T2	7		T3	39
all_pins[1]	339816	1			T1	5		T2	7		T3	39
all_pins[2]	339816	1			T1	5		T2	7		T3	39
all_pins[3]	339816	1			T1	5		T2	7		T3	39

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1080113	1			T1	13		T2	21		T3	119
values[0x1]	279151	1			T1	7		T2	7		T3	37
transitions[0x0=>0x1]	185073	1			T1	5		T2	5		T3	23
transitions[0x1=>0x0]	185318	1			T1	6		T2	5		T3	24

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	266473	1			T1	4		T2	5		T3	29
all_pins[0]	values[0x1]	73343	1			T1	1		T2	2		T3	10
all_pins[0]	transitions[0x0=>0x1]	72698	1			T2	2		T3	9		T4	235
all_pins[0]	transitions[0x1=>0x0]	67439	1			T1	3		T2	1		T3	4
all_pins[1]	values[0x0]	270642	1			T1	2		T2	5		T3	29
all_pins[1]	values[0x1]	69174	1			T1	3		T2	2		T3	10
all_pins[1]	transitions[0x0=>0x1]	37631	1			T1	2		T2	1		T3	7
all_pins[1]	transitions[0x1=>0x0]	41800	1			T2	1		T3	7		T4	112
all_pins[2]	values[0x0]	271021	1			T1	5		T2	5		T3	26
all_pins[2]	values[0x1]	68795	1			T2	2		T3	13		T4	232
all_pins[2]	transitions[0x0=>0x1]	37621	1			T2	1		T3	6		T4	108
all_pins[2]	transitions[0x1=>0x0]	38000	1			T1	3		T2	1		T3	3
all_pins[3]	values[0x0]	271977	1			T1	2		T2	6		T3	35
all_pins[3]	values[0x1]	67839	1			T1	3		T2	1		T3	4
all_pins[3]	transitions[0x0=>0x1]	37123	1			T1	3		T2	1		T3	1
all_pins[3]	transitions[0x1=>0x0]	38079	1			T2	2		T3	10		T4	124