Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	257	1			T186	4		T187	4		T188	4
all_values[1]	257	1			T186	4		T187	4		T188	4
all_values[2]	257	1			T186	4		T187	4		T188	4
all_values[3]	257	1			T186	4		T187	4		T188	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

571

1

T186

8

T187

15

T188

6

auto[1]

457

1

T186

8

T187

1

T188

10

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

392

1

T186

8

T187

8

T188

3

auto[1]

636

1

T186

8

T187

8

T188

13

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

602

1

T186

10

T187

9

T188

8

auto[1]

426

1

T186

6

T187

7

T188

8

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

59

1

T186

1

T187

2

T270

2

all_values[0]

auto[0]

auto[0]

auto[1]

20

1

T187

1

T256

1

T363

1

all_values[0]

auto[0]

auto[1]

auto[0]

46

1

T188

2

T270

2

T364

4

all_values[0]

auto[0]

auto[1]

auto[1]

26

1

T188

1

T256

2

T365

2

all_values[0]

auto[1]

auto[0]

auto[1]

57

1

T186

1

T187

1

T256

1

all_values[0]

auto[1]

auto[1]

auto[1]

49

1

T186

2

T188

1

T256

3

all_values[1]

auto[0]

auto[0]

auto[0]

60

1

T186

1

T187

2

T256

2

all_values[1]

auto[0]

auto[0]

auto[1]

27

1

T366

1

T363

1

T367

1

all_values[1]

auto[0]

auto[1]

auto[0]

44

1

T186

2

T256

1

T270

2

all_values[1]

auto[0]

auto[1]

auto[1]

28

1

T188

1

T256

1

T364

1

all_values[1]

auto[1]

auto[0]

auto[1]

57

1

T186

1

T187

2

T256

2

all_values[1]

auto[1]

auto[1]

auto[1]

41

1

T188

3

T256

1

T364

4

all_values[2]

auto[0]

auto[0]

auto[0]

51

1

T187

2

T188

1

T256

1

all_values[2]

auto[0]

auto[0]

auto[1]

30

1

T186

1

T188

1

T365

1

all_values[2]

auto[0]

auto[1]

auto[0]

42

1

T256

2

T366

2

T365

3

all_values[2]

auto[0]

auto[1]

auto[1]

23

1

T186

1

T256

2

T270

1

all_values[2]

auto[1]

auto[0]

auto[1]

77

1

T186

2

T187

2

T188

2

all_values[2]

auto[1]

auto[1]

auto[1]

34

1

T256

1

T364

3

T365

2

all_values[3]

auto[0]

auto[0]

auto[0]

40

1

T186

1

T187

1

T256

1

all_values[3]

auto[0]

auto[0]

auto[1]

28

1

T188

1

T256

1

T366

2

all_values[3]

auto[0]

auto[1]

auto[0]

50

1

T186

3

T187

1

T270

1

all_values[3]

auto[0]

auto[1]

auto[1]

28

1

T188

1

T364

1

T365

1

all_values[3]

auto[1]

auto[0]

auto[1]

65

1

T187

2

T188

1

T256

4

all_values[3]

auto[1]

auto[1]

auto[1]

46

1

T188

1

T256

1

T364

2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal