Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	86000	1			T4	257		T5	777		T6	674
accum_cnt_1000	236265	1			T4	1743		T5	1219		T6	1250
accum_cnt_100	26094	1			T3	1		T4	101		T5	83
accum_cnt_50	74355	1			T3	45		T4	69		T5	1111
accum_cnt_10	180393	1			T1	14		T2	4		T3	43
accum_cnt_0	364228	1			T1	6		T2	8		T3	19

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	250395	1			T1	5		T2	3		T3	27
class_index[0x1]	250395	1			T1	5		T2	3		T3	27
class_index[0x2]	250395	1			T1	5		T2	3		T3	27
class_index[0x3]	250395	1			T1	5		T2	3		T3	27

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	22550	1			T6	429		T16	320		T49	366
class_index[0x0]	accum_cnt_1000	67116	1			T4	666		T6	541		T16	538
class_index[0x0]	accum_cnt_100	8503	1			T4	38		T6	34		T16	28
class_index[0x0]	accum_cnt_50	21284	1			T3	13		T4	23		T5	1057
class_index[0x0]	accum_cnt_10	44983	1			T1	5		T2	1		T3	3
class_index[0x0]	accum_cnt_0	76727	1			T2	2		T3	11		T4	3
class_index[0x1]	accum_cnt_2000	22177	1			T4	97		T5	366		T15	409
class_index[0x1]	accum_cnt_1000	59507	1			T4	569		T5	625		T15	440
class_index[0x1]	accum_cnt_100	6565	1			T4	33		T5	45		T15	25
class_index[0x1]	accum_cnt_50	16867	1			T4	24		T5	29		T20	6
class_index[0x1]	accum_cnt_10	53531	1			T2	2		T3	24		T4	10
class_index[0x1]	accum_cnt_0	82078	1			T1	5		T2	1		T3	3
class_index[0x2]	accum_cnt_2000	22201	1			T5	411		T6	245		T14	79
class_index[0x2]	accum_cnt_1000	54040	1			T5	594		T6	709		T14	605
class_index[0x2]	accum_cnt_100	5319	1			T3	1		T5	38		T6	38
class_index[0x2]	accum_cnt_50	18654	1			T3	17		T5	25		T6	30
class_index[0x2]	accum_cnt_10	41680	1			T1	4		T2	1		T3	5
class_index[0x2]	accum_cnt_0	101101	1			T1	1		T2	2		T3	4
class_index[0x3]	accum_cnt_2000	19072	1			T4	160		T16	305		T49	317
class_index[0x3]	accum_cnt_1000	55602	1			T4	508		T16	550		T47	1013
class_index[0x3]	accum_cnt_100	5707	1			T4	30		T44	21		T16	32
class_index[0x3]	accum_cnt_50	17550	1			T3	15		T4	22		T20	6
class_index[0x3]	accum_cnt_10	40199	1			T1	5		T3	11		T4	8
class_index[0x3]	accum_cnt_0	104322	1			T2	3		T3	1		T4	7