Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	5099	1			T9	1		T100	10		T52	255
alert[0x1]	5378	1			T9	1		T63	232		T25	33
alert[0x2]	5225	1			T32	22		T52	57		T80	2051
alert[0x3]	3738	1			T259	1		T63	1		T72	9
alert[0x4]	14570	1			T31	77		T23	29		T25	9
alert[0x5]	4232	1			T17	1		T93	1		T99	1
alert[0x6]	13200	1			T25	42		T72	44		T51	2
alert[0x7]	3599	1			T9	1		T31	109		T23	3
alert[0x8]	7500	1			T9	1		T31	18		T25	20
alert[0x9]	4086	1			T100	37		T31	54		T72	41
alert[0xa]	16564	1			T100	6		T259	1		T63	18
alert[0xb]	5812	1			T259	1		T63	9		T93	1
alert[0xc]	10447	1			T9	1		T259	1		T99	1
alert[0xd]	8087	1			T8	1		T100	2		T31	30
alert[0xe]	3889	1			T31	68		T32	14		T123	1
alert[0xf]	4685	1			T259	1		T25	16		T93	2
alert[0x10]	6870	1			T31	379		T93	1		T32	1422
alert[0x11]	4796	1			T96	1		T51	4		T32	105
alert[0x12]	4939	1			T259	1		T71	11		T72	14
alert[0x13]	2956	1			T7	1		T8	1		T63	12
alert[0x14]	8327	1			T100	1		T259	2		T63	91
alert[0x15]	5146	1			T7	1		T100	1		T31	38
alert[0x16]	3903	1			T100	8		T63	2625		T25	21
alert[0x17]	5901	1			T17	22		T63	2414		T25	116
alert[0x18]	4221	1			T100	2		T31	156		T63	68
alert[0x19]	9766	1			T31	69		T72	19		T99	1
alert[0x1a]	7061	1			T8	2		T259	3		T31	19
alert[0x1b]	5693	1			T25	124		T93	1		T137	1
alert[0x1c]	3070	1			T17	2		T9	1		T72	23
alert[0x1d]	5383	1			T17	3		T7	1		T100	1
alert[0x1e]	10397	1			T100	1		T31	1		T63	291
alert[0x1f]	2910	1			T9	1		T96	1		T52	2
alert[0x20]	4415	1			T17	6		T100	3		T31	42
alert[0x21]	3434	1			T7	1		T23	16		T25	24
alert[0x22]	8453	1			T9	1		T69	1		T72	264
alert[0x23]	3147	1			T100	58		T31	17		T63	27
alert[0x24]	3037	1			T259	1		T23	1		T25	92
alert[0x25]	3816	1			T8	2		T259	1		T31	67
alert[0x26]	5901	1			T259	1		T63	12		T23	2
alert[0x27]	7590	1			T31	14		T25	602		T72	140
alert[0x28]	2139	1			T1	2		T7	1		T31	6
alert[0x29]	7110	1			T9	1		T72	13		T91	1
alert[0x2a]	6731	1			T31	118		T23	1		T91	1
alert[0x2b]	2592	1			T1	3		T9	1		T63	13
alert[0x2c]	6178	1			T100	1		T259	1		T63	9
alert[0x2d]	5085	1			T7	1		T63	526		T71	2
alert[0x2e]	11054	1			T23	19		T25	31		T72	10
alert[0x2f]	5053	1			T100	4		T259	1		T72	34
alert[0x30]	5178	1			T259	1		T96	1		T32	10
alert[0x31]	3959	1			T17	1		T31	22		T72	96
alert[0x32]	9814	1			T31	123		T72	45		T99	1
alert[0x33]	6983	1			T7	1		T8	1		T100	1
alert[0x34]	5938	1			T25	755		T72	45		T76	106
alert[0x35]	2397	1			T25	47		T72	41		T32	12
alert[0x36]	10304	1			T100	50		T25	194		T71	8
alert[0x37]	5980	1			T31	5		T63	295		T25	12
alert[0x38]	4024	1			T31	70		T25	19		T32	13
alert[0x39]	8319	1			T9	1		T31	38		T63	12
alert[0x3a]	4197	1			T17	2		T63	230		T72	53
alert[0x3b]	10468	1			T7	1		T9	1		T71	2
alert[0x3c]	8445	1			T31	19		T23	5		T25	51
alert[0x3d]	7165	1			T7	1		T25	28		T72	355
alert[0x3e]	10799	1			T25	390		T71	1		T72	117
alert[0x3f]	17464	1			T63	216		T25	82		T93	1
alert[0x40]	5695	1			T9	1		T100	3		T31	150

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	119543	1			T17	22		T7	1		T9	1
class_i[0x1]	101171	1			T17	7		T7	2		T31	1707
class_i[0x2]	76776	1			T1	5		T17	2		T8	7
class_i[0x3]	122824	1			T17	6		T7	6		T100	57

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

419594

1

T1

5

T17

37

T100

189

alert_ping_fail

720

1

T7

9

T8

7

T9

13

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	5089	1			T100	10		T52	255		T75	24
alert_integrity_fail	alert[0x1]	5366	1			T63	232		T25	33		T52	71
alert_integrity_fail	alert[0x2]	5219	1			T32	22		T52	57		T80	2051
alert_integrity_fail	alert[0x3]	3728	1			T63	1		T72	9		T32	9
alert_integrity_fail	alert[0x4]	14558	1			T31	77		T23	29		T25	9
alert_integrity_fail	alert[0x5]	4217	1			T17	1		T316	179		T54	2
alert_integrity_fail	alert[0x6]	13176	1			T25	42		T72	44		T51	2
alert_integrity_fail	alert[0x7]	3591	1			T31	109		T23	3		T25	638
alert_integrity_fail	alert[0x8]	7487	1			T31	18		T25	20		T80	33
alert_integrity_fail	alert[0x9]	4073	1			T100	37		T31	54		T72	41
alert_integrity_fail	alert[0xa]	16553	1			T100	6		T63	18		T25	54
alert_integrity_fail	alert[0xb]	5802	1			T63	9		T123	1		T52	144
alert_integrity_fail	alert[0xc]	10436	1			T32	8		T75	1562		T316	159
alert_integrity_fail	alert[0xd]	8080	1			T100	2		T31	30		T63	7
alert_integrity_fail	alert[0xe]	3883	1			T31	68		T32	14		T123	1
alert_integrity_fail	alert[0xf]	4671	1			T25	16		T32	507		T52	19
alert_integrity_fail	alert[0x10]	6860	1			T31	379		T32	1422		T76	3
alert_integrity_fail	alert[0x11]	4785	1			T51	4		T32	105		T52	239
alert_integrity_fail	alert[0x12]	4918	1			T71	11		T72	14		T52	322
alert_integrity_fail	alert[0x13]	2935	1			T63	12		T72	15		T316	19
alert_integrity_fail	alert[0x14]	8315	1			T100	1		T63	91		T25	117
alert_integrity_fail	alert[0x15]	5132	1			T100	1		T31	38		T72	141
alert_integrity_fail	alert[0x16]	3890	1			T100	8		T63	2625		T25	21
alert_integrity_fail	alert[0x17]	5891	1			T17	22		T63	2414		T25	116
alert_integrity_fail	alert[0x18]	4211	1			T100	2		T31	156		T63	68
alert_integrity_fail	alert[0x19]	9756	1			T31	69		T72	19		T32	658
alert_integrity_fail	alert[0x1a]	7045	1			T31	19		T63	5		T72	350
alert_integrity_fail	alert[0x1b]	5679	1			T25	124		T80	7		T29	17
alert_integrity_fail	alert[0x1c]	3058	1			T17	2		T72	23		T32	95
alert_integrity_fail	alert[0x1d]	5367	1			T17	3		T100	1		T31	13
alert_integrity_fail	alert[0x1e]	10390	1			T100	1		T31	1		T63	291
alert_integrity_fail	alert[0x1f]	2893	1			T52	2		T74	13		T80	84
alert_integrity_fail	alert[0x20]	4400	1			T17	6		T100	3		T31	42
alert_integrity_fail	alert[0x21]	3424	1			T23	16		T25	24		T72	25
alert_integrity_fail	alert[0x22]	8440	1			T72	264		T52	476		T75	839
alert_integrity_fail	alert[0x23]	3134	1			T100	58		T31	17		T63	27
alert_integrity_fail	alert[0x24]	3025	1			T23	1		T25	92		T32	34
alert_integrity_fail	alert[0x25]	3803	1			T31	67		T63	18		T25	14
alert_integrity_fail	alert[0x26]	5891	1			T63	12		T23	2		T25	5
alert_integrity_fail	alert[0x27]	7583	1			T31	14		T25	602		T72	140
alert_integrity_fail	alert[0x28]	2130	1			T1	2		T31	6		T63	21
alert_integrity_fail	alert[0x29]	7096	1			T72	13		T52	297		T76	7
alert_integrity_fail	alert[0x2a]	6721	1			T31	118		T23	1		T32	25
alert_integrity_fail	alert[0x2b]	2582	1			T1	3		T63	13		T72	91
alert_integrity_fail	alert[0x2c]	6160	1			T100	1		T63	9		T72	9
alert_integrity_fail	alert[0x2d]	5076	1			T63	526		T71	2		T32	41
alert_integrity_fail	alert[0x2e]	11044	1			T23	19		T25	31		T72	10
alert_integrity_fail	alert[0x2f]	5043	1			T100	4		T72	34		T32	18
alert_integrity_fail	alert[0x30]	5164	1			T32	10		T75	53		T76	6
alert_integrity_fail	alert[0x31]	3951	1			T17	1		T31	22		T72	96
alert_integrity_fail	alert[0x32]	9807	1			T31	123		T72	45		T29	25
alert_integrity_fail	alert[0x33]	6976	1			T100	1		T23	7		T72	37
alert_integrity_fail	alert[0x34]	5931	1			T25	755		T72	45		T76	106
alert_integrity_fail	alert[0x35]	2390	1			T25	47		T72	41		T32	12
alert_integrity_fail	alert[0x36]	10295	1			T100	50		T25	194		T71	8
alert_integrity_fail	alert[0x37]	5965	1			T31	5		T63	295		T25	12
alert_integrity_fail	alert[0x38]	4017	1			T31	70		T25	19		T32	13
alert_integrity_fail	alert[0x39]	8312	1			T31	38		T63	12		T72	769
alert_integrity_fail	alert[0x3a]	4190	1			T17	2		T63	230		T72	53
alert_integrity_fail	alert[0x3b]	10451	1			T71	2		T32	4		T80	225
alert_integrity_fail	alert[0x3c]	8438	1			T31	19		T23	5		T25	51
alert_integrity_fail	alert[0x3d]	7157	1			T25	28		T72	355		T52	5
alert_integrity_fail	alert[0x3e]	10792	1			T25	390		T71	1		T72	117
alert_integrity_fail	alert[0x3f]	17461	1			T63	216		T25	82		T75	15
alert_integrity_fail	alert[0x40]	5691	1			T100	3		T31	150		T25	17
alert_ping_fail	alert[0x0]	10	1			T9	1		T320	1		T321	2
alert_ping_fail	alert[0x1]	12	1			T9	1		T320	1		T321	1
alert_ping_fail	alert[0x2]	6	1			T322	1		T323	1		T116	1
alert_ping_fail	alert[0x3]	10	1			T259	1		T291	1		T323	1
alert_ping_fail	alert[0x4]	12	1			T324	1		T325	1		T322	1
alert_ping_fail	alert[0x5]	15	1			T93	1		T99	1		T326	1
alert_ping_fail	alert[0x6]	24	1			T135	2		T326	1		T327	1
alert_ping_fail	alert[0x7]	8	1			T9	1		T91	1		T141	1
alert_ping_fail	alert[0x8]	13	1			T9	1		T96	1		T135	1
alert_ping_fail	alert[0x9]	13	1			T91	1		T93	1		T325	1
alert_ping_fail	alert[0xa]	11	1			T259	1		T319	1		T328	1
alert_ping_fail	alert[0xb]	10	1			T259	1		T93	1		T324	1
alert_ping_fail	alert[0xc]	11	1			T9	1		T259	1		T99	1
alert_ping_fail	alert[0xd]	7	1			T8	1		T291	1		T329	2
alert_ping_fail	alert[0xe]	6	1			T326	1		T330	1		T331	1
alert_ping_fail	alert[0xf]	14	1			T259	1		T93	2		T324	2
alert_ping_fail	alert[0x10]	10	1			T93	1		T320	1		T332	1
alert_ping_fail	alert[0x11]	11	1			T96	1		T324	1		T323	1
alert_ping_fail	alert[0x12]	21	1			T259	1		T324	1		T326	3
alert_ping_fail	alert[0x13]	21	1			T7	1		T8	1		T93	1
alert_ping_fail	alert[0x14]	12	1			T259	2		T219	1		T333	1
alert_ping_fail	alert[0x15]	14	1			T7	1		T324	2		T334	2
alert_ping_fail	alert[0x16]	13	1			T93	2		T327	1		T335	1
alert_ping_fail	alert[0x17]	10	1			T99	1		T322	1		T336	1
alert_ping_fail	alert[0x18]	10	1			T137	1		T324	1		T325	1
alert_ping_fail	alert[0x19]	10	1			T99	1		T121	1		T337	1
alert_ping_fail	alert[0x1a]	16	1			T8	2		T259	3		T324	1
alert_ping_fail	alert[0x1b]	14	1			T93	1		T137	1		T141	1
alert_ping_fail	alert[0x1c]	12	1			T9	1		T319	2		T321	1
alert_ping_fail	alert[0x1d]	16	1			T7	1		T93	1		T137	1
alert_ping_fail	alert[0x1e]	7	1			T322	1		T323	1		T338	1
alert_ping_fail	alert[0x1f]	17	1			T9	1		T96	1		T291	1
alert_ping_fail	alert[0x20]	15	1			T99	1		T137	1		T324	1
alert_ping_fail	alert[0x21]	10	1			T7	1		T96	2		T321	1
alert_ping_fail	alert[0x22]	13	1			T9	1		T69	1		T96	1
alert_ping_fail	alert[0x23]	13	1			T93	1		T325	1		T327	1
alert_ping_fail	alert[0x24]	12	1			T259	1		T96	1		T326	1
alert_ping_fail	alert[0x25]	13	1			T8	2		T259	1		T325	1
alert_ping_fail	alert[0x26]	10	1			T259	1		T137	1		T320	2
alert_ping_fail	alert[0x27]	7	1			T326	1		T323	1		T335	1
alert_ping_fail	alert[0x28]	9	1			T7	1		T99	1		T121	1
alert_ping_fail	alert[0x29]	14	1			T9	1		T91	1		T137	1
alert_ping_fail	alert[0x2a]	10	1			T91	1		T96	1		T332	1
alert_ping_fail	alert[0x2b]	10	1			T9	1		T96	1		T99	1
alert_ping_fail	alert[0x2c]	18	1			T259	1		T318	1		T324	1
alert_ping_fail	alert[0x2d]	9	1			T7	1		T324	1		T326	1
alert_ping_fail	alert[0x2e]	10	1			T96	1		T137	1		T320	1
alert_ping_fail	alert[0x2f]	10	1			T259	1		T96	1		T324	2
alert_ping_fail	alert[0x30]	14	1			T259	1		T96	1		T137	1
alert_ping_fail	alert[0x31]	8	1			T335	1		T329	1		T339	1
alert_ping_fail	alert[0x32]	7	1			T99	1		T327	1		T323	1
alert_ping_fail	alert[0x33]	7	1			T7	1		T8	1		T322	1
alert_ping_fail	alert[0x34]	7	1			T322	1		T323	1		T340	1
alert_ping_fail	alert[0x35]	7	1			T332	1		T331	1		T341	1
alert_ping_fail	alert[0x36]	9	1			T96	1		T325	1		T320	1
alert_ping_fail	alert[0x37]	15	1			T96	1		T324	2		T326	1
alert_ping_fail	alert[0x38]	7	1			T325	1		T320	1		T321	1
alert_ping_fail	alert[0x39]	7	1			T9	1		T327	1		T323	1
alert_ping_fail	alert[0x3a]	7	1			T137	1		T320	1		T342	1
alert_ping_fail	alert[0x3b]	17	1			T7	1		T9	1		T96	1
alert_ping_fail	alert[0x3c]	7	1			T291	1		T323	1		T338	1
alert_ping_fail	alert[0x3d]	8	1			T7	1		T99	1		T323	1
alert_ping_fail	alert[0x3e]	7	1			T93	1		T324	1		T338	1
alert_ping_fail	alert[0x3f]	3	1			T93	1		T327	1		T343	1
alert_ping_fail	alert[0x40]	4	1			T9	1		T344	1		T340	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	119375	1			T17	22		T100	95		T23	11
alert_integrity_fail	class_i[0x1]	101036	1			T17	7		T31	1707		T63	7265
alert_integrity_fail	class_i[0x2]	76555	1			T1	5		T17	2		T100	37
alert_integrity_fail	class_i[0x3]	122628	1			T17	6		T100	57		T71	12
alert_ping_fail	class_i[0x0]	168	1			T7	1		T9	1		T96	2
alert_ping_fail	class_i[0x1]	135	1			T7	2		T91	1		T96	11
alert_ping_fail	class_i[0x2]	221	1			T8	7		T9	12		T259	17
alert_ping_fail	class_i[0x3]	196	1			T7	6		T96	1		T99	2