Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.66 99.99 98.72 100.00 100.00 100.00 99.38 99.56


Total test records in report: 827
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T773 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.582794808 Mar 17 02:41:33 PM PDT 24 Mar 17 02:41:34 PM PDT 24 20177836 ps
T774 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.4061458831 Mar 17 02:41:27 PM PDT 24 Mar 17 02:41:41 PM PDT 24 134855878 ps
T775 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3917436961 Mar 17 02:41:40 PM PDT 24 Mar 17 02:41:42 PM PDT 24 8671711 ps
T776 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.573000538 Mar 17 02:42:14 PM PDT 24 Mar 17 02:42:15 PM PDT 24 9936810 ps
T777 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1976426081 Mar 17 02:42:05 PM PDT 24 Mar 17 02:42:29 PM PDT 24 739079208 ps
T778 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2824126526 Mar 17 02:41:32 PM PDT 24 Mar 17 02:43:05 PM PDT 24 1705814457 ps
T156 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1625294370 Mar 17 02:41:46 PM PDT 24 Mar 17 02:44:40 PM PDT 24 8453878726 ps
T779 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.298857927 Mar 17 02:41:26 PM PDT 24 Mar 17 02:41:38 PM PDT 24 1722373933 ps
T780 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3748688572 Mar 17 02:42:14 PM PDT 24 Mar 17 02:42:15 PM PDT 24 11134597 ps
T781 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.53017360 Mar 17 02:42:15 PM PDT 24 Mar 17 02:42:16 PM PDT 24 14264170 ps
T782 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1197264194 Mar 17 02:41:58 PM PDT 24 Mar 17 02:42:04 PM PDT 24 151590739 ps
T783 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1841824489 Mar 17 02:41:32 PM PDT 24 Mar 17 02:41:36 PM PDT 24 88279039 ps
T204 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.764441642 Mar 17 02:41:32 PM PDT 24 Mar 17 02:41:36 PM PDT 24 50527658 ps
T164 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1067263051 Mar 17 02:42:09 PM PDT 24 Mar 17 02:45:47 PM PDT 24 3375551288 ps
T784 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3062264314 Mar 17 02:42:08 PM PDT 24 Mar 17 02:42:19 PM PDT 24 964995964 ps
T171 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.975334556 Mar 17 02:41:45 PM PDT 24 Mar 17 02:50:01 PM PDT 24 6440906158 ps
T785 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.182285172 Mar 17 02:41:29 PM PDT 24 Mar 17 02:41:30 PM PDT 24 8683709 ps
T172 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.886989432 Mar 17 02:41:58 PM PDT 24 Mar 17 02:45:13 PM PDT 24 8900435274 ps
T786 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.4268853637 Mar 17 02:41:57 PM PDT 24 Mar 17 02:41:58 PM PDT 24 10329411 ps
T787 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3752546638 Mar 17 02:42:13 PM PDT 24 Mar 17 02:42:15 PM PDT 24 14383181 ps
T788 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.2713925602 Mar 17 02:41:57 PM PDT 24 Mar 17 02:42:06 PM PDT 24 368544144 ps
T195 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.1341683834 Mar 17 02:42:04 PM PDT 24 Mar 17 02:42:28 PM PDT 24 185024653 ps
T789 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2033472979 Mar 17 02:42:10 PM PDT 24 Mar 17 02:42:32 PM PDT 24 523077742 ps
T790 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3378615764 Mar 17 02:42:04 PM PDT 24 Mar 17 02:42:16 PM PDT 24 2620727624 ps
T791 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.963401353 Mar 17 02:42:16 PM PDT 24 Mar 17 02:42:24 PM PDT 24 295232646 ps
T792 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.2135741323 Mar 17 02:42:15 PM PDT 24 Mar 17 02:42:17 PM PDT 24 11493574 ps
T178 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1066155618 Mar 17 02:41:44 PM PDT 24 Mar 17 02:48:20 PM PDT 24 21922904763 ps
T793 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.511702092 Mar 17 02:42:09 PM PDT 24 Mar 17 02:42:11 PM PDT 24 8573974 ps
T199 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.4274972283 Mar 17 02:41:38 PM PDT 24 Mar 17 02:41:43 PM PDT 24 540092649 ps
T794 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3355348586 Mar 17 02:41:20 PM PDT 24 Mar 17 02:41:26 PM PDT 24 83119271 ps
T795 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3485585499 Mar 17 02:42:16 PM PDT 24 Mar 17 02:42:38 PM PDT 24 331756864 ps
T796 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.539847180 Mar 17 02:41:42 PM PDT 24 Mar 17 02:41:59 PM PDT 24 400193677 ps
T797 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2437422013 Mar 17 02:41:39 PM PDT 24 Mar 17 02:41:47 PM PDT 24 381220690 ps
T198 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.3161354956 Mar 17 02:41:28 PM PDT 24 Mar 17 02:42:07 PM PDT 24 899170995 ps
T201 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.4119975123 Mar 17 02:41:47 PM PDT 24 Mar 17 02:42:23 PM PDT 24 1639479765 ps
T798 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.1136072964 Mar 17 02:42:20 PM PDT 24 Mar 17 02:42:23 PM PDT 24 20761969 ps
T165 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3593953637 Mar 17 02:41:47 PM PDT 24 Mar 17 02:43:29 PM PDT 24 1184648513 ps
T799 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1954009554 Mar 17 02:42:10 PM PDT 24 Mar 17 02:42:11 PM PDT 24 24576129 ps
T182 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.1915155970 Mar 17 02:41:44 PM PDT 24 Mar 17 02:57:40 PM PDT 24 23616868101 ps
T800 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3095814659 Mar 17 02:42:14 PM PDT 24 Mar 17 02:42:15 PM PDT 24 9579574 ps
T801 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.2236378536 Mar 17 02:41:36 PM PDT 24 Mar 17 02:41:40 PM PDT 24 906801675 ps
T802 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3197577247 Mar 17 02:41:39 PM PDT 24 Mar 17 02:41:44 PM PDT 24 30605704 ps
T803 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.3951020142 Mar 17 02:42:16 PM PDT 24 Mar 17 02:42:18 PM PDT 24 10438159 ps
T804 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.720642009 Mar 17 02:42:04 PM PDT 24 Mar 17 02:42:10 PM PDT 24 180261394 ps
T805 /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.744692915 Mar 17 02:41:43 PM PDT 24 Mar 17 02:41:52 PM PDT 24 115738288 ps
T806 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.4060242537 Mar 17 02:41:39 PM PDT 24 Mar 17 02:42:04 PM PDT 24 904195481 ps
T807 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3288545721 Mar 17 02:42:14 PM PDT 24 Mar 17 02:42:16 PM PDT 24 8154756 ps
T808 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1839523232 Mar 17 02:41:33 PM PDT 24 Mar 17 02:41:38 PM PDT 24 246674765 ps
T809 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.4223225545 Mar 17 02:41:31 PM PDT 24 Mar 17 02:41:39 PM PDT 24 178509305 ps
T179 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.856127539 Mar 17 02:41:50 PM PDT 24 Mar 17 03:02:57 PM PDT 24 65834902830 ps
T810 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3234020283 Mar 17 02:41:39 PM PDT 24 Mar 17 02:41:48 PM PDT 24 168621398 ps
T811 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2435614478 Mar 17 02:41:33 PM PDT 24 Mar 17 02:41:38 PM PDT 24 116078987 ps
T812 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.1828443336 Mar 17 02:42:16 PM PDT 24 Mar 17 02:42:19 PM PDT 24 14530772 ps
T813 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.419939812 Mar 17 02:41:17 PM PDT 24 Mar 17 02:41:26 PM PDT 24 120313272 ps
T181 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1738736318 Mar 17 02:41:37 PM PDT 24 Mar 17 02:44:26 PM PDT 24 7210746061 ps
T373 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3874534258 Mar 17 02:41:38 PM PDT 24 Mar 17 02:47:24 PM PDT 24 8117061580 ps
T814 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.186242825 Mar 17 02:41:46 PM PDT 24 Mar 17 02:41:48 PM PDT 24 9804533 ps
T815 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.386388942 Mar 17 02:42:17 PM PDT 24 Mar 17 02:42:19 PM PDT 24 6955458 ps
T816 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3009137560 Mar 17 02:42:05 PM PDT 24 Mar 17 02:42:26 PM PDT 24 1050888279 ps
T817 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2180295956 Mar 17 02:42:02 PM PDT 24 Mar 17 02:42:44 PM PDT 24 510754375 ps
T818 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.72444436 Mar 17 02:41:53 PM PDT 24 Mar 17 02:42:08 PM PDT 24 227184637 ps
T819 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.2158268931 Mar 17 02:42:14 PM PDT 24 Mar 17 02:42:16 PM PDT 24 10982699 ps
T820 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.177431546 Mar 17 02:42:14 PM PDT 24 Mar 17 02:42:15 PM PDT 24 59313748 ps
T821 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1164148397 Mar 17 02:41:45 PM PDT 24 Mar 17 02:41:48 PM PDT 24 11249272 ps
T822 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.611541773 Mar 17 02:41:34 PM PDT 24 Mar 17 02:46:05 PM PDT 24 12558585173 ps
T374 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.3752951864 Mar 17 02:41:28 PM PDT 24 Mar 17 02:51:32 PM PDT 24 33163053259 ps
T175 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2608320097 Mar 17 02:42:09 PM PDT 24 Mar 17 02:55:03 PM PDT 24 18208947936 ps
T823 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.983105388 Mar 17 02:41:29 PM PDT 24 Mar 17 02:41:40 PM PDT 24 858721907 ps
T177 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.2432870332 Mar 17 02:42:03 PM PDT 24 Mar 17 02:44:36 PM PDT 24 2144851932 ps
T824 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.3014408652 Mar 17 02:41:22 PM PDT 24 Mar 17 02:41:28 PM PDT 24 49591903 ps
T825 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.755078122 Mar 17 02:42:04 PM PDT 24 Mar 17 02:42:08 PM PDT 24 216921537 ps
T176 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2558608159 Mar 17 02:41:59 PM PDT 24 Mar 17 02:52:20 PM PDT 24 4889443623 ps
T826 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.1419668808 Mar 17 02:41:57 PM PDT 24 Mar 17 02:41:59 PM PDT 24 10603533 ps
T180 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.4159194892 Mar 17 02:41:19 PM PDT 24 Mar 17 02:43:05 PM PDT 24 2895380094 ps
T827 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.4693524 Mar 17 02:41:29 PM PDT 24 Mar 17 02:43:32 PM PDT 24 7668743912 ps
T197 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2259650190 Mar 17 02:41:45 PM PDT 24 Mar 17 02:41:47 PM PDT 24 35508774 ps
T193 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.4183437337 Mar 17 02:42:09 PM PDT 24 Mar 17 02:43:35 PM PDT 24 1388075982 ps

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.3508456290
Short name T4
Test name
Test status
Simulation time 35383920416 ps
CPU time 1228.76 seconds
Started Mar 17 02:16:19 PM PDT 24
Finished Mar 17 02:36:48 PM PDT 24
Peak memory 272596 kb
Host smart-5522227f-1560-45e4-aad3-4f3f48179214
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508456290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.3508456290
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.2470144659
Short name T25
Test name
Test status
Simulation time 18485891925 ps
CPU time 1891.08 seconds
Started Mar 17 02:14:56 PM PDT 24
Finished Mar 17 02:46:27 PM PDT 24
Peak memory 289416 kb
Host smart-70b9fa62-3181-430d-9b05-32987a5b96f2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470144659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.2470144659
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.556847330
Short name T7
Test name
Test status
Simulation time 6902530666 ps
CPU time 259.2 seconds
Started Mar 17 02:16:43 PM PDT 24
Finished Mar 17 02:21:03 PM PDT 24
Peak memory 247848 kb
Host smart-572d15c3-6af4-4f04-8eb2-fdaa369e09d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556847330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.556847330
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.2330198801
Short name T10
Test name
Test status
Simulation time 711013969 ps
CPU time 22.21 seconds
Started Mar 17 02:14:46 PM PDT 24
Finished Mar 17 02:15:10 PM PDT 24
Peak memory 273396 kb
Host smart-0c9c91cf-0666-4556-8601-c23741bae8f6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2330198801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.2330198801
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.2130254769
Short name T143
Test name
Test status
Simulation time 83992436846 ps
CPU time 2611.87 seconds
Started Mar 17 02:15:06 PM PDT 24
Finished Mar 17 02:58:38 PM PDT 24
Peak memory 287304 kb
Host smart-9fe21bb8-5723-413a-8d6e-ee96637bf6fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130254769 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.2130254769
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.3393814479
Short name T52
Test name
Test status
Simulation time 294302744693 ps
CPU time 3216.84 seconds
Started Mar 17 02:14:44 PM PDT 24
Finished Mar 17 03:08:22 PM PDT 24
Peak memory 289616 kb
Host smart-1c077fe4-039f-4e60-b6c2-3bf590b190fc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393814479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.3393814479
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.743649262
Short name T184
Test name
Test status
Simulation time 616224653 ps
CPU time 23.63 seconds
Started Mar 17 02:42:11 PM PDT 24
Finished Mar 17 02:42:35 PM PDT 24
Peak memory 245176 kb
Host smart-d52ebd15-fcba-4cdf-9bec-b181b364ea5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=743649262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.743649262
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.2389238464
Short name T135
Test name
Test status
Simulation time 73873421393 ps
CPU time 2836.24 seconds
Started Mar 17 02:15:07 PM PDT 24
Finished Mar 17 03:02:24 PM PDT 24
Peak memory 288088 kb
Host smart-91f42517-4f38-44f3-916a-98be06a9bcf3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389238464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.2389238464
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.2062923765
Short name T32
Test name
Test status
Simulation time 18468984847 ps
CPU time 1178.77 seconds
Started Mar 17 02:14:45 PM PDT 24
Finished Mar 17 02:34:24 PM PDT 24
Peak memory 265428 kb
Host smart-8f6edb01-1178-48f9-aab4-9e3eddb0493a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062923765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.2062923765
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.3027714292
Short name T153
Test name
Test status
Simulation time 1877581715 ps
CPU time 223 seconds
Started Mar 17 02:41:31 PM PDT 24
Finished Mar 17 02:45:14 PM PDT 24
Peak memory 265116 kb
Host smart-99f29385-f9d6-4dd5-80d7-8496f9d5bcd3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3027714292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.3027714292
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.2392207867
Short name T103
Test name
Test status
Simulation time 39248596730 ps
CPU time 2261.45 seconds
Started Mar 17 02:16:03 PM PDT 24
Finished Mar 17 02:53:45 PM PDT 24
Peak memory 284564 kb
Host smart-8db303a8-668d-48d4-a1e9-667e3b8ab686
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392207867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.2392207867
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.2984666907
Short name T231
Test name
Test status
Simulation time 3720567121 ps
CPU time 61.75 seconds
Started Mar 17 02:14:59 PM PDT 24
Finished Mar 17 02:16:01 PM PDT 24
Peak memory 240656 kb
Host smart-d77d2d81-28e8-4254-b168-b7481c2781f0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2984666907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.2984666907
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2049030482
Short name T148
Test name
Test status
Simulation time 51149517713 ps
CPU time 1113.06 seconds
Started Mar 17 02:42:07 PM PDT 24
Finished Mar 17 03:00:40 PM PDT 24
Peak memory 272488 kb
Host smart-65cd3411-0f9e-4ede-b7e0-d1b3b22391c2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049030482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.2049030482
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.3398939251
Short name T56
Test name
Test status
Simulation time 35108461292 ps
CPU time 3655.3 seconds
Started Mar 17 02:18:17 PM PDT 24
Finished Mar 17 03:19:12 PM PDT 24
Peak memory 305856 kb
Host smart-d5da8ffa-afac-48ff-9991-f1d4692fa26f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398939251 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.3398939251
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.906249051
Short name T31
Test name
Test status
Simulation time 13582767124 ps
CPU time 673.52 seconds
Started Mar 17 02:20:29 PM PDT 24
Finished Mar 17 02:31:42 PM PDT 24
Peak memory 272820 kb
Host smart-89c9dd4e-46fe-45e8-b38a-1b26bbcbee34
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906249051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.906249051
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.4267337836
Short name T109
Test name
Test status
Simulation time 52004461350 ps
CPU time 5608.82 seconds
Started Mar 17 02:18:36 PM PDT 24
Finished Mar 17 03:52:06 PM PDT 24
Peak memory 354496 kb
Host smart-75e4acb9-1807-474d-8801-b40fdc099a20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267337836 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.4267337836
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.4049161281
Short name T152
Test name
Test status
Simulation time 15444973267 ps
CPU time 1100.34 seconds
Started Mar 17 02:41:16 PM PDT 24
Finished Mar 17 02:59:37 PM PDT 24
Peak memory 265364 kb
Host smart-54ac8bc0-51da-4560-bc5e-5f1a8723c909
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049161281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.4049161281
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.3388998537
Short name T107
Test name
Test status
Simulation time 259131823244 ps
CPU time 2755.97 seconds
Started Mar 17 02:16:14 PM PDT 24
Finished Mar 17 03:02:10 PM PDT 24
Peak memory 281624 kb
Host smart-9ee02824-571c-4f21-ac8b-0613d98f3e60
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388998537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.3388998537
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3577752541
Short name T155
Test name
Test status
Simulation time 6759659547 ps
CPU time 194.99 seconds
Started Mar 17 02:41:40 PM PDT 24
Finished Mar 17 02:44:55 PM PDT 24
Peak memory 265196 kb
Host smart-e3de1cc2-4f74-4367-aa88-d68071fd7f07
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3577752541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.3577752541
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.1389809480
Short name T47
Test name
Test status
Simulation time 26766646880 ps
CPU time 1440.63 seconds
Started Mar 17 02:15:05 PM PDT 24
Finished Mar 17 02:39:07 PM PDT 24
Peak memory 289780 kb
Host smart-90d6929e-5749-46bb-9f21-59c956efd69d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389809480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.1389809480
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1758074637
Short name T256
Test name
Test status
Simulation time 8846210 ps
CPU time 1.6 seconds
Started Mar 17 02:42:14 PM PDT 24
Finished Mar 17 02:42:17 PM PDT 24
Peak memory 236688 kb
Host smart-15d9f604-ba92-41b5-b36e-85776f15474c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1758074637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.1758074637
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.976499478
Short name T170
Test name
Test status
Simulation time 55858854805 ps
CPU time 1054.95 seconds
Started Mar 17 02:42:03 PM PDT 24
Finished Mar 17 02:59:38 PM PDT 24
Peak memory 265156 kb
Host smart-00b3a5ea-4cde-4666-91f0-d1cbf65b7e8f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976499478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.976499478
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.3310079835
Short name T69
Test name
Test status
Simulation time 55448304079 ps
CPU time 3430.17 seconds
Started Mar 17 02:17:40 PM PDT 24
Finished Mar 17 03:14:51 PM PDT 24
Peak memory 289092 kb
Host smart-dbab4eb2-1370-4344-afd0-412208243b38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310079835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.3310079835
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.48745203
Short name T324
Test name
Test status
Simulation time 66918728182 ps
CPU time 538.89 seconds
Started Mar 17 02:16:24 PM PDT 24
Finished Mar 17 02:25:24 PM PDT 24
Peak memory 256068 kb
Host smart-c3ced79d-6213-43c6-ba6a-7ae7a52866f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48745203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.48745203
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.856127539
Short name T179
Test name
Test status
Simulation time 65834902830 ps
CPU time 1265.79 seconds
Started Mar 17 02:41:50 PM PDT 24
Finished Mar 17 03:02:57 PM PDT 24
Peak memory 272836 kb
Host smart-ea81dc9e-5cb7-41c9-a79d-8ed5d975cb5a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856127539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.856127539
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.3497610764
Short name T117
Test name
Test status
Simulation time 37480639515 ps
CPU time 2573.25 seconds
Started Mar 17 02:14:57 PM PDT 24
Finished Mar 17 02:57:51 PM PDT 24
Peak memory 281716 kb
Host smart-6dbfb55f-817f-4eec-aeb1-72c1af1fea8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497610764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.3497610764
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.1028107919
Short name T5
Test name
Test status
Simulation time 158930841157 ps
CPU time 2435.05 seconds
Started Mar 17 02:14:52 PM PDT 24
Finished Mar 17 02:55:27 PM PDT 24
Peak memory 282588 kb
Host smart-b4020d05-13bd-4de7-a86a-5f3961d646e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028107919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.1028107919
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.1593974936
Short name T323
Test name
Test status
Simulation time 14627586659 ps
CPU time 610.54 seconds
Started Mar 17 02:16:54 PM PDT 24
Finished Mar 17 02:27:05 PM PDT 24
Peak memory 247920 kb
Host smart-53d5d24e-8863-436a-9d79-d3ce0eb4765d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593974936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.1593974936
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1066155618
Short name T178
Test name
Test status
Simulation time 21922904763 ps
CPU time 396.51 seconds
Started Mar 17 02:41:44 PM PDT 24
Finished Mar 17 02:48:20 PM PDT 24
Peak memory 265132 kb
Host smart-ca86a233-f514-4933-9f3d-1fb53a1a691b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1066155618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.1066155618
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.1483592574
Short name T334
Test name
Test status
Simulation time 243012253168 ps
CPU time 3449.74 seconds
Started Mar 17 02:15:25 PM PDT 24
Finished Mar 17 03:12:55 PM PDT 24
Peak memory 289512 kb
Host smart-be6d4d5c-f001-494f-bf69-1a446395f44e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483592574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.1483592574
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.1167053729
Short name T329
Test name
Test status
Simulation time 9584696846 ps
CPU time 399.31 seconds
Started Mar 17 02:15:21 PM PDT 24
Finished Mar 17 02:22:00 PM PDT 24
Peak memory 248244 kb
Host smart-616d55e9-316b-406a-9fd9-e6f2e5825c9b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167053729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.1167053729
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.2272729563
Short name T640
Test name
Test status
Simulation time 53106517760 ps
CPU time 544.74 seconds
Started Mar 17 02:19:50 PM PDT 24
Finished Mar 17 02:28:55 PM PDT 24
Peak memory 247096 kb
Host smart-cd347e9f-d265-498c-aac7-72b53a6f1ff5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272729563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.2272729563
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1501388046
Short name T169
Test name
Test status
Simulation time 16910844228 ps
CPU time 1058.43 seconds
Started Mar 17 02:41:46 PM PDT 24
Finished Mar 17 02:59:25 PM PDT 24
Peak memory 265132 kb
Host smart-1b8c2357-967d-4846-b9ad-712270082f0b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501388046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.1501388046
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.1807667593
Short name T260
Test name
Test status
Simulation time 69828845002 ps
CPU time 4762.92 seconds
Started Mar 17 02:15:27 PM PDT 24
Finished Mar 17 03:34:50 PM PDT 24
Peak memory 305408 kb
Host smart-3659e0d6-8bb4-4d5b-9449-9aa42cbea91d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807667593 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.1807667593
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.848450300
Short name T174
Test name
Test status
Simulation time 2354462404 ps
CPU time 332.06 seconds
Started Mar 17 02:41:29 PM PDT 24
Finished Mar 17 02:47:01 PM PDT 24
Peak memory 268428 kb
Host smart-1ad66e5d-8f32-4da2-99ce-c526e6649577
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848450300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.848450300
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3921789478
Short name T157
Test name
Test status
Simulation time 24248314915 ps
CPU time 520.19 seconds
Started Mar 17 02:42:00 PM PDT 24
Finished Mar 17 02:50:41 PM PDT 24
Peak memory 267608 kb
Host smart-bffd038e-436e-4ace-b644-8475992e80ee
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921789478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.3921789478
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.2188688627
Short name T6
Test name
Test status
Simulation time 27534892858 ps
CPU time 1993.98 seconds
Started Mar 17 02:14:44 PM PDT 24
Finished Mar 17 02:47:59 PM PDT 24
Peak memory 282452 kb
Host smart-f154a9a7-a702-4312-84d3-00fe14349a51
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188688627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.2188688627
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.1651599863
Short name T88
Test name
Test status
Simulation time 3232730416 ps
CPU time 49.84 seconds
Started Mar 17 02:16:46 PM PDT 24
Finished Mar 17 02:17:36 PM PDT 24
Peak memory 255512 kb
Host smart-604fb5ce-9158-4433-81c3-a99663977d22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16515
99863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.1651599863
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.1227853589
Short name T345
Test name
Test status
Simulation time 185968891917 ps
CPU time 2187.07 seconds
Started Mar 17 02:18:15 PM PDT 24
Finished Mar 17 02:54:42 PM PDT 24
Peak memory 283776 kb
Host smart-295632c4-6b9f-4e9f-8ef0-0bd254a4dce9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227853589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.1227853589
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.1448964518
Short name T89
Test name
Test status
Simulation time 172975391354 ps
CPU time 6078.95 seconds
Started Mar 17 02:14:54 PM PDT 24
Finished Mar 17 03:56:14 PM PDT 24
Peak memory 347556 kb
Host smart-9889adf8-a59e-46d6-b76a-91693770c5d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448964518 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.1448964518
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1509345558
Short name T150
Test name
Test status
Simulation time 28505208132 ps
CPU time 1071.19 seconds
Started Mar 17 02:41:58 PM PDT 24
Finished Mar 17 02:59:49 PM PDT 24
Peak memory 265168 kb
Host smart-24ec65cf-5393-4010-9063-6fc08da0256d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509345558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.1509345558
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2750902410
Short name T364
Test name
Test status
Simulation time 12059740 ps
CPU time 1.35 seconds
Started Mar 17 02:41:28 PM PDT 24
Finished Mar 17 02:41:30 PM PDT 24
Peak memory 236668 kb
Host smart-35cbfeb7-91b1-43f3-93f1-f3ee547b59a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2750902410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.2750902410
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.832750753
Short name T126
Test name
Test status
Simulation time 108945841894 ps
CPU time 3119.75 seconds
Started Mar 17 02:16:12 PM PDT 24
Finished Mar 17 03:08:12 PM PDT 24
Peak memory 289720 kb
Host smart-3755a826-d676-4a18-8fc0-459ffe0437b6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832750753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_han
dler_stress_all.832750753
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.4144631229
Short name T358
Test name
Test status
Simulation time 180785963282 ps
CPU time 2313.39 seconds
Started Mar 17 02:17:04 PM PDT 24
Finished Mar 17 02:55:38 PM PDT 24
Peak memory 288952 kb
Host smart-9544e8e3-931a-4ca9-8833-ab8032c127fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144631229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.4144631229
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.2598039309
Short name T263
Test name
Test status
Simulation time 34919930892 ps
CPU time 2225.56 seconds
Started Mar 17 02:18:08 PM PDT 24
Finished Mar 17 02:55:14 PM PDT 24
Peak memory 288288 kb
Host smart-8c1dd2bb-bb28-498e-a91c-68792af69f2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598039309 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.2598039309
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.37832541
Short name T9
Test name
Test status
Simulation time 17022652838 ps
CPU time 385.92 seconds
Started Mar 17 02:19:11 PM PDT 24
Finished Mar 17 02:25:37 PM PDT 24
Peak memory 248060 kb
Host smart-7273dc2d-6c49-4bed-8964-67e449ddebb2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37832541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.37832541
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.4274972283
Short name T199
Test name
Test status
Simulation time 540092649 ps
CPU time 4.47 seconds
Started Mar 17 02:41:38 PM PDT 24
Finished Mar 17 02:41:43 PM PDT 24
Peak memory 236956 kb
Host smart-181131e7-b6e3-4a84-96dd-021733b40b9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4274972283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.4274972283
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.2423564905
Short name T93
Test name
Test status
Simulation time 11587554668 ps
CPU time 298.21 seconds
Started Mar 17 02:14:58 PM PDT 24
Finished Mar 17 02:19:57 PM PDT 24
Peak memory 248116 kb
Host smart-67eb5167-1772-49e1-9426-413fe29e9a72
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423564905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.2423564905
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.107499209
Short name T51
Test name
Test status
Simulation time 569862059 ps
CPU time 12.77 seconds
Started Mar 17 02:16:35 PM PDT 24
Finished Mar 17 02:16:48 PM PDT 24
Peak memory 248824 kb
Host smart-1566de35-8c38-4384-ba47-f19b06cab0de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10749
9209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.107499209
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.835933859
Short name T243
Test name
Test status
Simulation time 124846527 ps
CPU time 2.64 seconds
Started Mar 17 02:14:42 PM PDT 24
Finished Mar 17 02:14:45 PM PDT 24
Peak memory 249140 kb
Host smart-0416d3f9-e6d0-409c-b868-ec608be12c97
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=835933859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.835933859
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1951863291
Short name T242
Test name
Test status
Simulation time 24273949 ps
CPU time 2.81 seconds
Started Mar 17 02:14:51 PM PDT 24
Finished Mar 17 02:14:54 PM PDT 24
Peak memory 249064 kb
Host smart-d46e9eef-d2be-481d-9f33-0ee0a2d501c0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1951863291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1951863291
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.2505895558
Short name T247
Test name
Test status
Simulation time 22693544 ps
CPU time 2.6 seconds
Started Mar 17 02:15:17 PM PDT 24
Finished Mar 17 02:15:20 PM PDT 24
Peak memory 249096 kb
Host smart-598208c9-8f15-40f9-922e-d50bda174b6f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2505895558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.2505895558
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.2158112419
Short name T240
Test name
Test status
Simulation time 26131593 ps
CPU time 2.71 seconds
Started Mar 17 02:15:20 PM PDT 24
Finished Mar 17 02:15:23 PM PDT 24
Peak memory 249008 kb
Host smart-355152e0-55d6-42d3-b0fd-4b34ea4df5c0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2158112419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.2158112419
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3200750760
Short name T230
Test name
Test status
Simulation time 5702391520 ps
CPU time 367.72 seconds
Started Mar 17 02:41:26 PM PDT 24
Finished Mar 17 02:47:34 PM PDT 24
Peak memory 235788 kb
Host smart-46223200-9a66-4879-a66e-b3f4b180c9ec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3200750760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.3200750760
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1062796344
Short name T732
Test name
Test status
Simulation time 8485635 ps
CPU time 1.5 seconds
Started Mar 17 02:42:17 PM PDT 24
Finished Mar 17 02:42:19 PM PDT 24
Peak memory 235776 kb
Host smart-80abd0b7-8d00-4ab4-bb54-a135a6d2b16a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1062796344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.1062796344
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.713048802
Short name T351
Test name
Test status
Simulation time 147151414098 ps
CPU time 2593.58 seconds
Started Mar 17 02:15:13 PM PDT 24
Finished Mar 17 02:58:27 PM PDT 24
Peak memory 287084 kb
Host smart-0ae3441a-038b-45c9-8fe9-f18570b789cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713048802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.713048802
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.3798549242
Short name T298
Test name
Test status
Simulation time 3416377675 ps
CPU time 164.12 seconds
Started Mar 17 02:15:55 PM PDT 24
Finished Mar 17 02:18:39 PM PDT 24
Peak memory 252512 kb
Host smart-3dd758af-8868-4477-a6ec-f9557a935b49
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798549242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.3798549242
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.3582630456
Short name T343
Test name
Test status
Simulation time 12900399762 ps
CPU time 547.03 seconds
Started Mar 17 02:16:24 PM PDT 24
Finished Mar 17 02:25:32 PM PDT 24
Peak memory 248084 kb
Host smart-96dcbf7e-dde0-4645-9e43-75d8ff246f7f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582630456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.3582630456
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.505734472
Short name T306
Test name
Test status
Simulation time 249463720896 ps
CPU time 1950.34 seconds
Started Mar 17 02:17:15 PM PDT 24
Finished Mar 17 02:49:45 PM PDT 24
Peak memory 299424 kb
Host smart-60f4dd9f-07d6-4682-9f2d-1633ea578a43
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505734472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_han
dler_stress_all.505734472
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.1302587154
Short name T262
Test name
Test status
Simulation time 126386275251 ps
CPU time 4420.56 seconds
Started Mar 17 02:19:04 PM PDT 24
Finished Mar 17 03:32:45 PM PDT 24
Peak memory 305704 kb
Host smart-5c111d51-b7b7-4607-9646-cd93f84053ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302587154 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.1302587154
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.985769032
Short name T280
Test name
Test status
Simulation time 159474070607 ps
CPU time 7432.07 seconds
Started Mar 17 02:19:32 PM PDT 24
Finished Mar 17 04:23:25 PM PDT 24
Peak memory 338504 kb
Host smart-2d77379f-8333-418f-ad13-e998f2a1473a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985769032 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.985769032
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.2522184027
Short name T106
Test name
Test status
Simulation time 22229275466 ps
CPU time 1752.4 seconds
Started Mar 17 02:19:49 PM PDT 24
Finished Mar 17 02:49:02 PM PDT 24
Peak memory 289008 kb
Host smart-ab0b4d03-720d-49c9-91db-0525f4aafe0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522184027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.2522184027
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.2473391930
Short name T274
Test name
Test status
Simulation time 46049474219 ps
CPU time 1415.42 seconds
Started Mar 17 02:15:04 PM PDT 24
Finished Mar 17 02:38:41 PM PDT 24
Peak memory 289444 kb
Host smart-ca85e8ae-c59c-4787-8e10-93bc6e017744
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473391930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.2473391930
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.1811952148
Short name T332
Test name
Test status
Simulation time 14105533762 ps
CPU time 596.25 seconds
Started Mar 17 02:15:10 PM PDT 24
Finished Mar 17 02:25:06 PM PDT 24
Peak memory 248936 kb
Host smart-6f96db83-36de-40d8-9928-dc22dbb354ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811952148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.1811952148
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.1725277039
Short name T154
Test name
Test status
Simulation time 3950802790 ps
CPU time 284.08 seconds
Started Mar 17 02:42:03 PM PDT 24
Finished Mar 17 02:46:48 PM PDT 24
Peak memory 265136 kb
Host smart-c836052d-b665-44fa-8520-9ee1001994c0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1725277039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.1725277039
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.4249222906
Short name T23
Test name
Test status
Simulation time 249744974 ps
CPU time 27.47 seconds
Started Mar 17 02:19:48 PM PDT 24
Finished Mar 17 02:20:15 PM PDT 24
Peak memory 255460 kb
Host smart-c31190ad-8234-4c83-89bf-063cfcd00465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42492
22906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.4249222906
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.3069686646
Short name T28
Test name
Test status
Simulation time 48013736381 ps
CPU time 3335.29 seconds
Started Mar 17 02:15:02 PM PDT 24
Finished Mar 17 03:10:39 PM PDT 24
Peak memory 300128 kb
Host smart-a83d230e-118b-4042-ab28-569748a64146
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069686646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.3069686646
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3409580212
Short name T146
Test name
Test status
Simulation time 3736507778 ps
CPU time 294.08 seconds
Started Mar 17 02:42:03 PM PDT 24
Finished Mar 17 02:46:58 PM PDT 24
Peak memory 265148 kb
Host smart-33d5b2f0-1373-4616-8744-7f4a09c9fd60
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3409580212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.3409580212
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.1431879970
Short name T61
Test name
Test status
Simulation time 116830608224 ps
CPU time 6721.58 seconds
Started Mar 17 02:15:46 PM PDT 24
Finished Mar 17 04:07:48 PM PDT 24
Peak memory 370484 kb
Host smart-02b61e6d-5352-4f07-a9d3-35e13770b0b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431879970 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.1431879970
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.604207194
Short name T59
Test name
Test status
Simulation time 32519726942 ps
CPU time 2340.31 seconds
Started Mar 17 02:16:28 PM PDT 24
Finished Mar 17 02:55:30 PM PDT 24
Peak memory 289360 kb
Host smart-38942c04-f565-4d80-b0c9-2deb97aceed6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604207194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_han
dler_stress_all.604207194
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.1901298433
Short name T312
Test name
Test status
Simulation time 1303498267 ps
CPU time 20.63 seconds
Started Mar 17 02:16:47 PM PDT 24
Finished Mar 17 02:17:07 PM PDT 24
Peak memory 248888 kb
Host smart-56d8dcae-ba5c-4414-bf9a-eb70d0bdc4e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19012
98433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.1901298433
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.41124567
Short name T302
Test name
Test status
Simulation time 16024597562 ps
CPU time 1537.23 seconds
Started Mar 17 02:16:59 PM PDT 24
Finished Mar 17 02:42:36 PM PDT 24
Peak memory 289068 kb
Host smart-d426e386-bed0-4dee-83cc-3961d7bf20be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41124567 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.41124567
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.2540545034
Short name T305
Test name
Test status
Simulation time 388052556213 ps
CPU time 1539.27 seconds
Started Mar 17 02:16:59 PM PDT 24
Finished Mar 17 02:42:39 PM PDT 24
Peak memory 267364 kb
Host smart-abc4026b-97aa-4d41-9909-9db83dd1df0e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540545034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.2540545034
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.1081498911
Short name T296
Test name
Test status
Simulation time 432753700 ps
CPU time 37.46 seconds
Started Mar 17 02:17:28 PM PDT 24
Finished Mar 17 02:18:05 PM PDT 24
Peak memory 249796 kb
Host smart-8031f734-0dfd-47d6-aa6d-81b9feb6531f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10814
98911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1081498911
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.3030378814
Short name T261
Test name
Test status
Simulation time 50273291426 ps
CPU time 2973.2 seconds
Started Mar 17 02:17:35 PM PDT 24
Finished Mar 17 03:07:09 PM PDT 24
Peak memory 305520 kb
Host smart-c2c74f45-f43f-469e-b3af-11b13ff9bfea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030378814 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.3030378814
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.2971317885
Short name T229
Test name
Test status
Simulation time 167370765884 ps
CPU time 8619.89 seconds
Started Mar 17 02:17:44 PM PDT 24
Finished Mar 17 04:41:25 PM PDT 24
Peak memory 371400 kb
Host smart-33adee37-6286-4f77-bf6b-7e3842ae536d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971317885 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.2971317885
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.2790058110
Short name T297
Test name
Test status
Simulation time 377906013 ps
CPU time 39.98 seconds
Started Mar 17 02:18:14 PM PDT 24
Finished Mar 17 02:18:54 PM PDT 24
Peak memory 248836 kb
Host smart-b321270c-2a20-4a5f-aa6e-297088ff6e99
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790058110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.2790058110
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.825921538
Short name T303
Test name
Test status
Simulation time 1457465613 ps
CPU time 19.95 seconds
Started Mar 17 02:19:13 PM PDT 24
Finished Mar 17 02:19:33 PM PDT 24
Peak memory 248888 kb
Host smart-37c336f3-ce25-4ba3-bc7e-304625682c61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82592
1538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.825921538
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.637986653
Short name T145
Test name
Test status
Simulation time 2707345927 ps
CPU time 310.81 seconds
Started Mar 17 02:42:01 PM PDT 24
Finished Mar 17 02:47:12 PM PDT 24
Peak memory 265144 kb
Host smart-1aad781b-4241-4fd3-bf57-827bef0b59a0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637986653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.637986653
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3902620898
Short name T192
Test name
Test status
Simulation time 661265026 ps
CPU time 49.1 seconds
Started Mar 17 02:42:06 PM PDT 24
Finished Mar 17 02:42:55 PM PDT 24
Peak memory 245056 kb
Host smart-e3e17c19-229c-483f-b054-d84fad24960c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3902620898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.3902620898
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.4183437337
Short name T193
Test name
Test status
Simulation time 1388075982 ps
CPU time 85.54 seconds
Started Mar 17 02:42:09 PM PDT 24
Finished Mar 17 02:43:35 PM PDT 24
Peak memory 239572 kb
Host smart-107197a0-eb5e-47bc-923e-1ffc1e11d05c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4183437337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.4183437337
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3031022650
Short name T189
Test name
Test status
Simulation time 34140900 ps
CPU time 2.75 seconds
Started Mar 17 02:42:08 PM PDT 24
Finished Mar 17 02:42:11 PM PDT 24
Peak memory 236664 kb
Host smart-bc58f7ec-0b2f-46e7-8c8c-b9cdfdc6ac28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3031022650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.3031022650
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3814749025
Short name T202
Test name
Test status
Simulation time 609861045 ps
CPU time 27.86 seconds
Started Mar 17 02:41:41 PM PDT 24
Finished Mar 17 02:42:09 PM PDT 24
Peak memory 236988 kb
Host smart-53d630b6-5a29-491b-bc5c-5d3347d98dac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3814749025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.3814749025
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2259650190
Short name T197
Test name
Test status
Simulation time 35508774 ps
CPU time 2.28 seconds
Started Mar 17 02:41:45 PM PDT 24
Finished Mar 17 02:41:47 PM PDT 24
Peak memory 235752 kb
Host smart-7862ec0f-64ae-44f4-a833-17d53d1d3d5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2259650190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.2259650190
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.4159194892
Short name T180
Test name
Test status
Simulation time 2895380094 ps
CPU time 105.69 seconds
Started Mar 17 02:41:19 PM PDT 24
Finished Mar 17 02:43:05 PM PDT 24
Peak memory 256984 kb
Host smart-73c3c997-c4bb-4d10-b7d2-657e0ed9da25
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4159194892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.4159194892
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.1179268368
Short name T194
Test name
Test status
Simulation time 47452714 ps
CPU time 2.66 seconds
Started Mar 17 02:41:20 PM PDT 24
Finished Mar 17 02:41:23 PM PDT 24
Peak memory 236616 kb
Host smart-333623cc-6329-4dee-9350-96736acd6ba7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1179268368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.1179268368
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1562570744
Short name T196
Test name
Test status
Simulation time 310404158 ps
CPU time 2.99 seconds
Started Mar 17 02:41:27 PM PDT 24
Finished Mar 17 02:41:30 PM PDT 24
Peak memory 237524 kb
Host smart-ba55825a-d639-46b2-bb84-9be3ed6721d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1562570744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1562570744
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.58193290
Short name T191
Test name
Test status
Simulation time 342867285 ps
CPU time 3.84 seconds
Started Mar 17 02:41:52 PM PDT 24
Finished Mar 17 02:41:56 PM PDT 24
Peak memory 235784 kb
Host smart-5e7e8579-9893-472a-89f1-0292a1ea41e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=58193290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.58193290
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2558608159
Short name T176
Test name
Test status
Simulation time 4889443623 ps
CPU time 620.88 seconds
Started Mar 17 02:41:59 PM PDT 24
Finished Mar 17 02:52:20 PM PDT 24
Peak memory 265128 kb
Host smart-b7e5455b-15db-459a-b398-23e7039884a6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558608159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.2558608159
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.100773502
Short name T151
Test name
Test status
Simulation time 4655322241 ps
CPU time 314.9 seconds
Started Mar 17 02:42:04 PM PDT 24
Finished Mar 17 02:47:19 PM PDT 24
Peak memory 265108 kb
Host smart-1fc9fec2-8b8d-4fc8-ae9d-0d416a72ff50
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=100773502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_erro
rs.100773502
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.4210734816
Short name T190
Test name
Test status
Simulation time 111682127 ps
CPU time 2.91 seconds
Started Mar 17 02:41:58 PM PDT 24
Finished Mar 17 02:42:01 PM PDT 24
Peak memory 237648 kb
Host smart-c5aae966-7c32-4cb4-8d3f-ade657b37552
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4210734816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.4210734816
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1642891497
Short name T200
Test name
Test status
Simulation time 36328339 ps
CPU time 2.73 seconds
Started Mar 17 02:41:59 PM PDT 24
Finished Mar 17 02:42:02 PM PDT 24
Peak memory 236636 kb
Host smart-748f7955-87f4-41ef-80ac-cc3294f6d1e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1642891497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.1642891497
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1625294370
Short name T156
Test name
Test status
Simulation time 8453878726 ps
CPU time 173.84 seconds
Started Mar 17 02:41:46 PM PDT 24
Finished Mar 17 02:44:40 PM PDT 24
Peak memory 256912 kb
Host smart-ecd848e2-1623-451f-83b9-644cfb6dbd94
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1625294370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.1625294370
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.1454237330
Short name T203
Test name
Test status
Simulation time 423090788 ps
CPU time 53.37 seconds
Started Mar 17 02:41:51 PM PDT 24
Finished Mar 17 02:42:45 PM PDT 24
Peak memory 248536 kb
Host smart-87e90224-c0d3-404f-a0eb-486c1508f2b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1454237330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.1454237330
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.1341683834
Short name T195
Test name
Test status
Simulation time 185024653 ps
CPU time 23.7 seconds
Started Mar 17 02:42:04 PM PDT 24
Finished Mar 17 02:42:28 PM PDT 24
Peak memory 244940 kb
Host smart-6ad2bd7d-4d02-4278-b52e-9a5902d20009
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1341683834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.1341683834
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.3161354956
Short name T198
Test name
Test status
Simulation time 899170995 ps
CPU time 38.84 seconds
Started Mar 17 02:41:28 PM PDT 24
Finished Mar 17 02:42:07 PM PDT 24
Peak memory 236980 kb
Host smart-65f7a1bc-bec2-4eb1-ad80-4bf68a34c776
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3161354956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.3161354956
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.764441642
Short name T204
Test name
Test status
Simulation time 50527658 ps
CPU time 3.22 seconds
Started Mar 17 02:41:32 PM PDT 24
Finished Mar 17 02:41:36 PM PDT 24
Peak memory 237656 kb
Host smart-6df52a40-b5ea-4bbb-9d00-6e992f484c8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=764441642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.764441642
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.4119975123
Short name T201
Test name
Test status
Simulation time 1639479765 ps
CPU time 35.85 seconds
Started Mar 17 02:41:47 PM PDT 24
Finished Mar 17 02:42:23 PM PDT 24
Peak memory 236964 kb
Host smart-8089c3ee-6725-46b2-b6af-aa1690114af3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4119975123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.4119975123
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.207104645
Short name T723
Test name
Test status
Simulation time 19571892654 ps
CPU time 334.21 seconds
Started Mar 17 02:41:27 PM PDT 24
Finished Mar 17 02:47:01 PM PDT 24
Peak memory 240368 kb
Host smart-ed8c1782-85fe-4a92-810a-ad6a32be46fa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=207104645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.207104645
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3355348586
Short name T794
Test name
Test status
Simulation time 83119271 ps
CPU time 5.68 seconds
Started Mar 17 02:41:20 PM PDT 24
Finished Mar 17 02:41:26 PM PDT 24
Peak memory 240176 kb
Host smart-dfa20d16-0ecd-4c7a-a10f-c8e22485057d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3355348586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.3355348586
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.2161653656
Short name T752
Test name
Test status
Simulation time 560886332 ps
CPU time 11.98 seconds
Started Mar 17 02:41:21 PM PDT 24
Finished Mar 17 02:41:33 PM PDT 24
Peak memory 252572 kb
Host smart-7c13cd1f-0a03-4749-974c-2fecf0d90878
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161653656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.2161653656
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.3014408652
Short name T824
Test name
Test status
Simulation time 49591903 ps
CPU time 5.41 seconds
Started Mar 17 02:41:22 PM PDT 24
Finished Mar 17 02:41:28 PM PDT 24
Peak memory 236580 kb
Host smart-839092c1-777a-49a3-9dad-28bef8e2faab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3014408652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.3014408652
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.104312151
Short name T187
Test name
Test status
Simulation time 6515287 ps
CPU time 1.39 seconds
Started Mar 17 02:41:28 PM PDT 24
Finished Mar 17 02:41:29 PM PDT 24
Peak memory 234704 kb
Host smart-1f9354f8-3929-4e7d-b036-84386b0bca6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=104312151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.104312151
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1402088752
Short name T772
Test name
Test status
Simulation time 87678452 ps
CPU time 12.61 seconds
Started Mar 17 02:41:22 PM PDT 24
Finished Mar 17 02:41:35 PM PDT 24
Peak memory 244832 kb
Host smart-19132244-841e-4011-b1ec-22c443e79807
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1402088752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.1402088752
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.419939812
Short name T813
Test name
Test status
Simulation time 120313272 ps
CPU time 8.95 seconds
Started Mar 17 02:41:17 PM PDT 24
Finished Mar 17 02:41:26 PM PDT 24
Peak memory 248328 kb
Host smart-0738bab8-6c01-4083-8580-f4b5db1f7650
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=419939812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.419939812
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2664104330
Short name T738
Test name
Test status
Simulation time 3718940086 ps
CPU time 255.39 seconds
Started Mar 17 02:41:27 PM PDT 24
Finished Mar 17 02:45:43 PM PDT 24
Peak memory 240244 kb
Host smart-5ca21bc6-d5e4-47df-b0f6-359ea266dd4e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2664104330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.2664104330
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2101308141
Short name T759
Test name
Test status
Simulation time 5950295389 ps
CPU time 207.17 seconds
Started Mar 17 02:41:31 PM PDT 24
Finished Mar 17 02:44:58 PM PDT 24
Peak memory 236580 kb
Host smart-38e3ac66-a2a6-4028-a1f1-e0daa9788743
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2101308141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.2101308141
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.828568979
Short name T226
Test name
Test status
Simulation time 152711882 ps
CPU time 7.17 seconds
Started Mar 17 02:41:28 PM PDT 24
Finished Mar 17 02:41:35 PM PDT 24
Peak memory 240276 kb
Host smart-a3eca38f-422f-4103-89ff-02f90376af1a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=828568979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.828568979
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.2904465235
Short name T737
Test name
Test status
Simulation time 558251540 ps
CPU time 13.77 seconds
Started Mar 17 02:41:28 PM PDT 24
Finished Mar 17 02:41:42 PM PDT 24
Peak memory 256768 kb
Host smart-82e610d2-2504-4eda-847c-5a605d21a5ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904465235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.2904465235
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.2747862601
Short name T748
Test name
Test status
Simulation time 38966166 ps
CPU time 5.37 seconds
Started Mar 17 02:41:21 PM PDT 24
Finished Mar 17 02:41:27 PM PDT 24
Peak memory 240260 kb
Host smart-c0dda552-dd4a-4f33-af88-86b163bb5831
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2747862601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.2747862601
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.182285172
Short name T785
Test name
Test status
Simulation time 8683709 ps
CPU time 1.25 seconds
Started Mar 17 02:41:29 PM PDT 24
Finished Mar 17 02:41:30 PM PDT 24
Peak memory 236688 kb
Host smart-dcb89b0f-5587-4dce-8e4d-08e32c5e3d80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=182285172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.182285172
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.2825004381
Short name T743
Test name
Test status
Simulation time 1268438338 ps
CPU time 22.86 seconds
Started Mar 17 02:41:29 PM PDT 24
Finished Mar 17 02:41:51 PM PDT 24
Peak memory 244796 kb
Host smart-a0838072-4e16-4095-9d42-a4bf325b274a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2825004381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.2825004381
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2540282193
Short name T159
Test name
Test status
Simulation time 12033933537 ps
CPU time 131.49 seconds
Started Mar 17 02:41:28 PM PDT 24
Finished Mar 17 02:43:39 PM PDT 24
Peak memory 257048 kb
Host smart-eb76e122-a0fe-4034-8436-c439c93480df
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2540282193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.2540282193
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.3752951864
Short name T374
Test name
Test status
Simulation time 33163053259 ps
CPU time 603.72 seconds
Started Mar 17 02:41:28 PM PDT 24
Finished Mar 17 02:51:32 PM PDT 24
Peak memory 266236 kb
Host smart-52c935b4-6178-4e08-882a-63fd11f38fb1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752951864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.3752951864
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.3405472397
Short name T727
Test name
Test status
Simulation time 159667759 ps
CPU time 11.51 seconds
Started Mar 17 02:41:20 PM PDT 24
Finished Mar 17 02:41:32 PM PDT 24
Peak memory 251652 kb
Host smart-bd136bc7-893a-4907-a25b-f85a94e5509e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3405472397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.3405472397
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.3778199154
Short name T719
Test name
Test status
Simulation time 71369863 ps
CPU time 6.56 seconds
Started Mar 17 02:41:51 PM PDT 24
Finished Mar 17 02:41:58 PM PDT 24
Peak memory 239588 kb
Host smart-5e4b8495-16f9-42d6-bbfb-b4018b78bb42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778199154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.3778199154
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.2277257543
Short name T206
Test name
Test status
Simulation time 137035344 ps
CPU time 10.35 seconds
Started Mar 17 02:41:50 PM PDT 24
Finished Mar 17 02:42:01 PM PDT 24
Peak memory 240236 kb
Host smart-5acfbd7e-55f2-4f6a-9e31-0ba9d37a2303
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2277257543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.2277257543
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.984547785
Short name T720
Test name
Test status
Simulation time 7953556 ps
CPU time 1.64 seconds
Started Mar 17 02:41:51 PM PDT 24
Finished Mar 17 02:41:53 PM PDT 24
Peak memory 236600 kb
Host smart-4691713e-9c24-4b71-8152-78c96f4f8fa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=984547785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.984547785
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2667847157
Short name T769
Test name
Test status
Simulation time 690261308 ps
CPU time 25.63 seconds
Started Mar 17 02:41:52 PM PDT 24
Finished Mar 17 02:42:18 PM PDT 24
Peak memory 248512 kb
Host smart-9335a87e-72c0-47a1-b324-ba3e5ebad6a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2667847157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.2667847157
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3593953637
Short name T165
Test name
Test status
Simulation time 1184648513 ps
CPU time 101.59 seconds
Started Mar 17 02:41:47 PM PDT 24
Finished Mar 17 02:43:29 PM PDT 24
Peak memory 265108 kb
Host smart-c9ce17e8-0eb5-416d-bbc5-5c004c7409b7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3593953637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.3593953637
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.2230238957
Short name T735
Test name
Test status
Simulation time 189893749 ps
CPU time 15.38 seconds
Started Mar 17 02:41:51 PM PDT 24
Finished Mar 17 02:42:06 PM PDT 24
Peak memory 248368 kb
Host smart-2092abfa-fc67-494b-abc2-3ea2a40c9c80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2230238957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.2230238957
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3378615764
Short name T790
Test name
Test status
Simulation time 2620727624 ps
CPU time 12.61 seconds
Started Mar 17 02:42:04 PM PDT 24
Finished Mar 17 02:42:16 PM PDT 24
Peak memory 240404 kb
Host smart-d64ffbce-2aff-441e-aba3-128371508f4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378615764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.3378615764
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.3608686522
Short name T726
Test name
Test status
Simulation time 91751125 ps
CPU time 5.17 seconds
Started Mar 17 02:41:52 PM PDT 24
Finished Mar 17 02:41:58 PM PDT 24
Peak memory 238552 kb
Host smart-b7ac1858-926f-4234-bf77-6227423f503b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3608686522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.3608686522
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2874804933
Short name T763
Test name
Test status
Simulation time 7373381 ps
CPU time 1.34 seconds
Started Mar 17 02:41:51 PM PDT 24
Finished Mar 17 02:41:52 PM PDT 24
Peak memory 234768 kb
Host smart-ccc2a771-4c7b-4bbf-a650-b098d6f37ec2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2874804933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.2874804933
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.72444436
Short name T818
Test name
Test status
Simulation time 227184637 ps
CPU time 15.11 seconds
Started Mar 17 02:41:53 PM PDT 24
Finished Mar 17 02:42:08 PM PDT 24
Peak memory 240308 kb
Host smart-a3ae5f69-354b-4f79-b202-bc5c21958219
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=72444436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_outs
tanding.72444436
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.1498955520
Short name T163
Test name
Test status
Simulation time 3862630885 ps
CPU time 287.93 seconds
Started Mar 17 02:41:52 PM PDT 24
Finished Mar 17 02:46:40 PM PDT 24
Peak memory 265172 kb
Host smart-24523de9-5348-4668-ad6b-02de1e5e3f6f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1498955520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.1498955520
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.3640243840
Short name T710
Test name
Test status
Simulation time 183195923 ps
CPU time 7.7 seconds
Started Mar 17 02:41:52 PM PDT 24
Finished Mar 17 02:42:00 PM PDT 24
Peak memory 248576 kb
Host smart-f15f297d-0428-4c0a-955c-26282237155e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3640243840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.3640243840
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1197264194
Short name T782
Test name
Test status
Simulation time 151590739 ps
CPU time 6.42 seconds
Started Mar 17 02:41:58 PM PDT 24
Finished Mar 17 02:42:04 PM PDT 24
Peak memory 239880 kb
Host smart-a9caa83e-4479-4ae4-bb91-e3eef7447a52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197264194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.1197264194
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1469846743
Short name T718
Test name
Test status
Simulation time 25734205 ps
CPU time 3.74 seconds
Started Mar 17 02:42:03 PM PDT 24
Finished Mar 17 02:42:07 PM PDT 24
Peak memory 238348 kb
Host smart-e8221d6b-d11a-455a-949b-b663cb34e50e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1469846743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.1469846743
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.4268853637
Short name T786
Test name
Test status
Simulation time 10329411 ps
CPU time 1.37 seconds
Started Mar 17 02:41:57 PM PDT 24
Finished Mar 17 02:41:58 PM PDT 24
Peak memory 234768 kb
Host smart-0073d058-e956-4420-80a7-2698c731c370
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4268853637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.4268853637
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.3583639920
Short name T755
Test name
Test status
Simulation time 362719306 ps
CPU time 21.53 seconds
Started Mar 17 02:42:02 PM PDT 24
Finished Mar 17 02:42:23 PM PDT 24
Peak memory 244004 kb
Host smart-6a078097-2c41-4407-a47f-902a32af0609
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3583639920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.3583639920
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.886989432
Short name T172
Test name
Test status
Simulation time 8900435274 ps
CPU time 194.68 seconds
Started Mar 17 02:41:58 PM PDT 24
Finished Mar 17 02:45:13 PM PDT 24
Peak memory 266164 kb
Host smart-760dcec3-c8dd-4950-9258-fcfad73ebdec
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=886989432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_erro
rs.886989432
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.3562763489
Short name T744
Test name
Test status
Simulation time 384313610 ps
CPU time 7.55 seconds
Started Mar 17 02:41:59 PM PDT 24
Finished Mar 17 02:42:06 PM PDT 24
Peak memory 248580 kb
Host smart-731c9673-ab63-40f0-a470-0489eeff9c39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3562763489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.3562763489
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.3651516769
Short name T183
Test name
Test status
Simulation time 86928958 ps
CPU time 5.45 seconds
Started Mar 17 02:41:58 PM PDT 24
Finished Mar 17 02:42:04 PM PDT 24
Peak memory 237056 kb
Host smart-ab4065ad-7c9e-4a24-b48b-9b618e7cd407
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3651516769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.3651516769
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.929318556
Short name T756
Test name
Test status
Simulation time 66108999 ps
CPU time 12.76 seconds
Started Mar 17 02:42:02 PM PDT 24
Finished Mar 17 02:42:15 PM PDT 24
Peak memory 252628 kb
Host smart-ee4510cb-8490-428a-be2d-91b0ac319685
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929318556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.alert_handler_csr_mem_rw_with_rand_reset.929318556
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.809052343
Short name T375
Test name
Test status
Simulation time 98658752 ps
CPU time 8.76 seconds
Started Mar 17 02:42:00 PM PDT 24
Finished Mar 17 02:42:09 PM PDT 24
Peak memory 240304 kb
Host smart-48b5c5a8-574b-4d8f-849e-65e8d9bc5452
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=809052343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.809052343
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.1419668808
Short name T826
Test name
Test status
Simulation time 10603533 ps
CPU time 1.59 seconds
Started Mar 17 02:41:57 PM PDT 24
Finished Mar 17 02:41:59 PM PDT 24
Peak memory 235816 kb
Host smart-d4a775c8-3e48-455c-b23c-73ffeddf28d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1419668808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.1419668808
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2180295956
Short name T817
Test name
Test status
Simulation time 510754375 ps
CPU time 41.53 seconds
Started Mar 17 02:42:02 PM PDT 24
Finished Mar 17 02:42:44 PM PDT 24
Peak memory 248564 kb
Host smart-6b92ae92-045b-47ee-abf7-39c762774a38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2180295956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.2180295956
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2038424923
Short name T765
Test name
Test status
Simulation time 144576741 ps
CPU time 3.4 seconds
Started Mar 17 02:42:01 PM PDT 24
Finished Mar 17 02:42:05 PM PDT 24
Peak memory 248004 kb
Host smart-f8acf680-0343-4548-a2ba-1dffc7ea2209
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2038424923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.2038424923
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.4022803048
Short name T265
Test name
Test status
Simulation time 74781816 ps
CPU time 6.82 seconds
Started Mar 17 02:42:07 PM PDT 24
Finished Mar 17 02:42:14 PM PDT 24
Peak memory 240404 kb
Host smart-dc7bf85f-80e5-4e9b-aed9-86bb29b8dce8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022803048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.4022803048
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.2713925602
Short name T788
Test name
Test status
Simulation time 368544144 ps
CPU time 9.24 seconds
Started Mar 17 02:41:57 PM PDT 24
Finished Mar 17 02:42:06 PM PDT 24
Peak memory 236584 kb
Host smart-ee570f92-079f-46f6-b925-fa1008d8a128
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2713925602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.2713925602
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.4179580075
Short name T745
Test name
Test status
Simulation time 9812297 ps
CPU time 1.59 seconds
Started Mar 17 02:41:58 PM PDT 24
Finished Mar 17 02:42:00 PM PDT 24
Peak memory 236672 kb
Host smart-7e838acd-b3d2-4a58-8a56-081da8d6ef31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4179580075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.4179580075
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3009137560
Short name T816
Test name
Test status
Simulation time 1050888279 ps
CPU time 20.25 seconds
Started Mar 17 02:42:05 PM PDT 24
Finished Mar 17 02:42:26 PM PDT 24
Peak memory 244880 kb
Host smart-c814c2aa-79ce-402b-8e14-f510fb26c33a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3009137560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.3009137560
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.2432870332
Short name T177
Test name
Test status
Simulation time 2144851932 ps
CPU time 152.98 seconds
Started Mar 17 02:42:03 PM PDT 24
Finished Mar 17 02:44:36 PM PDT 24
Peak memory 256840 kb
Host smart-5c927e8d-51e2-429b-8a0c-6e3e92c9fbc9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2432870332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.2432870332
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.3437975485
Short name T764
Test name
Test status
Simulation time 74761493 ps
CPU time 3.2 seconds
Started Mar 17 02:41:59 PM PDT 24
Finished Mar 17 02:42:03 PM PDT 24
Peak memory 239832 kb
Host smart-45ce7e40-2c2d-4472-8640-45a51d825e20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3437975485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.3437975485
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.720642009
Short name T804
Test name
Test status
Simulation time 180261394 ps
CPU time 5.12 seconds
Started Mar 17 02:42:04 PM PDT 24
Finished Mar 17 02:42:10 PM PDT 24
Peak memory 238688 kb
Host smart-983f1718-8c29-4240-a94a-36d97215731e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720642009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.alert_handler_csr_mem_rw_with_rand_reset.720642009
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.755078122
Short name T825
Test name
Test status
Simulation time 216921537 ps
CPU time 3.98 seconds
Started Mar 17 02:42:04 PM PDT 24
Finished Mar 17 02:42:08 PM PDT 24
Peak memory 238628 kb
Host smart-c1030d9a-4433-4390-933a-b21406f531c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=755078122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.755078122
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.2919057627
Short name T711
Test name
Test status
Simulation time 6950940 ps
CPU time 1.47 seconds
Started Mar 17 02:42:03 PM PDT 24
Finished Mar 17 02:42:05 PM PDT 24
Peak memory 235772 kb
Host smart-1d328dad-2aa6-4ac9-97ac-16e0678bc41a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2919057627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.2919057627
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.904973691
Short name T742
Test name
Test status
Simulation time 2128876170 ps
CPU time 50.2 seconds
Started Mar 17 02:42:04 PM PDT 24
Finished Mar 17 02:42:55 PM PDT 24
Peak memory 244812 kb
Host smart-f2d93eb6-d85f-4143-b7b7-377deae01fc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=904973691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_out
standing.904973691
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1976426081
Short name T777
Test name
Test status
Simulation time 739079208 ps
CPU time 23.4 seconds
Started Mar 17 02:42:05 PM PDT 24
Finished Mar 17 02:42:29 PM PDT 24
Peak memory 253616 kb
Host smart-06a15068-f3ee-4859-bfde-b205d2a6bbad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1976426081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.1976426081
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1873693244
Short name T371
Test name
Test status
Simulation time 82329802 ps
CPU time 12.96 seconds
Started Mar 17 02:42:05 PM PDT 24
Finished Mar 17 02:42:18 PM PDT 24
Peak memory 256752 kb
Host smart-e68e1279-eb8c-4fbb-9ae9-c667c21bbb78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873693244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.1873693244
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1757276904
Short name T757
Test name
Test status
Simulation time 212103343 ps
CPU time 6.14 seconds
Started Mar 17 02:42:04 PM PDT 24
Finished Mar 17 02:42:10 PM PDT 24
Peak memory 240244 kb
Host smart-ef3163c5-7609-49a0-a882-a7ca86f1769f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1757276904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1757276904
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1136628882
Short name T731
Test name
Test status
Simulation time 12419531 ps
CPU time 1.47 seconds
Started Mar 17 02:42:04 PM PDT 24
Finished Mar 17 02:42:06 PM PDT 24
Peak memory 235752 kb
Host smart-f3b8abd6-1252-4a85-ad37-6828a390a9ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1136628882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1136628882
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1898903482
Short name T228
Test name
Test status
Simulation time 684560814 ps
CPU time 23.79 seconds
Started Mar 17 02:42:05 PM PDT 24
Finished Mar 17 02:42:29 PM PDT 24
Peak memory 244000 kb
Host smart-62e6eef8-b7fa-456f-9762-c3139d7598ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1898903482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.1898903482
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1206081333
Short name T162
Test name
Test status
Simulation time 8972949556 ps
CPU time 194.66 seconds
Started Mar 17 02:42:04 PM PDT 24
Finished Mar 17 02:45:19 PM PDT 24
Peak memory 265192 kb
Host smart-0e839ed8-a67a-4339-aac1-09de5512d192
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1206081333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.1206081333
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.2227242205
Short name T717
Test name
Test status
Simulation time 321402125 ps
CPU time 11.12 seconds
Started Mar 17 02:42:04 PM PDT 24
Finished Mar 17 02:42:15 PM PDT 24
Peak memory 248356 kb
Host smart-fa9017d4-f72b-4e99-8d71-fade9fe57a94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2227242205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.2227242205
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.963401353
Short name T791
Test name
Test status
Simulation time 295232646 ps
CPU time 7.63 seconds
Started Mar 17 02:42:16 PM PDT 24
Finished Mar 17 02:42:24 PM PDT 24
Peak memory 240384 kb
Host smart-47b403f9-c131-4310-9eb3-b7f16937bb68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963401353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.alert_handler_csr_mem_rw_with_rand_reset.963401353
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.1767010924
Short name T770
Test name
Test status
Simulation time 121397378 ps
CPU time 5.46 seconds
Started Mar 17 02:42:10 PM PDT 24
Finished Mar 17 02:42:16 PM PDT 24
Peak memory 235640 kb
Host smart-b919d92a-720f-418e-ad52-15232c27162e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1767010924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.1767010924
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.3951020142
Short name T803
Test name
Test status
Simulation time 10438159 ps
CPU time 1.43 seconds
Started Mar 17 02:42:16 PM PDT 24
Finished Mar 17 02:42:18 PM PDT 24
Peak memory 234740 kb
Host smart-f04caaf7-779b-4204-8e5a-f99a3b8364d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3951020142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.3951020142
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2033472979
Short name T789
Test name
Test status
Simulation time 523077742 ps
CPU time 21.84 seconds
Started Mar 17 02:42:10 PM PDT 24
Finished Mar 17 02:42:32 PM PDT 24
Peak memory 244856 kb
Host smart-7262cc1e-fd89-45af-9d86-03c3c08b18fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2033472979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.2033472979
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1426545045
Short name T173
Test name
Test status
Simulation time 9662500553 ps
CPU time 546.55 seconds
Started Mar 17 02:42:05 PM PDT 24
Finished Mar 17 02:51:12 PM PDT 24
Peak memory 265196 kb
Host smart-f8532e25-4297-414a-8506-fd0f16e110fd
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426545045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.1426545045
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.90220886
Short name T740
Test name
Test status
Simulation time 476288593 ps
CPU time 16.2 seconds
Started Mar 17 02:42:05 PM PDT 24
Finished Mar 17 02:42:22 PM PDT 24
Peak memory 252724 kb
Host smart-5532562f-7fa6-4d34-879b-95ff14d7a1e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=90220886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.90220886
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.2556647044
Short name T753
Test name
Test status
Simulation time 83965151 ps
CPU time 9.48 seconds
Started Mar 17 02:42:12 PM PDT 24
Finished Mar 17 02:42:22 PM PDT 24
Peak memory 255752 kb
Host smart-e5c27509-c853-44be-8738-a62289c5cb1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556647044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.2556647044
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.363118815
Short name T741
Test name
Test status
Simulation time 77046145 ps
CPU time 5.45 seconds
Started Mar 17 02:42:12 PM PDT 24
Finished Mar 17 02:42:18 PM PDT 24
Peak memory 236588 kb
Host smart-36b53a03-a76d-4bed-8380-2418c39f3085
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=363118815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.363118815
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.498957636
Short name T771
Test name
Test status
Simulation time 11794294 ps
CPU time 1.48 seconds
Started Mar 17 02:42:10 PM PDT 24
Finished Mar 17 02:42:12 PM PDT 24
Peak memory 236680 kb
Host smart-d7b8b96e-8091-44e2-a7dd-610646220b39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=498957636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.498957636
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3062264314
Short name T784
Test name
Test status
Simulation time 964995964 ps
CPU time 11.1 seconds
Started Mar 17 02:42:08 PM PDT 24
Finished Mar 17 02:42:19 PM PDT 24
Peak memory 240408 kb
Host smart-4b44564b-08a5-4fad-95da-fb8b02cd95c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3062264314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.3062264314
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1067263051
Short name T164
Test name
Test status
Simulation time 3375551288 ps
CPU time 217.8 seconds
Started Mar 17 02:42:09 PM PDT 24
Finished Mar 17 02:45:47 PM PDT 24
Peak memory 265172 kb
Host smart-76dfca3c-d183-48d2-a460-040c6b6cc835
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1067263051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.1067263051
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3908285915
Short name T709
Test name
Test status
Simulation time 320529697 ps
CPU time 7.89 seconds
Started Mar 17 02:42:08 PM PDT 24
Finished Mar 17 02:42:16 PM PDT 24
Peak memory 248120 kb
Host smart-fb4fe8b3-fb9e-4ce8-a4b5-dc9e36e15f1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3908285915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.3908285915
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.672474166
Short name T760
Test name
Test status
Simulation time 56160670 ps
CPU time 7.79 seconds
Started Mar 17 02:42:17 PM PDT 24
Finished Mar 17 02:42:25 PM PDT 24
Peak memory 250772 kb
Host smart-d0778074-804e-402a-8f34-8c38fb223609
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672474166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.alert_handler_csr_mem_rw_with_rand_reset.672474166
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.3443170227
Short name T766
Test name
Test status
Simulation time 367741005 ps
CPU time 8.74 seconds
Started Mar 17 02:42:09 PM PDT 24
Finished Mar 17 02:42:18 PM PDT 24
Peak memory 236612 kb
Host smart-d3ae0773-1ff5-43e3-ba27-5e353cb0b1b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3443170227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.3443170227
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.3522150188
Short name T734
Test name
Test status
Simulation time 12591845 ps
CPU time 1.38 seconds
Started Mar 17 02:42:10 PM PDT 24
Finished Mar 17 02:42:11 PM PDT 24
Peak memory 235832 kb
Host smart-00aaba36-0e37-451a-adb0-4293cdef948d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3522150188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.3522150188
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3485585499
Short name T795
Test name
Test status
Simulation time 331756864 ps
CPU time 21.3 seconds
Started Mar 17 02:42:16 PM PDT 24
Finished Mar 17 02:42:38 PM PDT 24
Peak memory 244820 kb
Host smart-375d2218-218e-4a0f-a91f-08c457b6a5a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3485585499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.3485585499
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.525101608
Short name T167
Test name
Test status
Simulation time 3346335246 ps
CPU time 228.21 seconds
Started Mar 17 02:42:09 PM PDT 24
Finished Mar 17 02:45:58 PM PDT 24
Peak memory 265152 kb
Host smart-fc4c2b8c-1aca-46e6-979d-a9b5fd11b5d7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=525101608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_erro
rs.525101608
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2608320097
Short name T175
Test name
Test status
Simulation time 18208947936 ps
CPU time 774.22 seconds
Started Mar 17 02:42:09 PM PDT 24
Finished Mar 17 02:55:03 PM PDT 24
Peak memory 265320 kb
Host smart-dd0a7e2b-25cd-4b89-83b4-793f92342e6d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608320097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.2608320097
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.382745190
Short name T725
Test name
Test status
Simulation time 308319808 ps
CPU time 14.69 seconds
Started Mar 17 02:42:07 PM PDT 24
Finished Mar 17 02:42:22 PM PDT 24
Peak memory 252400 kb
Host smart-08f319bb-0ed3-498f-b682-46576edec4e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=382745190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.382745190
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.4152936423
Short name T224
Test name
Test status
Simulation time 12333573884 ps
CPU time 345.4 seconds
Started Mar 17 02:41:31 PM PDT 24
Finished Mar 17 02:47:16 PM PDT 24
Peak memory 240732 kb
Host smart-ee913c43-9276-449f-aa4e-9da49f2f4d8a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4152936423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.4152936423
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2824126526
Short name T778
Test name
Test status
Simulation time 1705814457 ps
CPU time 92.49 seconds
Started Mar 17 02:41:32 PM PDT 24
Finished Mar 17 02:43:05 PM PDT 24
Peak memory 235688 kb
Host smart-01b4fd71-efc0-424b-b822-6a71c7bf580a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2824126526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.2824126526
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1841824489
Short name T783
Test name
Test status
Simulation time 88279039 ps
CPU time 3.76 seconds
Started Mar 17 02:41:32 PM PDT 24
Finished Mar 17 02:41:36 PM PDT 24
Peak memory 240244 kb
Host smart-b2ba4a6c-bb88-4784-9eeb-ccb3a56a3712
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1841824489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.1841824489
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3975262590
Short name T729
Test name
Test status
Simulation time 118749161 ps
CPU time 4.78 seconds
Started Mar 17 02:41:26 PM PDT 24
Finished Mar 17 02:41:31 PM PDT 24
Peak memory 252612 kb
Host smart-f85f5013-a292-4b69-91f4-4cba41f5ae86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975262590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.3975262590
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.4223225545
Short name T809
Test name
Test status
Simulation time 178509305 ps
CPU time 7.77 seconds
Started Mar 17 02:41:31 PM PDT 24
Finished Mar 17 02:41:39 PM PDT 24
Peak memory 235628 kb
Host smart-7d957ec3-da7a-4d39-8f5a-a4c11573b160
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4223225545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.4223225545
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.983105388
Short name T823
Test name
Test status
Simulation time 858721907 ps
CPU time 11.82 seconds
Started Mar 17 02:41:29 PM PDT 24
Finished Mar 17 02:41:40 PM PDT 24
Peak memory 243864 kb
Host smart-f97a1303-4681-4ee1-8e80-0b215d4a0d53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=983105388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outs
tanding.983105388
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.4061458831
Short name T774
Test name
Test status
Simulation time 134855878 ps
CPU time 14.31 seconds
Started Mar 17 02:41:27 PM PDT 24
Finished Mar 17 02:41:41 PM PDT 24
Peak memory 248584 kb
Host smart-be2979ca-466c-4a16-8f33-7f02fad7db9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4061458831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.4061458831
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.858443025
Short name T185
Test name
Test status
Simulation time 157199445 ps
CPU time 21.46 seconds
Started Mar 17 02:41:25 PM PDT 24
Finished Mar 17 02:41:47 PM PDT 24
Peak memory 236732 kb
Host smart-f09555eb-524a-4b5e-a206-0dc12b090dd3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=858443025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.858443025
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.741980167
Short name T730
Test name
Test status
Simulation time 10221222 ps
CPU time 1.59 seconds
Started Mar 17 02:42:11 PM PDT 24
Finished Mar 17 02:42:12 PM PDT 24
Peak memory 236696 kb
Host smart-61a02aec-c18d-4ae4-85f8-25df82773763
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=741980167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.741980167
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.573000538
Short name T776
Test name
Test status
Simulation time 9936810 ps
CPU time 1.26 seconds
Started Mar 17 02:42:14 PM PDT 24
Finished Mar 17 02:42:15 PM PDT 24
Peak memory 234732 kb
Host smart-98883218-34fa-44e7-956b-18bed86afee7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=573000538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.573000538
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.541480224
Short name T761
Test name
Test status
Simulation time 11637066 ps
CPU time 1.4 seconds
Started Mar 17 02:42:17 PM PDT 24
Finished Mar 17 02:42:18 PM PDT 24
Peak memory 235752 kb
Host smart-52d59c5c-e94a-463d-bebf-39a5e9a391b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=541480224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.541480224
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.511702092
Short name T793
Test name
Test status
Simulation time 8573974 ps
CPU time 1.56 seconds
Started Mar 17 02:42:09 PM PDT 24
Finished Mar 17 02:42:11 PM PDT 24
Peak memory 236692 kb
Host smart-8bae6d99-fa19-465a-8513-f1ec7f9a41c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=511702092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.511702092
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1954009554
Short name T799
Test name
Test status
Simulation time 24576129 ps
CPU time 1.47 seconds
Started Mar 17 02:42:10 PM PDT 24
Finished Mar 17 02:42:11 PM PDT 24
Peak memory 236672 kb
Host smart-a5c832a3-0b37-4e17-be73-4f20eed30975
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1954009554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.1954009554
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3748688572
Short name T780
Test name
Test status
Simulation time 11134597 ps
CPU time 1.25 seconds
Started Mar 17 02:42:14 PM PDT 24
Finished Mar 17 02:42:15 PM PDT 24
Peak memory 234756 kb
Host smart-c51cfaca-05cc-4b94-844e-19a9d4a1d2ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3748688572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.3748688572
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.53017360
Short name T781
Test name
Test status
Simulation time 14264170 ps
CPU time 1.48 seconds
Started Mar 17 02:42:15 PM PDT 24
Finished Mar 17 02:42:16 PM PDT 24
Peak memory 234824 kb
Host smart-01d7d55f-d4af-4075-b9bb-63d714d6439c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=53017360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.53017360
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.2158268931
Short name T819
Test name
Test status
Simulation time 10982699 ps
CPU time 1.4 seconds
Started Mar 17 02:42:14 PM PDT 24
Finished Mar 17 02:42:16 PM PDT 24
Peak memory 234792 kb
Host smart-3be754a6-5934-436a-b5b9-a0c3ad368ca8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2158268931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.2158268931
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.3157543580
Short name T270
Test name
Test status
Simulation time 10996238 ps
CPU time 1.75 seconds
Started Mar 17 02:42:15 PM PDT 24
Finished Mar 17 02:42:17 PM PDT 24
Peak memory 236696 kb
Host smart-8cdcc1b5-0a97-482d-ba55-af9bf2fe9a7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3157543580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.3157543580
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.3000729772
Short name T762
Test name
Test status
Simulation time 7606149 ps
CPU time 1.37 seconds
Started Mar 17 02:42:14 PM PDT 24
Finished Mar 17 02:42:15 PM PDT 24
Peak memory 236668 kb
Host smart-307c08e8-c0b7-4af2-b76a-1edd4c9b4614
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3000729772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.3000729772
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.4693524
Short name T827
Test name
Test status
Simulation time 7668743912 ps
CPU time 122.73 seconds
Started Mar 17 02:41:29 PM PDT 24
Finished Mar 17 02:43:32 PM PDT 24
Peak memory 240272 kb
Host smart-2c5e235c-304f-473f-b261-5093f3415656
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4693524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.4693524
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.1574635849
Short name T715
Test name
Test status
Simulation time 7774506004 ps
CPU time 203.39 seconds
Started Mar 17 02:41:29 PM PDT 24
Finished Mar 17 02:44:52 PM PDT 24
Peak memory 236636 kb
Host smart-7603426a-8c5c-4ccc-849f-7cd301695d8d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1574635849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.1574635849
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.298857927
Short name T779
Test name
Test status
Simulation time 1722373933 ps
CPU time 12.27 seconds
Started Mar 17 02:41:26 PM PDT 24
Finished Mar 17 02:41:38 PM PDT 24
Peak memory 240292 kb
Host smart-9a0adff2-eec3-4a30-883b-fc0a6505b57d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=298857927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.298857927
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2435614478
Short name T811
Test name
Test status
Simulation time 116078987 ps
CPU time 4.95 seconds
Started Mar 17 02:41:33 PM PDT 24
Finished Mar 17 02:41:38 PM PDT 24
Peak memory 239848 kb
Host smart-63d2ffd8-46ef-4773-a474-3e4657212f49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435614478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.2435614478
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2686359030
Short name T227
Test name
Test status
Simulation time 64034047 ps
CPU time 3.43 seconds
Started Mar 17 02:41:26 PM PDT 24
Finished Mar 17 02:41:30 PM PDT 24
Peak memory 235720 kb
Host smart-7625ff03-a0e0-449e-8807-18906351ab9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2686359030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.2686359030
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1733518378
Short name T188
Test name
Test status
Simulation time 27625539 ps
CPU time 1.42 seconds
Started Mar 17 02:41:27 PM PDT 24
Finished Mar 17 02:41:28 PM PDT 24
Peak memory 236664 kb
Host smart-662b6b6d-efdf-4858-8d6e-ed2e92079bd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1733518378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.1733518378
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2602954158
Short name T205
Test name
Test status
Simulation time 173450690 ps
CPU time 11.71 seconds
Started Mar 17 02:41:33 PM PDT 24
Finished Mar 17 02:41:45 PM PDT 24
Peak memory 243952 kb
Host smart-177d964d-688c-45bb-9dfa-089cdd8f7f3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2602954158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.2602954158
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.3433631358
Short name T160
Test name
Test status
Simulation time 1798295039 ps
CPU time 115.87 seconds
Started Mar 17 02:41:29 PM PDT 24
Finished Mar 17 02:43:25 PM PDT 24
Peak memory 266124 kb
Host smart-daa4235d-2765-4bd3-941a-e6c3995fa254
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3433631358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.3433631358
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1430656441
Short name T166
Test name
Test status
Simulation time 55076867471 ps
CPU time 666.46 seconds
Started Mar 17 02:41:27 PM PDT 24
Finished Mar 17 02:52:33 PM PDT 24
Peak memory 271944 kb
Host smart-5e4e0621-11ef-409e-9b65-0a74dbf6cb98
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430656441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.1430656441
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2945822589
Short name T269
Test name
Test status
Simulation time 171324253 ps
CPU time 11.94 seconds
Started Mar 17 02:41:28 PM PDT 24
Finished Mar 17 02:41:40 PM PDT 24
Peak memory 247316 kb
Host smart-b2fd3fb0-a1d3-4273-a647-2f6f085d29cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2945822589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2945822589
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.2135741323
Short name T792
Test name
Test status
Simulation time 11493574 ps
CPU time 1.77 seconds
Started Mar 17 02:42:15 PM PDT 24
Finished Mar 17 02:42:17 PM PDT 24
Peak memory 236644 kb
Host smart-0809a338-7908-4de8-8c0f-f01339618aa8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2135741323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.2135741323
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.1828443336
Short name T812
Test name
Test status
Simulation time 14530772 ps
CPU time 1.88 seconds
Started Mar 17 02:42:16 PM PDT 24
Finished Mar 17 02:42:19 PM PDT 24
Peak memory 236696 kb
Host smart-b0f59d90-fe13-4432-afe0-9d10214020d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1828443336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.1828443336
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.2211147840
Short name T186
Test name
Test status
Simulation time 12481852 ps
CPU time 1.61 seconds
Started Mar 17 02:42:15 PM PDT 24
Finished Mar 17 02:42:17 PM PDT 24
Peak memory 234840 kb
Host smart-3fff53ab-ba73-4c5c-b2dc-df77376ca6b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2211147840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.2211147840
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.34047797
Short name T367
Test name
Test status
Simulation time 11377364 ps
CPU time 1.35 seconds
Started Mar 17 02:42:13 PM PDT 24
Finished Mar 17 02:42:15 PM PDT 24
Peak memory 236588 kb
Host smart-00a1166f-a357-4cde-9842-c2d19b86c058
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=34047797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.34047797
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.177431546
Short name T820
Test name
Test status
Simulation time 59313748 ps
CPU time 1.31 seconds
Started Mar 17 02:42:14 PM PDT 24
Finished Mar 17 02:42:15 PM PDT 24
Peak memory 236464 kb
Host smart-d6630941-b69b-479a-b3ce-0db643e2cacd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=177431546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.177431546
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3288545721
Short name T807
Test name
Test status
Simulation time 8154756 ps
CPU time 1.45 seconds
Started Mar 17 02:42:14 PM PDT 24
Finished Mar 17 02:42:16 PM PDT 24
Peak memory 236648 kb
Host smart-2639164c-fb58-4042-bd88-a05fa2135756
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3288545721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3288545721
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.45562230
Short name T716
Test name
Test status
Simulation time 10615644 ps
CPU time 1.32 seconds
Started Mar 17 02:42:14 PM PDT 24
Finished Mar 17 02:42:16 PM PDT 24
Peak memory 236644 kb
Host smart-ab89fe6f-3173-4e3e-9c7e-cb4edc2fc42c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=45562230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.45562230
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3095814659
Short name T800
Test name
Test status
Simulation time 9579574 ps
CPU time 1.31 seconds
Started Mar 17 02:42:14 PM PDT 24
Finished Mar 17 02:42:15 PM PDT 24
Peak memory 235776 kb
Host smart-6f962e31-63d2-4803-9eca-f78011804208
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3095814659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.3095814659
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3752546638
Short name T787
Test name
Test status
Simulation time 14383181 ps
CPU time 1.71 seconds
Started Mar 17 02:42:13 PM PDT 24
Finished Mar 17 02:42:15 PM PDT 24
Peak memory 236600 kb
Host smart-8fd8fae0-6b3c-4e3d-a15e-2f67519176c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3752546638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.3752546638
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.291221422
Short name T366
Test name
Test status
Simulation time 13556098 ps
CPU time 1.39 seconds
Started Mar 17 02:42:13 PM PDT 24
Finished Mar 17 02:42:15 PM PDT 24
Peak memory 234844 kb
Host smart-fedadfc4-fa59-4010-b8d3-11cadb40523f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=291221422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.291221422
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2588349244
Short name T747
Test name
Test status
Simulation time 2380738859 ps
CPU time 170.08 seconds
Started Mar 17 02:41:34 PM PDT 24
Finished Mar 17 02:44:24 PM PDT 24
Peak memory 240304 kb
Host smart-2cb92c08-89d9-4a1b-8303-ed57cd73e535
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2588349244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.2588349244
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.611541773
Short name T822
Test name
Test status
Simulation time 12558585173 ps
CPU time 271.45 seconds
Started Mar 17 02:41:34 PM PDT 24
Finished Mar 17 02:46:05 PM PDT 24
Peak memory 236700 kb
Host smart-467f05d6-df83-4238-a436-f329322b926b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=611541773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.611541773
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.124230669
Short name T751
Test name
Test status
Simulation time 106503410 ps
CPU time 9.56 seconds
Started Mar 17 02:41:35 PM PDT 24
Finished Mar 17 02:41:44 PM PDT 24
Peak memory 240256 kb
Host smart-5da80510-4442-4eff-80b2-4cb9c0d5fd93
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=124230669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.124230669
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1781138036
Short name T372
Test name
Test status
Simulation time 161951570 ps
CPU time 5.75 seconds
Started Mar 17 02:41:36 PM PDT 24
Finished Mar 17 02:41:42 PM PDT 24
Peak memory 256756 kb
Host smart-df2df314-162a-4971-8552-9433059d3938
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781138036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.1781138036
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.3269074846
Short name T714
Test name
Test status
Simulation time 19693913 ps
CPU time 3.36 seconds
Started Mar 17 02:41:32 PM PDT 24
Finished Mar 17 02:41:36 PM PDT 24
Peak memory 238392 kb
Host smart-f5dfeaba-c483-4252-a8bf-9242a41f9625
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3269074846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.3269074846
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.582794808
Short name T773
Test name
Test status
Simulation time 20177836 ps
CPU time 1.54 seconds
Started Mar 17 02:41:33 PM PDT 24
Finished Mar 17 02:41:34 PM PDT 24
Peak memory 235828 kb
Host smart-9270aed8-687a-4472-b2ec-2acf610d0778
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=582794808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.582794808
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3758792114
Short name T207
Test name
Test status
Simulation time 676589769 ps
CPU time 55.47 seconds
Started Mar 17 02:41:32 PM PDT 24
Finished Mar 17 02:42:27 PM PDT 24
Peak memory 244760 kb
Host smart-a69fed0a-7008-4e6c-a2f7-59b224910fb1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3758792114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.3758792114
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1848489440
Short name T158
Test name
Test status
Simulation time 4186019395 ps
CPU time 290.8 seconds
Started Mar 17 02:41:35 PM PDT 24
Finished Mar 17 02:46:26 PM PDT 24
Peak memory 265100 kb
Host smart-25d06a6a-68ea-4b02-b508-2694e0982bfc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1848489440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.1848489440
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.519008151
Short name T149
Test name
Test status
Simulation time 6638018726 ps
CPU time 556.42 seconds
Started Mar 17 02:41:32 PM PDT 24
Finished Mar 17 02:50:49 PM PDT 24
Peak memory 265228 kb
Host smart-91120f24-f168-4b0a-ab15-5d73a00a7506
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519008151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.519008151
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2818365074
Short name T749
Test name
Test status
Simulation time 330251506 ps
CPU time 7.5 seconds
Started Mar 17 02:41:33 PM PDT 24
Finished Mar 17 02:41:41 PM PDT 24
Peak memory 248480 kb
Host smart-26e249df-b79e-42b5-867c-a9bfb7853a9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2818365074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.2818365074
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1839523232
Short name T808
Test name
Test status
Simulation time 246674765 ps
CPU time 4.78 seconds
Started Mar 17 02:41:33 PM PDT 24
Finished Mar 17 02:41:38 PM PDT 24
Peak memory 236984 kb
Host smart-1ddffd76-329f-489f-aa7f-2a7abc7ef829
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1839523232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.1839523232
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.386388942
Short name T815
Test name
Test status
Simulation time 6955458 ps
CPU time 1.4 seconds
Started Mar 17 02:42:17 PM PDT 24
Finished Mar 17 02:42:19 PM PDT 24
Peak memory 234756 kb
Host smart-7c696869-f82d-4708-990e-3224dabad518
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=386388942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.386388942
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.2321569500
Short name T768
Test name
Test status
Simulation time 16429941 ps
CPU time 1.78 seconds
Started Mar 17 02:42:16 PM PDT 24
Finished Mar 17 02:42:19 PM PDT 24
Peak memory 234756 kb
Host smart-7ce8a1a2-4e25-45e3-b7c8-cc0983be0b6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2321569500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.2321569500
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.3421499991
Short name T363
Test name
Test status
Simulation time 10633596 ps
CPU time 1.35 seconds
Started Mar 17 02:42:16 PM PDT 24
Finished Mar 17 02:42:18 PM PDT 24
Peak memory 236648 kb
Host smart-a2adc138-2524-4de4-8a20-8b85ae1268f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3421499991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.3421499991
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.2122268851
Short name T750
Test name
Test status
Simulation time 7272286 ps
CPU time 1.47 seconds
Started Mar 17 02:42:20 PM PDT 24
Finished Mar 17 02:42:22 PM PDT 24
Peak memory 236632 kb
Host smart-e7d992ba-7b67-4779-b320-4bcde2cb3236
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2122268851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.2122268851
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.1136072964
Short name T798
Test name
Test status
Simulation time 20761969 ps
CPU time 2.06 seconds
Started Mar 17 02:42:20 PM PDT 24
Finished Mar 17 02:42:23 PM PDT 24
Peak memory 235828 kb
Host smart-aa51d86b-d42b-408b-9a60-c070adf8a9a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1136072964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.1136072964
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.4249759476
Short name T758
Test name
Test status
Simulation time 46073953 ps
CPU time 1.4 seconds
Started Mar 17 02:42:20 PM PDT 24
Finished Mar 17 02:42:22 PM PDT 24
Peak memory 236496 kb
Host smart-e23f45dc-9e12-4b8b-a848-a5b7ffe0bae4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4249759476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.4249759476
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.3593810720
Short name T736
Test name
Test status
Simulation time 21318949 ps
CPU time 1.91 seconds
Started Mar 17 02:42:21 PM PDT 24
Finished Mar 17 02:42:24 PM PDT 24
Peak memory 236696 kb
Host smart-f79c4d18-a5b1-4941-a85b-250fde61e02e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3593810720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.3593810720
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.3624045680
Short name T712
Test name
Test status
Simulation time 14406989 ps
CPU time 1.72 seconds
Started Mar 17 02:42:19 PM PDT 24
Finished Mar 17 02:42:22 PM PDT 24
Peak memory 236660 kb
Host smart-8297b58c-02bb-4754-8ce4-3a17c6e65adc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3624045680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.3624045680
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.1386993165
Short name T370
Test name
Test status
Simulation time 94050531 ps
CPU time 9.45 seconds
Started Mar 17 02:41:38 PM PDT 24
Finished Mar 17 02:41:48 PM PDT 24
Peak memory 237192 kb
Host smart-347b39c2-da5e-4646-a206-864fe14fe570
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386993165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.1386993165
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.2236378536
Short name T801
Test name
Test status
Simulation time 906801675 ps
CPU time 4.56 seconds
Started Mar 17 02:41:36 PM PDT 24
Finished Mar 17 02:41:40 PM PDT 24
Peak memory 235604 kb
Host smart-6ac14037-51cd-4b91-80f6-65040768f293
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2236378536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.2236378536
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.790432498
Short name T365
Test name
Test status
Simulation time 18464197 ps
CPU time 1.47 seconds
Started Mar 17 02:41:35 PM PDT 24
Finished Mar 17 02:41:36 PM PDT 24
Peak memory 236648 kb
Host smart-f7f615f5-66ba-4482-9f03-a6eff9384c9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=790432498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.790432498
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.4060242537
Short name T806
Test name
Test status
Simulation time 904195481 ps
CPU time 24.96 seconds
Started Mar 17 02:41:39 PM PDT 24
Finished Mar 17 02:42:04 PM PDT 24
Peak memory 240320 kb
Host smart-ccf30812-d8a0-4ace-91cb-5a5a4d2424ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4060242537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.4060242537
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.2160371191
Short name T147
Test name
Test status
Simulation time 5938808775 ps
CPU time 320.28 seconds
Started Mar 17 02:41:35 PM PDT 24
Finished Mar 17 02:46:55 PM PDT 24
Peak memory 265092 kb
Host smart-bb1c21f8-d548-4618-ae86-c4ab9d7ba6a0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2160371191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.2160371191
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3231706111
Short name T168
Test name
Test status
Simulation time 27716408124 ps
CPU time 767.42 seconds
Started Mar 17 02:41:33 PM PDT 24
Finished Mar 17 02:54:20 PM PDT 24
Peak memory 273260 kb
Host smart-6dc51674-c40d-4797-b7f6-2f1351dcce91
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231706111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.3231706111
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.630710584
Short name T708
Test name
Test status
Simulation time 93216569 ps
CPU time 4.2 seconds
Started Mar 17 02:41:36 PM PDT 24
Finished Mar 17 02:41:40 PM PDT 24
Peak memory 248636 kb
Host smart-268d84cd-ade6-4c42-88e9-2c4383f592ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=630710584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.630710584
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3197577247
Short name T802
Test name
Test status
Simulation time 30605704 ps
CPU time 5.3 seconds
Started Mar 17 02:41:39 PM PDT 24
Finished Mar 17 02:41:44 PM PDT 24
Peak memory 238760 kb
Host smart-a7e4c6b4-bf84-43c5-b6ea-2ef9d3ffc68b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197577247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.3197577247
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3234020283
Short name T810
Test name
Test status
Simulation time 168621398 ps
CPU time 8.84 seconds
Started Mar 17 02:41:39 PM PDT 24
Finished Mar 17 02:41:48 PM PDT 24
Peak memory 236580 kb
Host smart-0abbb07a-c1cc-4a7f-92f5-5c5d54231011
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3234020283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.3234020283
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3917436961
Short name T775
Test name
Test status
Simulation time 8671711 ps
CPU time 1.37 seconds
Started Mar 17 02:41:40 PM PDT 24
Finished Mar 17 02:41:42 PM PDT 24
Peak memory 235812 kb
Host smart-a208746f-ad0b-4321-b8c3-b6b728e281d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3917436961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.3917436961
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2466990104
Short name T225
Test name
Test status
Simulation time 2521495444 ps
CPU time 45.02 seconds
Started Mar 17 02:41:39 PM PDT 24
Finished Mar 17 02:42:24 PM PDT 24
Peak memory 244036 kb
Host smart-789881f0-9625-4110-bb69-9d3114973a98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2466990104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.2466990104
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3874534258
Short name T373
Test name
Test status
Simulation time 8117061580 ps
CPU time 345.54 seconds
Started Mar 17 02:41:38 PM PDT 24
Finished Mar 17 02:47:24 PM PDT 24
Peak memory 265148 kb
Host smart-e548c539-161c-48c0-ab3a-562a3d76c86a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874534258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.3874534258
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.33001724
Short name T767
Test name
Test status
Simulation time 50977420 ps
CPU time 7.95 seconds
Started Mar 17 02:41:38 PM PDT 24
Finished Mar 17 02:41:46 PM PDT 24
Peak memory 248540 kb
Host smart-05efeb1a-4804-4c97-86bf-ffd2f8ab0191
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=33001724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.33001724
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.2464311893
Short name T746
Test name
Test status
Simulation time 74828337 ps
CPU time 6.29 seconds
Started Mar 17 02:41:42 PM PDT 24
Finished Mar 17 02:41:49 PM PDT 24
Peak memory 240340 kb
Host smart-3c810445-2b41-4b7e-ace2-fc8e470882eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464311893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.2464311893
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1468417469
Short name T721
Test name
Test status
Simulation time 401997111 ps
CPU time 11 seconds
Started Mar 17 02:41:38 PM PDT 24
Finished Mar 17 02:41:49 PM PDT 24
Peak memory 240240 kb
Host smart-92165dc3-4438-42fb-a1c4-a99cb512d8e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1468417469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.1468417469
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.2127689705
Short name T722
Test name
Test status
Simulation time 25465502 ps
CPU time 1.24 seconds
Started Mar 17 02:41:39 PM PDT 24
Finished Mar 17 02:41:40 PM PDT 24
Peak memory 236508 kb
Host smart-a0d19761-aed0-4391-bd4f-5bea502551b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2127689705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.2127689705
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.539847180
Short name T796
Test name
Test status
Simulation time 400193677 ps
CPU time 16.85 seconds
Started Mar 17 02:41:42 PM PDT 24
Finished Mar 17 02:41:59 PM PDT 24
Peak memory 248484 kb
Host smart-06dd43bb-b129-44e3-a0e4-668f1cb4499a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=539847180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_outs
tanding.539847180
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1738736318
Short name T181
Test name
Test status
Simulation time 7210746061 ps
CPU time 168.31 seconds
Started Mar 17 02:41:37 PM PDT 24
Finished Mar 17 02:44:26 PM PDT 24
Peak memory 265212 kb
Host smart-d4016ce1-b986-4588-aab1-b64533a50d47
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1738736318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.1738736318
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3792107048
Short name T161
Test name
Test status
Simulation time 30528340063 ps
CPU time 569.52 seconds
Started Mar 17 02:41:40 PM PDT 24
Finished Mar 17 02:51:10 PM PDT 24
Peak memory 267648 kb
Host smart-29f1e8f3-143f-48b5-ad56-37e9aca7686d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792107048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.3792107048
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2437422013
Short name T797
Test name
Test status
Simulation time 381220690 ps
CPU time 7.56 seconds
Started Mar 17 02:41:39 PM PDT 24
Finished Mar 17 02:41:47 PM PDT 24
Peak memory 251328 kb
Host smart-c7a6b6ea-ba35-4664-90ab-a19884f03c49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2437422013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.2437422013
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.626704376
Short name T369
Test name
Test status
Simulation time 104226279 ps
CPU time 5.49 seconds
Started Mar 17 02:41:44 PM PDT 24
Finished Mar 17 02:41:50 PM PDT 24
Peak memory 252836 kb
Host smart-808d78ad-2998-4a91-937f-d19f5ae0a15c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626704376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.alert_handler_csr_mem_rw_with_rand_reset.626704376
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.3852800497
Short name T724
Test name
Test status
Simulation time 69793021 ps
CPU time 4.01 seconds
Started Mar 17 02:41:45 PM PDT 24
Finished Mar 17 02:41:49 PM PDT 24
Peak memory 236564 kb
Host smart-4e30d69a-a1b0-4cf1-a12c-7f7eee3ab80e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3852800497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.3852800497
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1164148397
Short name T821
Test name
Test status
Simulation time 11249272 ps
CPU time 1.62 seconds
Started Mar 17 02:41:45 PM PDT 24
Finished Mar 17 02:41:48 PM PDT 24
Peak memory 236704 kb
Host smart-00281027-19e8-40ab-87d0-a347e031e6d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1164148397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.1164148397
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.845090625
Short name T713
Test name
Test status
Simulation time 666974565 ps
CPU time 50.29 seconds
Started Mar 17 02:41:48 PM PDT 24
Finished Mar 17 02:42:38 PM PDT 24
Peak memory 244796 kb
Host smart-9f978bc9-4b0d-4070-956d-4d377f287c45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=845090625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outs
tanding.845090625
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.1915155970
Short name T182
Test name
Test status
Simulation time 23616868101 ps
CPU time 954.94 seconds
Started Mar 17 02:41:44 PM PDT 24
Finished Mar 17 02:57:40 PM PDT 24
Peak memory 265392 kb
Host smart-e5f744c6-26e1-44d9-8ab8-05f2329b900c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915155970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.1915155970
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.2767808713
Short name T754
Test name
Test status
Simulation time 269065462 ps
CPU time 8.63 seconds
Started Mar 17 02:41:44 PM PDT 24
Finished Mar 17 02:41:53 PM PDT 24
Peak memory 252656 kb
Host smart-e2395e42-ac85-4f9a-bfce-aa2dbbd936b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2767808713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.2767808713
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2468152542
Short name T739
Test name
Test status
Simulation time 261516154 ps
CPU time 10.11 seconds
Started Mar 17 02:41:45 PM PDT 24
Finished Mar 17 02:41:56 PM PDT 24
Peak memory 240400 kb
Host smart-f8c4b6c4-bd0c-4034-9a10-24f690b5e3b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468152542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.2468152542
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.744692915
Short name T805
Test name
Test status
Simulation time 115738288 ps
CPU time 8.76 seconds
Started Mar 17 02:41:43 PM PDT 24
Finished Mar 17 02:41:52 PM PDT 24
Peak memory 235712 kb
Host smart-5677b402-1892-4135-ae53-edb060292c47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=744692915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.744692915
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.186242825
Short name T814
Test name
Test status
Simulation time 9804533 ps
CPU time 1.61 seconds
Started Mar 17 02:41:46 PM PDT 24
Finished Mar 17 02:41:48 PM PDT 24
Peak memory 235868 kb
Host smart-03d61757-f756-4b01-a561-60bd6452a48f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=186242825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.186242825
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1024205154
Short name T733
Test name
Test status
Simulation time 339361252 ps
CPU time 26.01 seconds
Started Mar 17 02:41:45 PM PDT 24
Finished Mar 17 02:42:11 PM PDT 24
Peak memory 248584 kb
Host smart-266146b1-c938-46a4-adea-7813ea51c7fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1024205154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1024205154
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.975334556
Short name T171
Test name
Test status
Simulation time 6440906158 ps
CPU time 494.27 seconds
Started Mar 17 02:41:45 PM PDT 24
Finished Mar 17 02:50:01 PM PDT 24
Peak memory 265204 kb
Host smart-346e4101-6dbe-44cc-b66c-cd1e039f88f1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975334556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.975334556
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1772364679
Short name T728
Test name
Test status
Simulation time 179449772 ps
CPU time 13.38 seconds
Started Mar 17 02:41:47 PM PDT 24
Finished Mar 17 02:42:01 PM PDT 24
Peak memory 248348 kb
Host smart-a95a8f3d-01ab-4f9e-9bd0-75dea8983927
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1772364679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.1772364679
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.4102382921
Short name T548
Test name
Test status
Simulation time 443492608 ps
CPU time 15.86 seconds
Started Mar 17 02:14:45 PM PDT 24
Finished Mar 17 02:15:02 PM PDT 24
Peak memory 240560 kb
Host smart-8692fe00-048e-4737-a9e6-0963d131d7ee
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4102382921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.4102382921
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.813895367
Short name T37
Test name
Test status
Simulation time 2079258678 ps
CPU time 69.42 seconds
Started Mar 17 02:14:45 PM PDT 24
Finished Mar 17 02:15:55 PM PDT 24
Peak memory 256756 kb
Host smart-3fc90a87-d972-44f1-8ef5-5743101bb1ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81389
5367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.813895367
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.1279102293
Short name T125
Test name
Test status
Simulation time 3094392849 ps
CPU time 43.03 seconds
Started Mar 17 02:14:47 PM PDT 24
Finished Mar 17 02:15:31 PM PDT 24
Peak memory 255612 kb
Host smart-6b99f2e3-a230-496d-a1e0-65df5e4de705
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12791
02293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.1279102293
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.878549938
Short name T128
Test name
Test status
Simulation time 178268840690 ps
CPU time 1923.44 seconds
Started Mar 17 02:14:44 PM PDT 24
Finished Mar 17 02:46:48 PM PDT 24
Peak memory 270544 kb
Host smart-caa17bb3-2fd6-4f48-8a48-d47848d84915
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878549938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.878549938
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.401088548
Short name T340
Test name
Test status
Simulation time 57266436652 ps
CPU time 617.28 seconds
Started Mar 17 02:14:47 PM PDT 24
Finished Mar 17 02:25:05 PM PDT 24
Peak memory 247096 kb
Host smart-f97ac395-600a-473a-afdf-aa4bb4d49da1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401088548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.401088548
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.3078399988
Short name T217
Test name
Test status
Simulation time 4546088131 ps
CPU time 35.64 seconds
Started Mar 17 02:14:44 PM PDT 24
Finished Mar 17 02:15:20 PM PDT 24
Peak memory 257128 kb
Host smart-7869b031-2508-49d6-b8f9-20ca5aeb726f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30783
99988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.3078399988
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.84054520
Short name T404
Test name
Test status
Simulation time 2178086781 ps
CPU time 39.11 seconds
Started Mar 17 02:14:47 PM PDT 24
Finished Mar 17 02:15:27 PM PDT 24
Peak memory 247964 kb
Host smart-af397a91-717f-48a2-aeed-09faf720bf81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84054
520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.84054520
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.1332550064
Short name T12
Test name
Test status
Simulation time 743851157 ps
CPU time 10.87 seconds
Started Mar 17 02:14:43 PM PDT 24
Finished Mar 17 02:14:54 PM PDT 24
Peak memory 277660 kb
Host smart-e14fb007-f755-42a1-a7fe-d8af4286240b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1332550064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.1332550064
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.1146946113
Short name T139
Test name
Test status
Simulation time 994551062 ps
CPU time 60.54 seconds
Started Mar 17 02:14:44 PM PDT 24
Finished Mar 17 02:15:45 PM PDT 24
Peak memory 248904 kb
Host smart-792000fb-5d3e-4582-ba1d-13d15c5dc5f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11469
46113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.1146946113
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.812632833
Short name T655
Test name
Test status
Simulation time 3343303182 ps
CPU time 54.8 seconds
Started Mar 17 02:14:43 PM PDT 24
Finished Mar 17 02:15:38 PM PDT 24
Peak memory 256748 kb
Host smart-e0132203-0c3a-4d4e-9592-c3e56de44b52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81263
2833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.812632833
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.1918468124
Short name T288
Test name
Test status
Simulation time 33501169613 ps
CPU time 2200.62 seconds
Started Mar 17 02:14:45 PM PDT 24
Finished Mar 17 02:51:25 PM PDT 24
Peak memory 289188 kb
Host smart-ef9ff887-6924-4999-be08-19c175a30809
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918468124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.1918468124
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.4263528212
Short name T397
Test name
Test status
Simulation time 63498492166 ps
CPU time 2135.85 seconds
Started Mar 17 02:14:44 PM PDT 24
Finished Mar 17 02:50:21 PM PDT 24
Peak memory 283648 kb
Host smart-6bae15c1-28f0-45d9-91b0-138181ce1701
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263528212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.4263528212
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.586001549
Short name T696
Test name
Test status
Simulation time 5891492971 ps
CPU time 16.61 seconds
Started Mar 17 02:14:46 PM PDT 24
Finished Mar 17 02:15:04 PM PDT 24
Peak memory 240704 kb
Host smart-03a8cc84-45fa-44de-99a3-4442f74f8103
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=586001549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.586001549
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.3450304740
Short name T474
Test name
Test status
Simulation time 14709559956 ps
CPU time 213.92 seconds
Started Mar 17 02:14:46 PM PDT 24
Finished Mar 17 02:18:21 PM PDT 24
Peak memory 249940 kb
Host smart-46353e82-0123-451c-959b-48efa1d7cdf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34503
04740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.3450304740
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.1357654267
Short name T528
Test name
Test status
Simulation time 961418708 ps
CPU time 26.62 seconds
Started Mar 17 02:14:45 PM PDT 24
Finished Mar 17 02:15:12 PM PDT 24
Peak memory 257012 kb
Host smart-972ce416-6212-4d2c-b728-9dda314b500b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13576
54267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.1357654267
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.1801422159
Short name T653
Test name
Test status
Simulation time 186585891757 ps
CPU time 2560.72 seconds
Started Mar 17 02:14:43 PM PDT 24
Finished Mar 17 02:57:25 PM PDT 24
Peak memory 286872 kb
Host smart-c5bb3fdf-0212-4f8d-a8de-608e263ba86b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801422159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.1801422159
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.706103777
Short name T339
Test name
Test status
Simulation time 11213787576 ps
CPU time 480.18 seconds
Started Mar 17 02:14:47 PM PDT 24
Finished Mar 17 02:22:48 PM PDT 24
Peak memory 247072 kb
Host smart-2bfcc95b-9a69-481d-983c-39a8fcb09526
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706103777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.706103777
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.1974241096
Short name T391
Test name
Test status
Simulation time 2477969102 ps
CPU time 70.11 seconds
Started Mar 17 02:14:46 PM PDT 24
Finished Mar 17 02:15:58 PM PDT 24
Peak memory 256120 kb
Host smart-3cf22f15-bbb9-45b1-a1dc-56a432d3a858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19742
41096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.1974241096
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.1554251
Short name T501
Test name
Test status
Simulation time 461506004 ps
CPU time 12.23 seconds
Started Mar 17 02:14:44 PM PDT 24
Finished Mar 17 02:14:57 PM PDT 24
Peak memory 248604 kb
Host smart-70eb87c1-1435-4046-8765-f4e67f2a85d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15542
51 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.1554251
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.2200926697
Short name T386
Test name
Test status
Simulation time 846070931 ps
CPU time 51.91 seconds
Started Mar 17 02:14:46 PM PDT 24
Finished Mar 17 02:15:39 PM PDT 24
Peak memory 249248 kb
Host smart-9ae8782b-8754-45fa-b0eb-f7ec691377b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22009
26697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.2200926697
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.4017531584
Short name T387
Test name
Test status
Simulation time 831140693 ps
CPU time 51.08 seconds
Started Mar 17 02:14:44 PM PDT 24
Finished Mar 17 02:15:36 PM PDT 24
Peak memory 256076 kb
Host smart-a7dd0003-e318-430b-ac3b-4fd44f16946d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40175
31584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.4017531584
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.2098097587
Short name T286
Test name
Test status
Simulation time 67978494723 ps
CPU time 6736.68 seconds
Started Mar 17 02:14:45 PM PDT 24
Finished Mar 17 04:07:03 PM PDT 24
Peak memory 355232 kb
Host smart-4f421c01-843c-42f5-8265-08b5a2d46304
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098097587 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.2098097587
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.40190162
Short name T316
Test name
Test status
Simulation time 502444195146 ps
CPU time 1851.51 seconds
Started Mar 17 02:15:13 PM PDT 24
Finished Mar 17 02:46:04 PM PDT 24
Peak memory 271544 kb
Host smart-806604fd-9b36-429d-aa26-002bd4837ef0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40190162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.40190162
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.810481541
Short name T700
Test name
Test status
Simulation time 135027088 ps
CPU time 9.12 seconds
Started Mar 17 02:15:13 PM PDT 24
Finished Mar 17 02:15:22 PM PDT 24
Peak memory 248852 kb
Host smart-d10b5e1d-daab-4104-854c-953493347982
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=810481541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.810481541
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.2082229028
Short name T315
Test name
Test status
Simulation time 1055613792 ps
CPU time 72.43 seconds
Started Mar 17 02:15:12 PM PDT 24
Finished Mar 17 02:16:24 PM PDT 24
Peak memory 256704 kb
Host smart-24da9bef-ff1f-4392-b9a2-4144d4f76b46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20822
29028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2082229028
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.1624579593
Short name T506
Test name
Test status
Simulation time 520073959 ps
CPU time 34.4 seconds
Started Mar 17 02:15:15 PM PDT 24
Finished Mar 17 02:15:49 PM PDT 24
Peak memory 255400 kb
Host smart-0eab732d-ea38-4da8-8f2a-5a0ae7cae12d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16245
79593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.1624579593
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.3236439619
Short name T416
Test name
Test status
Simulation time 18477015574 ps
CPU time 1355.98 seconds
Started Mar 17 02:15:14 PM PDT 24
Finished Mar 17 02:37:50 PM PDT 24
Peak memory 286280 kb
Host smart-255a72d2-6873-472f-8e3f-a0767a52e24e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236439619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.3236439619
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.3886060208
Short name T291
Test name
Test status
Simulation time 28720954737 ps
CPU time 305.3 seconds
Started Mar 17 02:15:14 PM PDT 24
Finished Mar 17 02:20:19 PM PDT 24
Peak memory 248276 kb
Host smart-1684bf02-7937-4753-a623-526618689804
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886060208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3886060208
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.4011735461
Short name T597
Test name
Test status
Simulation time 687041767 ps
CPU time 33.72 seconds
Started Mar 17 02:15:14 PM PDT 24
Finished Mar 17 02:15:49 PM PDT 24
Peak memory 256008 kb
Host smart-3cbc3e0e-7e2d-489e-91e0-82ce6c0586e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40117
35461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.4011735461
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.1260723898
Short name T637
Test name
Test status
Simulation time 715045065 ps
CPU time 47.4 seconds
Started Mar 17 02:15:13 PM PDT 24
Finished Mar 17 02:16:00 PM PDT 24
Peak memory 254776 kb
Host smart-abd6b8f1-a7d6-4f47-b76b-9d877acc0a21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12607
23898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.1260723898
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.1562850357
Short name T456
Test name
Test status
Simulation time 2966474278 ps
CPU time 21.38 seconds
Started Mar 17 02:15:13 PM PDT 24
Finished Mar 17 02:15:34 PM PDT 24
Peak memory 252188 kb
Host smart-e01fdd83-5151-4880-9e63-ab48b46bfea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15628
50357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.1562850357
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.1495627840
Short name T656
Test name
Test status
Simulation time 2628236466 ps
CPU time 51.7 seconds
Started Mar 17 02:15:14 PM PDT 24
Finished Mar 17 02:16:06 PM PDT 24
Peak memory 255916 kb
Host smart-4a233f0f-30fa-4ba9-b291-1fbab0d79d08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14956
27840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.1495627840
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.3391347339
Short name T62
Test name
Test status
Simulation time 59267120483 ps
CPU time 801.44 seconds
Started Mar 17 02:15:13 PM PDT 24
Finished Mar 17 02:28:34 PM PDT 24
Peak memory 273436 kb
Host smart-71c9c3b6-3d21-4908-b42a-33b1081f356f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391347339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.3391347339
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.560066424
Short name T639
Test name
Test status
Simulation time 399821754773 ps
CPU time 2409.45 seconds
Started Mar 17 02:15:12 PM PDT 24
Finished Mar 17 02:55:22 PM PDT 24
Peak memory 321944 kb
Host smart-615020de-afef-4b27-913e-f506923fdba1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560066424 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.560066424
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.2410018799
Short name T489
Test name
Test status
Simulation time 279369012522 ps
CPU time 1321.91 seconds
Started Mar 17 02:15:21 PM PDT 24
Finished Mar 17 02:37:23 PM PDT 24
Peak memory 273152 kb
Host smart-8c630da9-a2ab-4a37-ad41-e9753443208c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410018799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.2410018799
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.1899274594
Short name T425
Test name
Test status
Simulation time 497183126 ps
CPU time 9.06 seconds
Started Mar 17 02:15:20 PM PDT 24
Finished Mar 17 02:15:29 PM PDT 24
Peak memory 240672 kb
Host smart-7f2a80ae-e88d-494c-804a-e0eb56bbae6f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1899274594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1899274594
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.625540020
Short name T666
Test name
Test status
Simulation time 11278218079 ps
CPU time 312.83 seconds
Started Mar 17 02:15:21 PM PDT 24
Finished Mar 17 02:20:34 PM PDT 24
Peak memory 257028 kb
Host smart-041589ec-95b8-44c2-a5e5-670587ff2f95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62554
0020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.625540020
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.4107069146
Short name T507
Test name
Test status
Simulation time 184201722 ps
CPU time 23.44 seconds
Started Mar 17 02:15:19 PM PDT 24
Finished Mar 17 02:15:43 PM PDT 24
Peak memory 254756 kb
Host smart-d3e7c38a-86fb-4c12-ae56-2eb5e623ffc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41070
69146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.4107069146
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.2470529484
Short name T141
Test name
Test status
Simulation time 102460906079 ps
CPU time 1265.91 seconds
Started Mar 17 02:15:20 PM PDT 24
Finished Mar 17 02:36:26 PM PDT 24
Peak memory 265276 kb
Host smart-f5e27ce9-261c-41ca-a7bf-52dbde14b572
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470529484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.2470529484
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.2027036508
Short name T395
Test name
Test status
Simulation time 69148446507 ps
CPU time 2130.44 seconds
Started Mar 17 02:15:19 PM PDT 24
Finished Mar 17 02:50:50 PM PDT 24
Peak memory 273388 kb
Host smart-80a773c0-d7be-4980-a603-833e7b9f2fc9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027036508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.2027036508
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.2258639768
Short name T458
Test name
Test status
Simulation time 3220981381 ps
CPU time 53.04 seconds
Started Mar 17 02:15:20 PM PDT 24
Finished Mar 17 02:16:14 PM PDT 24
Peak memory 248944 kb
Host smart-ee68cfb8-f38e-4db8-b308-6ae3819edfab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22586
39768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.2258639768
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.2920104625
Short name T450
Test name
Test status
Simulation time 4658133914 ps
CPU time 78.09 seconds
Started Mar 17 02:15:20 PM PDT 24
Finished Mar 17 02:16:38 PM PDT 24
Peak memory 255144 kb
Host smart-d3213626-f455-48f9-bbc5-7706f5ecec5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29201
04625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2920104625
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.1118974700
Short name T481
Test name
Test status
Simulation time 4377971511 ps
CPU time 30.42 seconds
Started Mar 17 02:15:20 PM PDT 24
Finished Mar 17 02:15:51 PM PDT 24
Peak memory 248976 kb
Host smart-f6b0331d-c8cb-49f9-bea2-4caac3d8f56d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11189
74700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.1118974700
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.1513791729
Short name T464
Test name
Test status
Simulation time 940344800 ps
CPU time 24.58 seconds
Started Mar 17 02:15:13 PM PDT 24
Finished Mar 17 02:15:37 PM PDT 24
Peak memory 248824 kb
Host smart-4999b6e0-4c70-46be-b3cf-f0807c56dfa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15137
91729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1513791729
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.3174445782
Short name T313
Test name
Test status
Simulation time 51874409995 ps
CPU time 1545.84 seconds
Started Mar 17 02:15:21 PM PDT 24
Finished Mar 17 02:41:07 PM PDT 24
Peak memory 289028 kb
Host smart-3a2ebb2d-f57a-4602-84d5-dd94ec9cdf57
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174445782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.3174445782
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.3629804095
Short name T582
Test name
Test status
Simulation time 247736741831 ps
CPU time 1994.88 seconds
Started Mar 17 02:15:21 PM PDT 24
Finished Mar 17 02:48:37 PM PDT 24
Peak memory 306212 kb
Host smart-0dabca9c-df7d-42ff-9ae8-8bb168216748
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629804095 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.3629804095
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.3070843440
Short name T239
Test name
Test status
Simulation time 34924762 ps
CPU time 3.25 seconds
Started Mar 17 02:15:32 PM PDT 24
Finished Mar 17 02:15:35 PM PDT 24
Peak memory 249096 kb
Host smart-a44a069d-c6bd-4b75-aab1-5c5287ca7f0d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3070843440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.3070843440
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.1444209865
Short name T131
Test name
Test status
Simulation time 48624317501 ps
CPU time 1637.8 seconds
Started Mar 17 02:15:24 PM PDT 24
Finished Mar 17 02:42:42 PM PDT 24
Peak memory 272100 kb
Host smart-d0253012-d33f-498b-972b-2fc03fb37e68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444209865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.1444209865
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.1834758836
Short name T257
Test name
Test status
Simulation time 162439426 ps
CPU time 10.17 seconds
Started Mar 17 02:15:27 PM PDT 24
Finished Mar 17 02:15:37 PM PDT 24
Peak memory 248868 kb
Host smart-7a33a600-49f6-44f5-bdb0-45f577e177df
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1834758836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.1834758836
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.4269405047
Short name T566
Test name
Test status
Simulation time 339067399 ps
CPU time 40.27 seconds
Started Mar 17 02:15:21 PM PDT 24
Finished Mar 17 02:16:01 PM PDT 24
Peak memory 256696 kb
Host smart-f16e2224-458a-4510-b6e5-e3b3a92a61da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42694
05047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.4269405047
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.1210666296
Short name T558
Test name
Test status
Simulation time 600554723 ps
CPU time 33.08 seconds
Started Mar 17 02:15:21 PM PDT 24
Finished Mar 17 02:15:54 PM PDT 24
Peak memory 249148 kb
Host smart-e691691d-3cad-4180-ac06-dff30a6fbed6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12106
66296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.1210666296
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.353387669
Short name T130
Test name
Test status
Simulation time 8040736671 ps
CPU time 770.09 seconds
Started Mar 17 02:15:25 PM PDT 24
Finished Mar 17 02:28:15 PM PDT 24
Peak memory 272208 kb
Host smart-b5c61282-32b4-4bdf-8adf-ee2c49c3ac15
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353387669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.353387669
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.2084457743
Short name T14
Test name
Test status
Simulation time 23799670234 ps
CPU time 1622.44 seconds
Started Mar 17 02:15:25 PM PDT 24
Finished Mar 17 02:42:28 PM PDT 24
Peak memory 273032 kb
Host smart-a4202254-44c7-4cbc-bf50-becd73f71e3c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084457743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.2084457743
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.1396618138
Short name T698
Test name
Test status
Simulation time 6575541104 ps
CPU time 288.47 seconds
Started Mar 17 02:15:26 PM PDT 24
Finished Mar 17 02:20:15 PM PDT 24
Peak memory 248232 kb
Host smart-94201e18-39a7-4934-9625-3301fa3fbf82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396618138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.1396618138
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.3059911716
Short name T536
Test name
Test status
Simulation time 655382001 ps
CPU time 25.05 seconds
Started Mar 17 02:15:19 PM PDT 24
Finished Mar 17 02:15:44 PM PDT 24
Peak memory 255908 kb
Host smart-8590bd9c-7e25-418d-b017-ec06173d3610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30599
11716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.3059911716
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.1907648150
Short name T608
Test name
Test status
Simulation time 3177620596 ps
CPU time 42.07 seconds
Started Mar 17 02:15:20 PM PDT 24
Finished Mar 17 02:16:02 PM PDT 24
Peak memory 248832 kb
Host smart-37a6ef22-7676-4e36-b836-87fbacc47e74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19076
48150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.1907648150
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.2383947296
Short name T277
Test name
Test status
Simulation time 566974291 ps
CPU time 36.55 seconds
Started Mar 17 02:15:33 PM PDT 24
Finished Mar 17 02:16:09 PM PDT 24
Peak memory 256052 kb
Host smart-cfb59aa1-ed65-4c16-801e-84f3f10c5183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23839
47296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.2383947296
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.2020989386
Short name T645
Test name
Test status
Simulation time 573985754 ps
CPU time 35.99 seconds
Started Mar 17 02:15:23 PM PDT 24
Finished Mar 17 02:15:59 PM PDT 24
Peak memory 256132 kb
Host smart-aeac8838-b95f-4140-8855-676d1ab31bcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20209
89386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2020989386
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.3115513277
Short name T405
Test name
Test status
Simulation time 188160187201 ps
CPU time 3195.3 seconds
Started Mar 17 02:15:28 PM PDT 24
Finished Mar 17 03:08:43 PM PDT 24
Peak memory 299736 kb
Host smart-351d54a2-3574-4244-9607-337494954796
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115513277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.3115513277
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.2537891084
Short name T232
Test name
Test status
Simulation time 58644871 ps
CPU time 3.43 seconds
Started Mar 17 02:15:32 PM PDT 24
Finished Mar 17 02:15:35 PM PDT 24
Peak memory 249060 kb
Host smart-bca8b40c-e432-4342-a983-f34a79f0da60
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2537891084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.2537891084
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.2870206675
Short name T268
Test name
Test status
Simulation time 27123326392 ps
CPU time 1585 seconds
Started Mar 17 02:15:26 PM PDT 24
Finished Mar 17 02:41:51 PM PDT 24
Peak memory 273524 kb
Host smart-7bd0fa2b-bf46-4f97-a172-7311cca62565
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870206675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.2870206675
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.1717208412
Short name T463
Test name
Test status
Simulation time 1945801438 ps
CPU time 24.55 seconds
Started Mar 17 02:15:26 PM PDT 24
Finished Mar 17 02:15:50 PM PDT 24
Peak memory 248892 kb
Host smart-aee2ab3c-8250-4efc-a8b6-429c7caf054b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1717208412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.1717208412
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.2910642356
Short name T45
Test name
Test status
Simulation time 3720672459 ps
CPU time 71.45 seconds
Started Mar 17 02:15:28 PM PDT 24
Finished Mar 17 02:16:39 PM PDT 24
Peak memory 249124 kb
Host smart-7dad2a22-3beb-46c3-b9a5-365bb96d511d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29106
42356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.2910642356
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.1259660755
Short name T556
Test name
Test status
Simulation time 1008501008 ps
CPU time 57.56 seconds
Started Mar 17 02:15:32 PM PDT 24
Finished Mar 17 02:16:30 PM PDT 24
Peak memory 254668 kb
Host smart-8db11a0e-12ed-416f-a5ad-f23fb95ca97f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12596
60755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.1259660755
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.4113388359
Short name T90
Test name
Test status
Simulation time 52248014110 ps
CPU time 1062.38 seconds
Started Mar 17 02:15:27 PM PDT 24
Finished Mar 17 02:33:10 PM PDT 24
Peak memory 273504 kb
Host smart-66e91645-0e35-4df9-b185-3e862bcc9a16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113388359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.4113388359
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.918344280
Short name T96
Test name
Test status
Simulation time 19433486241 ps
CPU time 532.96 seconds
Started Mar 17 02:15:32 PM PDT 24
Finished Mar 17 02:24:25 PM PDT 24
Peak memory 247416 kb
Host smart-d663eef5-0b74-4a6b-913e-93518d1f1648
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918344280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.918344280
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.2367535184
Short name T496
Test name
Test status
Simulation time 646845893 ps
CPU time 18.5 seconds
Started Mar 17 02:15:27 PM PDT 24
Finished Mar 17 02:15:46 PM PDT 24
Peak memory 255152 kb
Host smart-f7e3b592-ca9b-4ab6-b31e-2345730db687
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23675
35184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.2367535184
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.742382601
Short name T543
Test name
Test status
Simulation time 614532086 ps
CPU time 37.07 seconds
Started Mar 17 02:15:28 PM PDT 24
Finished Mar 17 02:16:05 PM PDT 24
Peak memory 248892 kb
Host smart-9b273414-9bf7-4316-8010-c67d95e7e516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74238
2601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.742382601
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.1356681027
Short name T706
Test name
Test status
Simulation time 981453186 ps
CPU time 11.88 seconds
Started Mar 17 02:15:25 PM PDT 24
Finished Mar 17 02:15:37 PM PDT 24
Peak memory 253884 kb
Host smart-7f593bbb-bfe6-415e-9332-6babd17361fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13566
81027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.1356681027
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.1194064157
Short name T614
Test name
Test status
Simulation time 582380016 ps
CPU time 10.83 seconds
Started Mar 17 02:15:28 PM PDT 24
Finished Mar 17 02:15:38 PM PDT 24
Peak memory 248812 kb
Host smart-52e35658-b9fe-402b-9cdc-37eb45620528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11940
64157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.1194064157
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.543752380
Short name T472
Test name
Test status
Simulation time 733775687489 ps
CPU time 2976.46 seconds
Started Mar 17 02:15:33 PM PDT 24
Finished Mar 17 03:05:10 PM PDT 24
Peak memory 287668 kb
Host smart-9755052f-5c0a-41c3-bd57-0805f37f3e09
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543752380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_han
dler_stress_all.543752380
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.2286892334
Short name T462
Test name
Test status
Simulation time 127883289534 ps
CPU time 6928.02 seconds
Started Mar 17 02:15:31 PM PDT 24
Finished Mar 17 04:11:00 PM PDT 24
Peak memory 355280 kb
Host smart-8fb3ce06-228d-4ffd-b79a-39d1ee0e4899
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286892334 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.2286892334
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.2347306009
Short name T64
Test name
Test status
Simulation time 107726174 ps
CPU time 3.52 seconds
Started Mar 17 02:15:42 PM PDT 24
Finished Mar 17 02:15:45 PM PDT 24
Peak memory 249124 kb
Host smart-4b56d16b-6123-4b10-b736-c4d9bea30a58
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2347306009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.2347306009
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.471195675
Short name T495
Test name
Test status
Simulation time 5697363494 ps
CPU time 663.09 seconds
Started Mar 17 02:15:42 PM PDT 24
Finished Mar 17 02:26:46 PM PDT 24
Peak memory 273476 kb
Host smart-a0125499-3a9c-452c-b1d5-f362cec77b67
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471195675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.471195675
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.3517737528
Short name T635
Test name
Test status
Simulation time 691835657 ps
CPU time 22.03 seconds
Started Mar 17 02:15:42 PM PDT 24
Finished Mar 17 02:16:04 PM PDT 24
Peak memory 240684 kb
Host smart-79607178-96df-44cc-b706-a53b6b2ecb24
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3517737528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.3517737528
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.1515092384
Short name T250
Test name
Test status
Simulation time 131079414 ps
CPU time 15 seconds
Started Mar 17 02:15:33 PM PDT 24
Finished Mar 17 02:15:48 PM PDT 24
Peak memory 254944 kb
Host smart-d5c3bb3b-c248-4950-9a8a-5ab943a01bf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15150
92384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.1515092384
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.449687515
Short name T553
Test name
Test status
Simulation time 5026866565 ps
CPU time 71.31 seconds
Started Mar 17 02:15:33 PM PDT 24
Finished Mar 17 02:16:44 PM PDT 24
Peak memory 255668 kb
Host smart-11e8fa2d-2cc8-44d4-a623-cdbfc0751eef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44968
7515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.449687515
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.3217990928
Short name T479
Test name
Test status
Simulation time 27600877342 ps
CPU time 703.8 seconds
Started Mar 17 02:15:42 PM PDT 24
Finished Mar 17 02:27:26 PM PDT 24
Peak memory 265208 kb
Host smart-1a793255-22dd-4a34-874c-6691b41d5ee2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217990928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.3217990928
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.4157535624
Short name T211
Test name
Test status
Simulation time 33981328297 ps
CPU time 2057.84 seconds
Started Mar 17 02:15:44 PM PDT 24
Finished Mar 17 02:50:02 PM PDT 24
Peak memory 273460 kb
Host smart-c15aa411-5d4c-4d90-99bf-eec0a20b179b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157535624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.4157535624
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.2664624723
Short name T8
Test name
Test status
Simulation time 4440675337 ps
CPU time 171.8 seconds
Started Mar 17 02:15:43 PM PDT 24
Finished Mar 17 02:18:35 PM PDT 24
Peak memory 247992 kb
Host smart-48ba179c-37b9-460f-bf67-b667cf98c0d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664624723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.2664624723
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.1512373444
Short name T588
Test name
Test status
Simulation time 424278321 ps
CPU time 33.1 seconds
Started Mar 17 02:15:32 PM PDT 24
Finished Mar 17 02:16:06 PM PDT 24
Peak memory 248896 kb
Host smart-22e347cc-e836-4c88-9fa6-6402d4bf1264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15123
73444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.1512373444
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.212225006
Short name T57
Test name
Test status
Simulation time 2848200713 ps
CPU time 26.81 seconds
Started Mar 17 02:15:32 PM PDT 24
Finished Mar 17 02:15:58 PM PDT 24
Peak memory 248888 kb
Host smart-ec4f223b-1a15-430c-8982-5fdf865c875f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21222
5006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.212225006
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.3587608498
Short name T285
Test name
Test status
Simulation time 248788835 ps
CPU time 7.51 seconds
Started Mar 17 02:15:33 PM PDT 24
Finished Mar 17 02:15:41 PM PDT 24
Peak memory 248780 kb
Host smart-634a938a-4039-4f07-bb3f-4a2e7ed472b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35876
08498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.3587608498
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.678758149
Short name T377
Test name
Test status
Simulation time 256303707 ps
CPU time 32.49 seconds
Started Mar 17 02:15:32 PM PDT 24
Finished Mar 17 02:16:04 PM PDT 24
Peak memory 256052 kb
Host smart-66513cc5-86a7-477b-8dcc-c36f5ae650e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67875
8149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.678758149
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.1597697499
Short name T113
Test name
Test status
Simulation time 2139592262 ps
CPU time 143.2 seconds
Started Mar 17 02:15:42 PM PDT 24
Finished Mar 17 02:18:06 PM PDT 24
Peak memory 257068 kb
Host smart-8847b64c-29bc-4c24-84fb-2c3adff87b1f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597697499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.1597697499
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.2483920392
Short name T235
Test name
Test status
Simulation time 42410970 ps
CPU time 2.25 seconds
Started Mar 17 02:15:47 PM PDT 24
Finished Mar 17 02:15:49 PM PDT 24
Peak memory 249104 kb
Host smart-ba06eacf-923d-4a8d-ab7b-79b0d2ddc962
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2483920392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.2483920392
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.1586603212
Short name T112
Test name
Test status
Simulation time 7956644000 ps
CPU time 698.97 seconds
Started Mar 17 02:15:43 PM PDT 24
Finished Mar 17 02:27:22 PM PDT 24
Peak memory 265280 kb
Host smart-2d387021-691f-4aff-9e1c-7097873b0b8e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586603212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.1586603212
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.4060784716
Short name T632
Test name
Test status
Simulation time 2005168954 ps
CPU time 43.8 seconds
Started Mar 17 02:15:45 PM PDT 24
Finished Mar 17 02:16:29 PM PDT 24
Peak memory 240636 kb
Host smart-bc872932-3baa-491a-b3c7-6259afd17f53
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4060784716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.4060784716
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.678205404
Short name T435
Test name
Test status
Simulation time 146927692 ps
CPU time 12.05 seconds
Started Mar 17 02:15:44 PM PDT 24
Finished Mar 17 02:15:56 PM PDT 24
Peak memory 253044 kb
Host smart-1004857a-82a7-416d-b2ad-86c3ffa572df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67820
5404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.678205404
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.1923678072
Short name T662
Test name
Test status
Simulation time 97718005 ps
CPU time 9.51 seconds
Started Mar 17 02:15:42 PM PDT 24
Finished Mar 17 02:15:51 PM PDT 24
Peak memory 253076 kb
Host smart-c5da885a-c0ba-43d3-92d0-d3a93c934355
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19236
78072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.1923678072
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.1449957889
Short name T704
Test name
Test status
Simulation time 77118287956 ps
CPU time 2281.76 seconds
Started Mar 17 02:15:45 PM PDT 24
Finished Mar 17 02:53:48 PM PDT 24
Peak memory 272888 kb
Host smart-a1e2cfc2-8361-400b-8344-f1053ad97590
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449957889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.1449957889
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.1848887994
Short name T307
Test name
Test status
Simulation time 10651251916 ps
CPU time 841.79 seconds
Started Mar 17 02:15:44 PM PDT 24
Finished Mar 17 02:29:46 PM PDT 24
Peak memory 265324 kb
Host smart-eda6b614-447b-4ce3-9b6f-43cc8b75621d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848887994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.1848887994
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.3280437237
Short name T661
Test name
Test status
Simulation time 10615558491 ps
CPU time 230.33 seconds
Started Mar 17 02:15:46 PM PDT 24
Finished Mar 17 02:19:36 PM PDT 24
Peak memory 247848 kb
Host smart-3f585885-3da2-488d-b945-79d8932d6c1a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280437237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.3280437237
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.3987468513
Short name T97
Test name
Test status
Simulation time 3733466571 ps
CPU time 67.43 seconds
Started Mar 17 02:15:43 PM PDT 24
Finished Mar 17 02:16:50 PM PDT 24
Peak memory 257064 kb
Host smart-8904eda7-7d02-471b-8a6f-99a15571acec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39874
68513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.3987468513
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.1895525626
Short name T494
Test name
Test status
Simulation time 71527384 ps
CPU time 4.26 seconds
Started Mar 17 02:15:43 PM PDT 24
Finished Mar 17 02:15:47 PM PDT 24
Peak memory 239180 kb
Host smart-0178e762-7bdf-4832-b6a7-a7e10a649b69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18955
25626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.1895525626
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.2102122918
Short name T621
Test name
Test status
Simulation time 2141512811 ps
CPU time 34.35 seconds
Started Mar 17 02:15:45 PM PDT 24
Finished Mar 17 02:16:20 PM PDT 24
Peak memory 255844 kb
Host smart-03058604-d037-45ed-835f-8ea89020309b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21021
22918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.2102122918
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.1478369189
Short name T38
Test name
Test status
Simulation time 1489468203 ps
CPU time 12.05 seconds
Started Mar 17 02:15:42 PM PDT 24
Finished Mar 17 02:15:54 PM PDT 24
Peak memory 248784 kb
Host smart-43574e15-c680-41fa-9dd9-f4a8bb31d655
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14783
69189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.1478369189
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.2634337438
Short name T460
Test name
Test status
Simulation time 41770452436 ps
CPU time 1076.47 seconds
Started Mar 17 02:15:48 PM PDT 24
Finished Mar 17 02:33:44 PM PDT 24
Peak memory 287592 kb
Host smart-96e782da-f697-4408-af52-feb0fd827906
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634337438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.2634337438
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.712299348
Short name T234
Test name
Test status
Simulation time 40072037 ps
CPU time 2.61 seconds
Started Mar 17 02:15:50 PM PDT 24
Finished Mar 17 02:15:52 PM PDT 24
Peak memory 249080 kb
Host smart-00f42966-390a-4e2f-bc09-2a54ac00c665
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=712299348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.712299348
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.2560711084
Short name T542
Test name
Test status
Simulation time 72349211071 ps
CPU time 1980.92 seconds
Started Mar 17 02:15:45 PM PDT 24
Finished Mar 17 02:48:46 PM PDT 24
Peak memory 288624 kb
Host smart-4edf2b0d-d534-41eb-83ef-d116abe8c4e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560711084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.2560711084
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.2427899867
Short name T389
Test name
Test status
Simulation time 288014586 ps
CPU time 8.69 seconds
Started Mar 17 02:15:49 PM PDT 24
Finished Mar 17 02:15:58 PM PDT 24
Peak memory 240668 kb
Host smart-fdf6b6bd-65cf-4ad4-9ea5-923c41dc0efe
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2427899867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.2427899867
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.3815447671
Short name T95
Test name
Test status
Simulation time 1263414531 ps
CPU time 31.08 seconds
Started Mar 17 02:15:47 PM PDT 24
Finished Mar 17 02:16:19 PM PDT 24
Peak memory 255988 kb
Host smart-fd660bad-2831-47ef-975d-d8a9630e6c36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38154
47671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.3815447671
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.2990897318
Short name T554
Test name
Test status
Simulation time 98912961 ps
CPU time 5.22 seconds
Started Mar 17 02:15:44 PM PDT 24
Finished Mar 17 02:15:50 PM PDT 24
Peak memory 249556 kb
Host smart-ffb6ae98-f884-49c5-be1b-52fb10ec8a48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29908
97318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.2990897318
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.4183392281
Short name T353
Test name
Test status
Simulation time 33052341522 ps
CPU time 1744.63 seconds
Started Mar 17 02:15:48 PM PDT 24
Finished Mar 17 02:44:53 PM PDT 24
Peak memory 289212 kb
Host smart-560cc452-0351-4dcf-acef-4cdeaa69ff64
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183392281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.4183392281
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.4017982074
Short name T398
Test name
Test status
Simulation time 11829689844 ps
CPU time 985.96 seconds
Started Mar 17 02:15:50 PM PDT 24
Finished Mar 17 02:32:16 PM PDT 24
Peak memory 285740 kb
Host smart-7abed961-2ecf-4db5-b7ac-67fef3b10918
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017982074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.4017982074
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.2367809053
Short name T342
Test name
Test status
Simulation time 24124612875 ps
CPU time 272.57 seconds
Started Mar 17 02:15:45 PM PDT 24
Finished Mar 17 02:20:18 PM PDT 24
Peak memory 247008 kb
Host smart-e5858763-d99d-4244-9b6e-4f3fb74848b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367809053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.2367809053
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.1872560841
Short name T310
Test name
Test status
Simulation time 905895776 ps
CPU time 32.38 seconds
Started Mar 17 02:15:42 PM PDT 24
Finished Mar 17 02:16:15 PM PDT 24
Peak memory 248896 kb
Host smart-56a51c4f-55d1-41fa-b0dc-0c2a6f3807cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18725
60841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.1872560841
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.3588769965
Short name T602
Test name
Test status
Simulation time 6787143086 ps
CPU time 47.4 seconds
Started Mar 17 02:15:45 PM PDT 24
Finished Mar 17 02:16:32 PM PDT 24
Peak memory 255408 kb
Host smart-863505e9-9a86-4280-9848-d7e41305d858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35887
69965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.3588769965
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.1318107340
Short name T284
Test name
Test status
Simulation time 243090512 ps
CPU time 31.13 seconds
Started Mar 17 02:15:43 PM PDT 24
Finished Mar 17 02:16:14 PM PDT 24
Peak memory 248832 kb
Host smart-e2b09d0f-35e3-4fa8-a27d-0a78fb186409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13181
07340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.1318107340
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.2476965519
Short name T442
Test name
Test status
Simulation time 408741855 ps
CPU time 10.12 seconds
Started Mar 17 02:15:45 PM PDT 24
Finished Mar 17 02:15:55 PM PDT 24
Peak memory 257048 kb
Host smart-38fb1664-aeba-4d45-ab9e-20b54c10b252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24769
65519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.2476965519
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.3644383716
Short name T34
Test name
Test status
Simulation time 40624532488 ps
CPU time 1511.43 seconds
Started Mar 17 02:15:49 PM PDT 24
Finished Mar 17 02:41:00 PM PDT 24
Peak memory 268388 kb
Host smart-d7890418-17c3-40bb-a450-cc88be6f1331
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644383716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.3644383716
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.2730322913
Short name T241
Test name
Test status
Simulation time 31134346 ps
CPU time 3.56 seconds
Started Mar 17 02:15:59 PM PDT 24
Finished Mar 17 02:16:03 PM PDT 24
Peak memory 249064 kb
Host smart-e788486a-cda7-484c-9e2f-590959a16882
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2730322913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.2730322913
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.2088026102
Short name T100
Test name
Test status
Simulation time 65642663841 ps
CPU time 1345.74 seconds
Started Mar 17 02:15:55 PM PDT 24
Finished Mar 17 02:38:21 PM PDT 24
Peak memory 284960 kb
Host smart-f1473108-5a17-4e24-975b-4095bbe54daa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088026102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.2088026102
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.2792499830
Short name T441
Test name
Test status
Simulation time 950955963 ps
CPU time 13.07 seconds
Started Mar 17 02:15:57 PM PDT 24
Finished Mar 17 02:16:10 PM PDT 24
Peak memory 240696 kb
Host smart-9cc3ede0-e762-4d98-bcef-4b278a68864f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2792499830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.2792499830
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.4269394305
Short name T380
Test name
Test status
Simulation time 7559725897 ps
CPU time 168.97 seconds
Started Mar 17 02:15:51 PM PDT 24
Finished Mar 17 02:18:41 PM PDT 24
Peak memory 257072 kb
Host smart-807e6af6-5ae9-42a1-aa7e-4f6e6a8e0bf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42693
94305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.4269394305
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.1206317493
Short name T634
Test name
Test status
Simulation time 9015492916 ps
CPU time 50.63 seconds
Started Mar 17 02:15:50 PM PDT 24
Finished Mar 17 02:16:40 PM PDT 24
Peak memory 248956 kb
Host smart-66fc508b-bd8b-47f0-b9eb-9e01843ade7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12063
17493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.1206317493
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.2514032674
Short name T699
Test name
Test status
Simulation time 37848964083 ps
CPU time 1990.48 seconds
Started Mar 17 02:15:54 PM PDT 24
Finished Mar 17 02:49:05 PM PDT 24
Peak memory 272936 kb
Host smart-ea8bcddb-554c-4ba9-9af2-d27c38b86fd7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514032674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2514032674
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.4163346193
Short name T108
Test name
Test status
Simulation time 22575600895 ps
CPU time 1496.26 seconds
Started Mar 17 02:15:56 PM PDT 24
Finished Mar 17 02:40:52 PM PDT 24
Peak memory 273612 kb
Host smart-df5103e8-2d33-4844-91f7-863d3598ab9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163346193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.4163346193
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.3560304962
Short name T322
Test name
Test status
Simulation time 15434735795 ps
CPU time 328.68 seconds
Started Mar 17 02:15:58 PM PDT 24
Finished Mar 17 02:21:28 PM PDT 24
Peak memory 246964 kb
Host smart-5c0d01e5-554f-4593-9d3e-8f455248114e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560304962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.3560304962
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.40697298
Short name T94
Test name
Test status
Simulation time 362977415 ps
CPU time 23.86 seconds
Started Mar 17 02:15:51 PM PDT 24
Finished Mar 17 02:16:15 PM PDT 24
Peak memory 255268 kb
Host smart-063f790a-2da8-4366-b88a-1f22bcf1c1b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40697
298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.40697298
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.55323816
Short name T92
Test name
Test status
Simulation time 484452908 ps
CPU time 38.37 seconds
Started Mar 17 02:15:50 PM PDT 24
Finished Mar 17 02:16:29 PM PDT 24
Peak memory 254776 kb
Host smart-9e3720b4-c473-48e8-b0cf-e3dcd7d46444
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55323
816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.55323816
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.1410703772
Short name T617
Test name
Test status
Simulation time 1630785206 ps
CPU time 27.02 seconds
Started Mar 17 02:15:58 PM PDT 24
Finished Mar 17 02:16:26 PM PDT 24
Peak memory 255368 kb
Host smart-81064b35-0c03-4612-b80b-add2d49b5caa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14107
03772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.1410703772
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.2670965552
Short name T580
Test name
Test status
Simulation time 520413041 ps
CPU time 31.05 seconds
Started Mar 17 02:15:51 PM PDT 24
Finished Mar 17 02:16:22 PM PDT 24
Peak memory 249052 kb
Host smart-43063f08-93dd-4da1-8923-df5b140b6781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26709
65552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.2670965552
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.4248045679
Short name T110
Test name
Test status
Simulation time 373698238749 ps
CPU time 2374.78 seconds
Started Mar 17 02:15:55 PM PDT 24
Finished Mar 17 02:55:30 PM PDT 24
Peak memory 297620 kb
Host smart-76264344-1f55-4b7e-b0e0-90210eebbb7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248045679 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.4248045679
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.2598940686
Short name T246
Test name
Test status
Simulation time 442420464 ps
CPU time 3.37 seconds
Started Mar 17 02:16:13 PM PDT 24
Finished Mar 17 02:16:17 PM PDT 24
Peak memory 249076 kb
Host smart-bd198f9a-e639-4897-8a7e-e3df0950e762
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2598940686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2598940686
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.4134814697
Short name T214
Test name
Test status
Simulation time 535136779 ps
CPU time 6.84 seconds
Started Mar 17 02:16:00 PM PDT 24
Finished Mar 17 02:16:07 PM PDT 24
Peak memory 248876 kb
Host smart-7188002a-e34c-450b-85a5-8a51a4d39742
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4134814697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.4134814697
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.3518220366
Short name T418
Test name
Test status
Simulation time 1719965695 ps
CPU time 126.79 seconds
Started Mar 17 02:16:02 PM PDT 24
Finished Mar 17 02:18:09 PM PDT 24
Peak memory 250944 kb
Host smart-3a3ecbf5-2805-4dd1-ba48-738e24620ef2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35182
20366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.3518220366
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.1777659448
Short name T642
Test name
Test status
Simulation time 381888780 ps
CPU time 27.13 seconds
Started Mar 17 02:16:01 PM PDT 24
Finished Mar 17 02:16:28 PM PDT 24
Peak memory 255172 kb
Host smart-a6ca1802-4d1c-4320-b5ae-fef45dc58164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17776
59448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.1777659448
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.1197422482
Short name T483
Test name
Test status
Simulation time 99783568277 ps
CPU time 1591.5 seconds
Started Mar 17 02:16:00 PM PDT 24
Finished Mar 17 02:42:32 PM PDT 24
Peak memory 268408 kb
Host smart-cd15259b-b954-4c23-bef5-7b6cf14d92c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197422482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.1197422482
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.2183834049
Short name T465
Test name
Test status
Simulation time 42935840588 ps
CPU time 1577.4 seconds
Started Mar 17 02:16:00 PM PDT 24
Finished Mar 17 02:42:18 PM PDT 24
Peak memory 273352 kb
Host smart-dd76ea1f-840b-48c6-a6b4-bfa2f35eb41c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183834049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.2183834049
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.2043535658
Short name T331
Test name
Test status
Simulation time 33922301774 ps
CPU time 374.04 seconds
Started Mar 17 02:16:02 PM PDT 24
Finished Mar 17 02:22:17 PM PDT 24
Peak memory 247012 kb
Host smart-1362a909-891b-4930-a05b-4a72ffee8c1e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043535658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.2043535658
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.3809164494
Short name T68
Test name
Test status
Simulation time 654627709 ps
CPU time 16.87 seconds
Started Mar 17 02:15:54 PM PDT 24
Finished Mar 17 02:16:11 PM PDT 24
Peak memory 248896 kb
Host smart-13470991-1967-4ad8-9d57-d18317481f39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38091
64494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.3809164494
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.1352494060
Short name T532
Test name
Test status
Simulation time 40752801 ps
CPU time 3.32 seconds
Started Mar 17 02:16:01 PM PDT 24
Finished Mar 17 02:16:04 PM PDT 24
Peak memory 239036 kb
Host smart-d18a37a1-98ee-431b-b96e-49556a008583
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13524
94060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.1352494060
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.4103827583
Short name T583
Test name
Test status
Simulation time 832985077 ps
CPU time 33.93 seconds
Started Mar 17 02:16:01 PM PDT 24
Finished Mar 17 02:16:36 PM PDT 24
Peak memory 247348 kb
Host smart-77902c7d-3e85-4166-bfa4-4bd958a3e2a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41038
27583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.4103827583
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.3348498554
Short name T215
Test name
Test status
Simulation time 596047486 ps
CPU time 40.1 seconds
Started Mar 17 02:15:55 PM PDT 24
Finished Mar 17 02:16:36 PM PDT 24
Peak memory 248824 kb
Host smart-1becdf01-378b-466f-8b54-9aff791a5b3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33484
98554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.3348498554
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.3539204967
Short name T78
Test name
Test status
Simulation time 7512185983 ps
CPU time 149.99 seconds
Started Mar 17 02:16:01 PM PDT 24
Finished Mar 17 02:18:31 PM PDT 24
Peak memory 257084 kb
Host smart-6c382ec2-f41e-4773-8f37-6e1f244d6348
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539204967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.3539204967
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.2636396309
Short name T210
Test name
Test status
Simulation time 165683876 ps
CPU time 4.52 seconds
Started Mar 17 02:16:13 PM PDT 24
Finished Mar 17 02:16:19 PM PDT 24
Peak memory 249032 kb
Host smart-3b638b34-7bd4-4bc4-9bae-b74010f4c969
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2636396309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2636396309
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.1185725580
Short name T527
Test name
Test status
Simulation time 71146118018 ps
CPU time 2357.93 seconds
Started Mar 17 02:16:08 PM PDT 24
Finished Mar 17 02:55:26 PM PDT 24
Peak memory 289256 kb
Host smart-d0e59f3e-920a-48b8-99be-b75b7aaea9db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185725580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.1185725580
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.2989104418
Short name T630
Test name
Test status
Simulation time 758627943 ps
CPU time 7.4 seconds
Started Mar 17 02:16:13 PM PDT 24
Finished Mar 17 02:16:21 PM PDT 24
Peak memory 240632 kb
Host smart-6bdac778-fd20-4925-a9ae-28f89b726fce
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2989104418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.2989104418
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.4039548688
Short name T213
Test name
Test status
Simulation time 34446101784 ps
CPU time 238.16 seconds
Started Mar 17 02:16:09 PM PDT 24
Finished Mar 17 02:20:08 PM PDT 24
Peak memory 256840 kb
Host smart-43fd9de0-5398-466a-85b0-2b586c1e748a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40395
48688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.4039548688
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.2764407954
Short name T657
Test name
Test status
Simulation time 109510514 ps
CPU time 8.79 seconds
Started Mar 17 02:16:09 PM PDT 24
Finished Mar 17 02:16:18 PM PDT 24
Peak memory 250520 kb
Host smart-9eb647eb-83e9-4932-b4a3-7920fcf834e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27644
07954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.2764407954
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.3147175095
Short name T360
Test name
Test status
Simulation time 222703066485 ps
CPU time 3386.54 seconds
Started Mar 17 02:16:08 PM PDT 24
Finished Mar 17 03:12:35 PM PDT 24
Peak memory 288916 kb
Host smart-f70b98ca-94e3-4892-b736-25af11d62368
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147175095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.3147175095
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.1067035977
Short name T616
Test name
Test status
Simulation time 11261020694 ps
CPU time 1018.14 seconds
Started Mar 17 02:16:09 PM PDT 24
Finished Mar 17 02:33:08 PM PDT 24
Peak memory 283132 kb
Host smart-6a486ec1-5a2e-42e9-8bdb-f822394af861
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067035977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.1067035977
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.976862594
Short name T338
Test name
Test status
Simulation time 13198968219 ps
CPU time 544.02 seconds
Started Mar 17 02:16:07 PM PDT 24
Finished Mar 17 02:25:11 PM PDT 24
Peak memory 248104 kb
Host smart-56daeb96-b18d-4f17-b163-097dc35575c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976862594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.976862594
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.3164557087
Short name T606
Test name
Test status
Simulation time 231856964 ps
CPU time 27.68 seconds
Started Mar 17 02:16:08 PM PDT 24
Finished Mar 17 02:16:36 PM PDT 24
Peak memory 248772 kb
Host smart-57305b53-c1bd-4f4d-baf7-37be89215b16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31645
57087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.3164557087
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.3151829797
Short name T417
Test name
Test status
Simulation time 84144643 ps
CPU time 4.71 seconds
Started Mar 17 02:16:07 PM PDT 24
Finished Mar 17 02:16:12 PM PDT 24
Peak memory 239332 kb
Host smart-a394823d-76fb-44b2-9854-1ac83314cc00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31518
29797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.3151829797
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.2905305117
Short name T487
Test name
Test status
Simulation time 149980878 ps
CPU time 11.39 seconds
Started Mar 17 02:16:06 PM PDT 24
Finished Mar 17 02:16:18 PM PDT 24
Peak memory 256016 kb
Host smart-34563fec-f753-4ddb-ac80-fc0cea92f2c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29053
05117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2905305117
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.2921025291
Short name T293
Test name
Test status
Simulation time 2663824691 ps
CPU time 65.68 seconds
Started Mar 17 02:16:06 PM PDT 24
Finished Mar 17 02:17:12 PM PDT 24
Peak memory 248864 kb
Host smart-dfede4ab-29b0-42cb-929e-81f76b3cbf98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29210
25291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.2921025291
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.2290415800
Short name T233
Test name
Test status
Simulation time 42039907 ps
CPU time 4.13 seconds
Started Mar 17 02:14:58 PM PDT 24
Finished Mar 17 02:15:03 PM PDT 24
Peak memory 248992 kb
Host smart-69a01530-d050-48e0-bc4e-1d2ed5275154
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2290415800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.2290415800
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.2904715143
Short name T266
Test name
Test status
Simulation time 103176341324 ps
CPU time 1773.45 seconds
Started Mar 17 02:14:58 PM PDT 24
Finished Mar 17 02:44:32 PM PDT 24
Peak memory 273440 kb
Host smart-3c81f67e-0b41-4b46-80d5-81987e11ebdb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904715143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2904715143
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.3089475583
Short name T518
Test name
Test status
Simulation time 1300404577 ps
CPU time 53.53 seconds
Started Mar 17 02:14:50 PM PDT 24
Finished Mar 17 02:15:44 PM PDT 24
Peak memory 240672 kb
Host smart-ff09fb94-a714-47dc-a41e-812d2f4a029d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3089475583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.3089475583
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.3892124286
Short name T531
Test name
Test status
Simulation time 1824471882 ps
CPU time 33.61 seconds
Started Mar 17 02:14:50 PM PDT 24
Finished Mar 17 02:15:24 PM PDT 24
Peak memory 255952 kb
Host smart-bd035f4d-9e7c-4fa3-82b3-d3884e6b0ecd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38921
24286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.3892124286
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.3685950700
Short name T385
Test name
Test status
Simulation time 505544034 ps
CPU time 34.06 seconds
Started Mar 17 02:14:57 PM PDT 24
Finished Mar 17 02:15:32 PM PDT 24
Peak memory 255824 kb
Host smart-de821bdd-de09-4f54-acf1-46eba6ea74f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36859
50700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.3685950700
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.1996691389
Short name T357
Test name
Test status
Simulation time 30680254422 ps
CPU time 1303.79 seconds
Started Mar 17 02:14:49 PM PDT 24
Finished Mar 17 02:36:34 PM PDT 24
Peak memory 265336 kb
Host smart-62207a64-2083-4c52-8873-2cdb5eb048f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996691389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.1996691389
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.1403436142
Short name T535
Test name
Test status
Simulation time 390398573 ps
CPU time 38.89 seconds
Started Mar 17 02:14:48 PM PDT 24
Finished Mar 17 02:15:28 PM PDT 24
Peak memory 255188 kb
Host smart-f7ada24d-de78-4a1a-b976-8a14b2488bae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14034
36142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.1403436142
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.1083851101
Short name T480
Test name
Test status
Simulation time 8874069574 ps
CPU time 32.47 seconds
Started Mar 17 02:14:57 PM PDT 24
Finished Mar 17 02:15:30 PM PDT 24
Peak memory 247612 kb
Host smart-a4c41061-cd6b-4e57-a314-448aad5eaa69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10838
51101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.1083851101
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.3607006689
Short name T36
Test name
Test status
Simulation time 623966751 ps
CPU time 11.53 seconds
Started Mar 17 02:14:50 PM PDT 24
Finished Mar 17 02:15:02 PM PDT 24
Peak memory 265248 kb
Host smart-f560d8b6-c799-45d8-a65f-fbbc7837c844
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3607006689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.3607006689
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.171632478
Short name T573
Test name
Test status
Simulation time 161697477 ps
CPU time 10.49 seconds
Started Mar 17 02:14:58 PM PDT 24
Finished Mar 17 02:15:09 PM PDT 24
Peak memory 248832 kb
Host smart-a2914501-f963-47d9-a075-7225d6ef39c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17163
2478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.171632478
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.2704014522
Short name T299
Test name
Test status
Simulation time 4746407353 ps
CPU time 43.42 seconds
Started Mar 17 02:14:50 PM PDT 24
Finished Mar 17 02:15:33 PM PDT 24
Peak memory 248956 kb
Host smart-c72e20ed-4173-4621-84f5-f71f321b76be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27040
14522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.2704014522
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.1436033737
Short name T50
Test name
Test status
Simulation time 13911098906 ps
CPU time 312.6 seconds
Started Mar 17 02:14:58 PM PDT 24
Finished Mar 17 02:20:11 PM PDT 24
Peak memory 256976 kb
Host smart-c58a6705-4dc8-4bf3-8802-52f88ff7243d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436033737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.1436033737
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.1153242296
Short name T85
Test name
Test status
Simulation time 37264941607 ps
CPU time 1329.39 seconds
Started Mar 17 02:16:12 PM PDT 24
Finished Mar 17 02:38:22 PM PDT 24
Peak memory 273492 kb
Host smart-97563562-6ed6-497b-bc78-4831cf830799
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153242296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.1153242296
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.1524483270
Short name T524
Test name
Test status
Simulation time 3641666435 ps
CPU time 80.42 seconds
Started Mar 17 02:16:14 PM PDT 24
Finished Mar 17 02:17:35 PM PDT 24
Peak memory 257024 kb
Host smart-95302de6-71b9-42f9-a8ad-6e81d5bddd17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15244
83270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.1524483270
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.718525063
Short name T627
Test name
Test status
Simulation time 90758192 ps
CPU time 11.87 seconds
Started Mar 17 02:16:12 PM PDT 24
Finished Mar 17 02:16:25 PM PDT 24
Peak memory 255164 kb
Host smart-88889f0d-66e5-4e92-bcd5-b003b5682e03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71852
5063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.718525063
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.1058229215
Short name T682
Test name
Test status
Simulation time 10664291117 ps
CPU time 1231.35 seconds
Started Mar 17 02:16:13 PM PDT 24
Finished Mar 17 02:36:45 PM PDT 24
Peak memory 272476 kb
Host smart-09f9ff32-d17d-427e-b810-f2d3cdd492df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058229215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1058229215
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.270278563
Short name T254
Test name
Test status
Simulation time 126361508794 ps
CPU time 2214.18 seconds
Started Mar 17 02:16:12 PM PDT 24
Finished Mar 17 02:53:07 PM PDT 24
Peak memory 285084 kb
Host smart-facd11af-c90d-40bc-a6a2-a01ec64b11ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270278563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.270278563
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.2421140906
Short name T707
Test name
Test status
Simulation time 10280653504 ps
CPU time 431.83 seconds
Started Mar 17 02:16:12 PM PDT 24
Finished Mar 17 02:23:25 PM PDT 24
Peak memory 248852 kb
Host smart-be4e93c0-232d-43e0-826c-82fac1f5ce51
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421140906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.2421140906
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.1101510179
Short name T659
Test name
Test status
Simulation time 450671126 ps
CPU time 22.22 seconds
Started Mar 17 02:16:14 PM PDT 24
Finished Mar 17 02:16:36 PM PDT 24
Peak memory 255484 kb
Host smart-1c69fcb5-6f7a-496a-9a31-ec4bb79a3712
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11015
10179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.1101510179
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.3008533347
Short name T3
Test name
Test status
Simulation time 5025707888 ps
CPU time 57.13 seconds
Started Mar 17 02:16:13 PM PDT 24
Finished Mar 17 02:17:10 PM PDT 24
Peak memory 255536 kb
Host smart-af55ca9f-cb63-4c00-b801-45d36dc30cb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30085
33347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.3008533347
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.4144383499
Short name T123
Test name
Test status
Simulation time 1302033493 ps
CPU time 25.31 seconds
Started Mar 17 02:16:14 PM PDT 24
Finished Mar 17 02:16:40 PM PDT 24
Peak memory 255348 kb
Host smart-252d3f18-e3cb-4c11-85f8-bb30e9e409e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41443
83499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.4144383499
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.2573348616
Short name T684
Test name
Test status
Simulation time 45339549 ps
CPU time 4 seconds
Started Mar 17 02:16:14 PM PDT 24
Finished Mar 17 02:16:18 PM PDT 24
Peak memory 240612 kb
Host smart-00fe1693-9129-4c71-8cf0-c1807d2bd1a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25733
48616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.2573348616
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.614331894
Short name T592
Test name
Test status
Simulation time 95209404692 ps
CPU time 1306.23 seconds
Started Mar 17 02:16:14 PM PDT 24
Finished Mar 17 02:38:01 PM PDT 24
Peak memory 287184 kb
Host smart-d0125f89-8f89-4e6b-9e4e-041aaeb64314
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614331894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.614331894
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.582858173
Short name T599
Test name
Test status
Simulation time 9160142656 ps
CPU time 177.56 seconds
Started Mar 17 02:16:12 PM PDT 24
Finished Mar 17 02:19:10 PM PDT 24
Peak memory 256836 kb
Host smart-53391505-80d0-4d0d-bfcc-608218446783
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58285
8173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.582858173
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.207240813
Short name T685
Test name
Test status
Simulation time 675381209 ps
CPU time 37.83 seconds
Started Mar 17 02:16:13 PM PDT 24
Finished Mar 17 02:16:51 PM PDT 24
Peak memory 255632 kb
Host smart-d30b0ab3-2bf6-4d73-a43e-56c174d345f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20724
0813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.207240813
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.3436493016
Short name T346
Test name
Test status
Simulation time 94432526462 ps
CPU time 1573.31 seconds
Started Mar 17 02:16:17 PM PDT 24
Finished Mar 17 02:42:30 PM PDT 24
Peak memory 289184 kb
Host smart-585cf681-20ad-4868-a404-160a76707f15
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436493016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.3436493016
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.1177793172
Short name T91
Test name
Test status
Simulation time 45285799791 ps
CPU time 103.15 seconds
Started Mar 17 02:16:12 PM PDT 24
Finished Mar 17 02:17:56 PM PDT 24
Peak memory 247948 kb
Host smart-147c5d72-f946-4dcc-bdaa-17ef0a2842e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177793172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.1177793172
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.4286451423
Short name T379
Test name
Test status
Simulation time 2259695517 ps
CPU time 77.71 seconds
Started Mar 17 02:16:14 PM PDT 24
Finished Mar 17 02:17:32 PM PDT 24
Peak memory 249024 kb
Host smart-282882f2-3895-45ca-b677-a3fe1f175536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42864
51423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.4286451423
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.3277045406
Short name T308
Test name
Test status
Simulation time 336716456 ps
CPU time 10.95 seconds
Started Mar 17 02:16:12 PM PDT 24
Finished Mar 17 02:16:23 PM PDT 24
Peak memory 248884 kb
Host smart-90ab7027-e8ee-40da-86ab-aedfd7cfe833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32770
45406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.3277045406
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.2612475067
Short name T382
Test name
Test status
Simulation time 294926764 ps
CPU time 8.93 seconds
Started Mar 17 02:16:14 PM PDT 24
Finished Mar 17 02:16:23 PM PDT 24
Peak memory 251836 kb
Host smart-723c2332-057e-4317-871a-e8f9b85c8161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26124
75067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.2612475067
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.1049218998
Short name T623
Test name
Test status
Simulation time 5267516095 ps
CPU time 70.62 seconds
Started Mar 17 02:16:14 PM PDT 24
Finished Mar 17 02:17:25 PM PDT 24
Peak memory 256004 kb
Host smart-d8393e03-a83e-4362-9181-e67bd09bba9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10492
18998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.1049218998
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.3015152320
Short name T41
Test name
Test status
Simulation time 40491173187 ps
CPU time 2305.01 seconds
Started Mar 17 02:16:19 PM PDT 24
Finished Mar 17 02:54:44 PM PDT 24
Peak memory 289832 kb
Host smart-75a70be3-5557-4079-88fe-c1855bbcfe79
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015152320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.3015152320
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.2120597327
Short name T394
Test name
Test status
Simulation time 17002230727 ps
CPU time 1328.69 seconds
Started Mar 17 02:16:17 PM PDT 24
Finished Mar 17 02:38:26 PM PDT 24
Peak memory 285104 kb
Host smart-980aea24-59b9-4b2d-8f93-73dfddbaab29
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120597327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.2120597327
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.3334090397
Short name T44
Test name
Test status
Simulation time 3959522329 ps
CPU time 169.97 seconds
Started Mar 17 02:16:17 PM PDT 24
Finished Mar 17 02:19:07 PM PDT 24
Peak memory 248924 kb
Host smart-9710ba40-8e0a-4ce2-8f90-05d62e14b38e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33340
90397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.3334090397
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.2593656903
Short name T552
Test name
Test status
Simulation time 2170854938 ps
CPU time 35.15 seconds
Started Mar 17 02:16:19 PM PDT 24
Finished Mar 17 02:16:55 PM PDT 24
Peak memory 249168 kb
Host smart-383b0cd3-8391-44f5-990a-01699d7b8228
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25936
56903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.2593656903
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.225602695
Short name T347
Test name
Test status
Simulation time 461618057776 ps
CPU time 2388.83 seconds
Started Mar 17 02:16:24 PM PDT 24
Finished Mar 17 02:56:14 PM PDT 24
Peak memory 273204 kb
Host smart-c408f348-a9c0-464c-91a0-040070b6d8ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225602695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.225602695
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.3402044614
Short name T422
Test name
Test status
Simulation time 33747329947 ps
CPU time 2028.68 seconds
Started Mar 17 02:16:23 PM PDT 24
Finished Mar 17 02:50:12 PM PDT 24
Peak memory 273472 kb
Host smart-ed7ae650-dc82-4721-b95c-81581c0dd3c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402044614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.3402044614
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.954058612
Short name T18
Test name
Test status
Simulation time 248736160 ps
CPU time 19.61 seconds
Started Mar 17 02:16:18 PM PDT 24
Finished Mar 17 02:16:37 PM PDT 24
Peak memory 248780 kb
Host smart-7c73910a-ac7e-4905-b78e-4dc6398938f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95405
8612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.954058612
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.3665554929
Short name T73
Test name
Test status
Simulation time 1575625789 ps
CPU time 24.15 seconds
Started Mar 17 02:16:16 PM PDT 24
Finished Mar 17 02:16:41 PM PDT 24
Peak memory 255468 kb
Host smart-3c9da6d5-a437-4ef3-a5d5-a615096f8448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36655
54929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.3665554929
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.2751213379
Short name T22
Test name
Test status
Simulation time 1297028205 ps
CPU time 48.68 seconds
Started Mar 17 02:16:18 PM PDT 24
Finished Mar 17 02:17:06 PM PDT 24
Peak memory 254772 kb
Host smart-01db359f-8497-4962-98c9-e5dfc2db829a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27512
13379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.2751213379
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.3967076816
Short name T560
Test name
Test status
Simulation time 3843396401 ps
CPU time 61.51 seconds
Started Mar 17 02:16:17 PM PDT 24
Finished Mar 17 02:17:19 PM PDT 24
Peak memory 248996 kb
Host smart-8474ff88-1ae6-4cb9-8dd0-33ad129dab6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39670
76816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.3967076816
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.2425228802
Short name T132
Test name
Test status
Simulation time 460593376589 ps
CPU time 5007.72 seconds
Started Mar 17 02:16:25 PM PDT 24
Finished Mar 17 03:39:54 PM PDT 24
Peak memory 303436 kb
Host smart-2a6a00ee-8f9f-4ae5-a7e8-88ff39999f66
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425228802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.2425228802
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.2695035418
Short name T702
Test name
Test status
Simulation time 70338814148 ps
CPU time 1142.35 seconds
Started Mar 17 02:16:25 PM PDT 24
Finished Mar 17 02:35:28 PM PDT 24
Peak memory 265324 kb
Host smart-698b92e3-79c3-4da8-88e6-7fd380729697
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695035418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2695035418
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.4214866863
Short name T467
Test name
Test status
Simulation time 4673645795 ps
CPU time 219.23 seconds
Started Mar 17 02:16:23 PM PDT 24
Finished Mar 17 02:20:02 PM PDT 24
Peak memory 256956 kb
Host smart-ca896f0c-9a54-448a-9df2-1ae88ce044f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42148
66863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.4214866863
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.682846163
Short name T445
Test name
Test status
Simulation time 1846854274 ps
CPU time 16.3 seconds
Started Mar 17 02:16:23 PM PDT 24
Finished Mar 17 02:16:40 PM PDT 24
Peak memory 249104 kb
Host smart-0aa9d84f-a3cc-4429-952d-4813eeaa85d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68284
6163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.682846163
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.2411301164
Short name T348
Test name
Test status
Simulation time 65281334639 ps
CPU time 1508.79 seconds
Started Mar 17 02:16:31 PM PDT 24
Finished Mar 17 02:41:41 PM PDT 24
Peak memory 273468 kb
Host smart-9fc347b4-6606-4560-a2a3-1bcb7e03fd64
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411301164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.2411301164
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.4046392909
Short name T687
Test name
Test status
Simulation time 33829418833 ps
CPU time 2382.37 seconds
Started Mar 17 02:16:29 PM PDT 24
Finished Mar 17 02:56:13 PM PDT 24
Peak memory 289760 kb
Host smart-08094aee-c589-41b4-aa70-feeb8a70f2a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046392909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.4046392909
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.2087793886
Short name T519
Test name
Test status
Simulation time 1157656131 ps
CPU time 44.16 seconds
Started Mar 17 02:16:24 PM PDT 24
Finished Mar 17 02:17:09 PM PDT 24
Peak memory 256240 kb
Host smart-7ab2c098-a127-440b-aa77-ca3a8f514e7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20877
93886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.2087793886
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.3051804946
Short name T650
Test name
Test status
Simulation time 4083737096 ps
CPU time 59.06 seconds
Started Mar 17 02:16:22 PM PDT 24
Finished Mar 17 02:17:22 PM PDT 24
Peak memory 255036 kb
Host smart-d6217220-20ff-40d0-a54c-e1f3e00035b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30518
04946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.3051804946
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.2912358663
Short name T133
Test name
Test status
Simulation time 416118052 ps
CPU time 29.08 seconds
Started Mar 17 02:16:24 PM PDT 24
Finished Mar 17 02:16:53 PM PDT 24
Peak memory 247416 kb
Host smart-42d1ef07-1b6c-41aa-99fd-590731021f16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29123
58663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.2912358663
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.4237220776
Short name T492
Test name
Test status
Simulation time 215493291 ps
CPU time 14.13 seconds
Started Mar 17 02:16:25 PM PDT 24
Finished Mar 17 02:16:40 PM PDT 24
Peak memory 255752 kb
Host smart-cceaa334-38f2-4397-9ca1-a6e22c00fdf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42372
20776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.4237220776
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.2315520455
Short name T654
Test name
Test status
Simulation time 856311347677 ps
CPU time 5071.31 seconds
Started Mar 17 02:16:30 PM PDT 24
Finished Mar 17 03:41:03 PM PDT 24
Peak memory 322516 kb
Host smart-f9e3179b-2654-4910-891b-8e51719cfd46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315520455 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.2315520455
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.3191683476
Short name T624
Test name
Test status
Simulation time 51821594788 ps
CPU time 837.05 seconds
Started Mar 17 02:16:29 PM PDT 24
Finished Mar 17 02:30:27 PM PDT 24
Peak memory 269832 kb
Host smart-722d7d9f-f628-4c87-b47f-c086f693e317
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191683476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.3191683476
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.1783496537
Short name T40
Test name
Test status
Simulation time 4861346372 ps
CPU time 94.89 seconds
Started Mar 17 02:16:29 PM PDT 24
Finished Mar 17 02:18:04 PM PDT 24
Peak memory 257112 kb
Host smart-260b5237-d69c-4abf-bc65-bb1cdcccc189
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17834
96537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.1783496537
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.2753736384
Short name T498
Test name
Test status
Simulation time 3592481033 ps
CPU time 58.17 seconds
Started Mar 17 02:16:31 PM PDT 24
Finished Mar 17 02:17:30 PM PDT 24
Peak memory 255680 kb
Host smart-469bf96b-5735-48ca-a261-df792e2aae53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27537
36384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2753736384
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.171770224
Short name T48
Test name
Test status
Simulation time 33543857015 ps
CPU time 971.03 seconds
Started Mar 17 02:16:31 PM PDT 24
Finished Mar 17 02:32:43 PM PDT 24
Peak memory 267356 kb
Host smart-c743ab47-cffd-446f-964d-6a046f375dea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171770224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.171770224
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.2120627805
Short name T679
Test name
Test status
Simulation time 51183049677 ps
CPU time 1386.95 seconds
Started Mar 17 02:16:31 PM PDT 24
Finished Mar 17 02:39:40 PM PDT 24
Peak memory 289680 kb
Host smart-9e943761-ba83-4e1b-9f2f-158d763f43bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120627805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.2120627805
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.3338571606
Short name T326
Test name
Test status
Simulation time 11270869547 ps
CPU time 480.66 seconds
Started Mar 17 02:16:29 PM PDT 24
Finished Mar 17 02:24:30 PM PDT 24
Peak memory 247856 kb
Host smart-68429f01-6398-47c5-b725-1b6301004c3c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338571606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.3338571606
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.1119600795
Short name T521
Test name
Test status
Simulation time 463876025 ps
CPU time 19.31 seconds
Started Mar 17 02:16:30 PM PDT 24
Finished Mar 17 02:16:50 PM PDT 24
Peak memory 254424 kb
Host smart-322d0cd0-fbac-439f-a615-c1e5227b4a90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11196
00795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.1119600795
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.142850256
Short name T432
Test name
Test status
Simulation time 1991556707 ps
CPU time 58.91 seconds
Started Mar 17 02:16:30 PM PDT 24
Finished Mar 17 02:17:30 PM PDT 24
Peak memory 255472 kb
Host smart-c1a031d9-9d5c-435e-bf15-684cd12265d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14285
0256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.142850256
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.2384442428
Short name T619
Test name
Test status
Simulation time 857840346 ps
CPU time 26.16 seconds
Started Mar 17 02:16:29 PM PDT 24
Finished Mar 17 02:16:56 PM PDT 24
Peak memory 249100 kb
Host smart-90703132-6db9-41ab-92b3-0224e0a5478a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23844
42428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.2384442428
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.3068068913
Short name T136
Test name
Test status
Simulation time 4168929215 ps
CPU time 18.8 seconds
Started Mar 17 02:16:29 PM PDT 24
Finished Mar 17 02:16:49 PM PDT 24
Peak memory 248972 kb
Host smart-336d5d17-8beb-448d-a742-2d967ced04b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30680
68913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.3068068913
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.738658452
Short name T294
Test name
Test status
Simulation time 58329510004 ps
CPU time 2261.48 seconds
Started Mar 17 02:16:32 PM PDT 24
Finished Mar 17 02:54:15 PM PDT 24
Peak memory 285624 kb
Host smart-055e30b1-b4b9-4c4f-aa28-38fc08bcdbeb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738658452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_han
dler_stress_all.738658452
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.1962407401
Short name T557
Test name
Test status
Simulation time 21547246608 ps
CPU time 1428.63 seconds
Started Mar 17 02:16:36 PM PDT 24
Finished Mar 17 02:40:25 PM PDT 24
Peak memory 268432 kb
Host smart-76e25edf-06d9-4a20-b495-bbee3fcdb66c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962407401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.1962407401
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.1433733413
Short name T138
Test name
Test status
Simulation time 3416869392 ps
CPU time 62.14 seconds
Started Mar 17 02:16:35 PM PDT 24
Finished Mar 17 02:17:38 PM PDT 24
Peak memory 256644 kb
Host smart-eac9827d-f242-42eb-807a-a729391ab325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14337
33413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.1433733413
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.4248767228
Short name T24
Test name
Test status
Simulation time 376036758 ps
CPU time 26.31 seconds
Started Mar 17 02:16:36 PM PDT 24
Finished Mar 17 02:17:03 PM PDT 24
Peak memory 253768 kb
Host smart-44446065-fcfd-4ff5-b69d-8fe9fb138134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42487
67228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.4248767228
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.4246820814
Short name T677
Test name
Test status
Simulation time 72983217377 ps
CPU time 1196.54 seconds
Started Mar 17 02:16:36 PM PDT 24
Finished Mar 17 02:36:33 PM PDT 24
Peak memory 273392 kb
Host smart-0c810ca3-ce6a-415a-888b-1852a755e3fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246820814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.4246820814
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.3501401007
Short name T500
Test name
Test status
Simulation time 17623862978 ps
CPU time 1307.82 seconds
Started Mar 17 02:16:36 PM PDT 24
Finished Mar 17 02:38:24 PM PDT 24
Peak memory 283900 kb
Host smart-2305914d-682d-4910-bd41-3b68a96d1561
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501401007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.3501401007
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.343827316
Short name T651
Test name
Test status
Simulation time 8102101777 ps
CPU time 305.45 seconds
Started Mar 17 02:16:35 PM PDT 24
Finished Mar 17 02:21:41 PM PDT 24
Peak memory 248068 kb
Host smart-97fce9ba-aef0-41c8-a90b-ba83d26ed7cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343827316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.343827316
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.2018255462
Short name T411
Test name
Test status
Simulation time 4582407302 ps
CPU time 72.13 seconds
Started Mar 17 02:16:30 PM PDT 24
Finished Mar 17 02:17:43 PM PDT 24
Peak memory 257064 kb
Host smart-727253db-1641-4a15-a072-4737082cb8d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20182
55462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.2018255462
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.2374062806
Short name T514
Test name
Test status
Simulation time 338970919 ps
CPU time 9.17 seconds
Started Mar 17 02:16:36 PM PDT 24
Finished Mar 17 02:16:45 PM PDT 24
Peak memory 248820 kb
Host smart-15f06ef4-a35e-4f04-b18d-5e84d6ac5b1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23740
62806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.2374062806
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.1866607962
Short name T530
Test name
Test status
Simulation time 362765344 ps
CPU time 38.42 seconds
Started Mar 17 02:16:31 PM PDT 24
Finished Mar 17 02:17:10 PM PDT 24
Peak memory 255876 kb
Host smart-03ba88ed-b723-4737-b91e-74eb2dbe7bc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18666
07962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.1866607962
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.2179961138
Short name T87
Test name
Test status
Simulation time 1808347436 ps
CPU time 159.62 seconds
Started Mar 17 02:16:41 PM PDT 24
Finished Mar 17 02:19:20 PM PDT 24
Peak memory 257064 kb
Host smart-feadb903-f988-4dd0-8a24-8dc4a640443f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179961138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.2179961138
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.1434547132
Short name T72
Test name
Test status
Simulation time 32208346182 ps
CPU time 2004.68 seconds
Started Mar 17 02:16:41 PM PDT 24
Finished Mar 17 02:50:06 PM PDT 24
Peak memory 268340 kb
Host smart-27b9482f-b170-46b6-8d85-f0f0dc57689a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434547132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.1434547132
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.2561097404
Short name T578
Test name
Test status
Simulation time 4223958530 ps
CPU time 255.9 seconds
Started Mar 17 02:16:42 PM PDT 24
Finished Mar 17 02:20:59 PM PDT 24
Peak memory 257068 kb
Host smart-ec8fafa3-4017-44a4-9caf-7899c8cc5a9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25610
97404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.2561097404
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.2371472881
Short name T540
Test name
Test status
Simulation time 156701748 ps
CPU time 7.64 seconds
Started Mar 17 02:16:46 PM PDT 24
Finished Mar 17 02:16:54 PM PDT 24
Peak memory 249568 kb
Host smart-a6587cb7-54b8-4198-819d-c9ce1527f887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23714
72881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.2371472881
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.3913830850
Short name T355
Test name
Test status
Simulation time 536445693961 ps
CPU time 1900.09 seconds
Started Mar 17 02:16:47 PM PDT 24
Finished Mar 17 02:48:27 PM PDT 24
Peak memory 267368 kb
Host smart-bb11fdab-846d-481d-afd5-af8bb2da1d5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913830850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.3913830850
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.3186274395
Short name T15
Test name
Test status
Simulation time 361951725689 ps
CPU time 2129.3 seconds
Started Mar 17 02:16:42 PM PDT 24
Finished Mar 17 02:52:11 PM PDT 24
Peak memory 270428 kb
Host smart-1a575933-dff1-40b3-908b-d04ab261becd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186274395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.3186274395
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.142269367
Short name T574
Test name
Test status
Simulation time 683424408 ps
CPU time 22.06 seconds
Started Mar 17 02:16:46 PM PDT 24
Finished Mar 17 02:17:08 PM PDT 24
Peak memory 248868 kb
Host smart-ba3ef14a-7c8e-430b-b2f3-27511c55efac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14226
9367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.142269367
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.1050294809
Short name T39
Test name
Test status
Simulation time 366700060 ps
CPU time 47.11 seconds
Started Mar 17 02:16:40 PM PDT 24
Finished Mar 17 02:17:27 PM PDT 24
Peak memory 256708 kb
Host smart-c2d945a8-7167-435c-accc-39d67112a416
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10502
94809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.1050294809
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.2773479599
Short name T610
Test name
Test status
Simulation time 16266425961 ps
CPU time 60.87 seconds
Started Mar 17 02:16:42 PM PDT 24
Finished Mar 17 02:17:43 PM PDT 24
Peak memory 255464 kb
Host smart-85af123e-370b-4229-8370-bfb3abc46bcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27734
79599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.2773479599
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.2865786207
Short name T252
Test name
Test status
Simulation time 183024201 ps
CPU time 21.21 seconds
Started Mar 17 02:16:41 PM PDT 24
Finished Mar 17 02:17:03 PM PDT 24
Peak memory 248892 kb
Host smart-395a2f8b-b69d-4d71-860f-f323693c2861
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28657
86207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.2865786207
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.1079170680
Short name T282
Test name
Test status
Simulation time 184393843297 ps
CPU time 2697.4 seconds
Started Mar 17 02:16:40 PM PDT 24
Finished Mar 17 03:01:38 PM PDT 24
Peak memory 289120 kb
Host smart-7f91eaf6-f5e5-46df-91d7-88cea5aa810e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079170680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.1079170680
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.3678267948
Short name T568
Test name
Test status
Simulation time 57061976656 ps
CPU time 4109.11 seconds
Started Mar 17 02:16:45 PM PDT 24
Finished Mar 17 03:25:15 PM PDT 24
Peak memory 306044 kb
Host smart-d51828c1-2468-4a65-b36d-812edcc802b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678267948 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.3678267948
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.4107774901
Short name T104
Test name
Test status
Simulation time 78465150253 ps
CPU time 2468.96 seconds
Started Mar 17 02:16:48 PM PDT 24
Finished Mar 17 02:57:57 PM PDT 24
Peak memory 289540 kb
Host smart-0f04857b-84db-4b59-96b3-6bf28d18e328
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107774901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.4107774901
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.1780613672
Short name T477
Test name
Test status
Simulation time 3154407736 ps
CPU time 54.17 seconds
Started Mar 17 02:16:48 PM PDT 24
Finished Mar 17 02:17:42 PM PDT 24
Peak memory 256408 kb
Host smart-fe05a940-b5e3-4443-b786-ab90f4dab51b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17806
13672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.1780613672
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.2797707131
Short name T628
Test name
Test status
Simulation time 567535683 ps
CPU time 30.51 seconds
Started Mar 17 02:16:47 PM PDT 24
Finished Mar 17 02:17:17 PM PDT 24
Peak memory 255624 kb
Host smart-352c7ae2-700f-4d12-93dd-bef727e552df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27977
07131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2797707131
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.379173832
Short name T670
Test name
Test status
Simulation time 19297191636 ps
CPU time 1559.12 seconds
Started Mar 17 02:16:54 PM PDT 24
Finished Mar 17 02:42:54 PM PDT 24
Peak memory 289024 kb
Host smart-226942d6-139d-40f9-9315-355302ea51e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379173832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.379173832
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3906873339
Short name T526
Test name
Test status
Simulation time 36375070652 ps
CPU time 2154.68 seconds
Started Mar 17 02:16:55 PM PDT 24
Finished Mar 17 02:52:50 PM PDT 24
Peak memory 273508 kb
Host smart-827a1f5f-14b2-4a0b-b049-b5f318cbccce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906873339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3906873339
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.3976943179
Short name T672
Test name
Test status
Simulation time 222805916 ps
CPU time 18.93 seconds
Started Mar 17 02:16:45 PM PDT 24
Finished Mar 17 02:17:04 PM PDT 24
Peak memory 249016 kb
Host smart-09688416-d250-4de8-9f12-42e7801e06f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39769
43179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.3976943179
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.2956766218
Short name T409
Test name
Test status
Simulation time 979338538 ps
CPU time 59.4 seconds
Started Mar 17 02:16:46 PM PDT 24
Finished Mar 17 02:17:46 PM PDT 24
Peak memory 256060 kb
Host smart-970a778c-a9a6-4808-a570-8cdb28973110
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29567
66218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.2956766218
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.2858855315
Short name T290
Test name
Test status
Simulation time 39476492480 ps
CPU time 2352.77 seconds
Started Mar 17 02:16:53 PM PDT 24
Finished Mar 17 02:56:06 PM PDT 24
Peak memory 283072 kb
Host smart-8cb427fb-9163-4575-a5a8-831da33526cc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858855315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.2858855315
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.3560394493
Short name T54
Test name
Test status
Simulation time 20491512238 ps
CPU time 2279.46 seconds
Started Mar 17 02:16:54 PM PDT 24
Finished Mar 17 02:54:54 PM PDT 24
Peak memory 304320 kb
Host smart-a7ebc976-9fa9-4d21-966b-2ada9d5009ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560394493 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.3560394493
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.4091382743
Short name T314
Test name
Test status
Simulation time 142096884233 ps
CPU time 2229.5 seconds
Started Mar 17 02:16:57 PM PDT 24
Finished Mar 17 02:54:07 PM PDT 24
Peak memory 281708 kb
Host smart-6ae68176-455e-4bad-943e-2f6524d55042
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091382743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.4091382743
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.3920540526
Short name T452
Test name
Test status
Simulation time 1067869423 ps
CPU time 51.38 seconds
Started Mar 17 02:16:54 PM PDT 24
Finished Mar 17 02:17:46 PM PDT 24
Peak memory 256580 kb
Host smart-5d910a80-9858-4715-a26c-ff18c5a53d49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39205
40526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.3920540526
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.2815103282
Short name T127
Test name
Test status
Simulation time 565841930 ps
CPU time 21.76 seconds
Started Mar 17 02:16:57 PM PDT 24
Finished Mar 17 02:17:19 PM PDT 24
Peak memory 255596 kb
Host smart-3ebdf9ed-ceaa-42e3-8c99-ed905e5e1bd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28151
03282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.2815103282
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.2781764399
Short name T362
Test name
Test status
Simulation time 26416065091 ps
CPU time 1334.47 seconds
Started Mar 17 02:16:52 PM PDT 24
Finished Mar 17 02:39:07 PM PDT 24
Peak memory 281812 kb
Host smart-73db8364-f8d6-49d9-967f-7ab38f1fa14a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781764399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.2781764399
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.253595958
Short name T575
Test name
Test status
Simulation time 23994836489 ps
CPU time 1615.92 seconds
Started Mar 17 02:16:59 PM PDT 24
Finished Mar 17 02:43:55 PM PDT 24
Peak memory 265344 kb
Host smart-485bf1aa-7324-40e6-a205-f3823f2f58a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253595958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.253595958
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.4235014258
Short name T259
Test name
Test status
Simulation time 9490794858 ps
CPU time 390.89 seconds
Started Mar 17 02:16:57 PM PDT 24
Finished Mar 17 02:23:28 PM PDT 24
Peak memory 248116 kb
Host smart-bca0e879-b152-4c4d-a9c7-611a0d5864c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235014258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.4235014258
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2844613304
Short name T421
Test name
Test status
Simulation time 621483355 ps
CPU time 34.58 seconds
Started Mar 17 02:16:54 PM PDT 24
Finished Mar 17 02:17:29 PM PDT 24
Peak memory 255736 kb
Host smart-186fde37-d0c6-44e1-a142-ea2eaac52536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28446
13304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2844613304
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.3845305732
Short name T537
Test name
Test status
Simulation time 170526324 ps
CPU time 11.07 seconds
Started Mar 17 02:16:53 PM PDT 24
Finished Mar 17 02:17:04 PM PDT 24
Peak memory 254316 kb
Host smart-35a53e82-39f1-4a02-a489-0963be93fba2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38453
05732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.3845305732
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.84790258
Short name T438
Test name
Test status
Simulation time 216793642 ps
CPU time 4.37 seconds
Started Mar 17 02:16:53 PM PDT 24
Finished Mar 17 02:16:58 PM PDT 24
Peak memory 240620 kb
Host smart-b070f764-2a97-4a2f-b291-8f34ff736081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84790
258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.84790258
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.3594290488
Short name T98
Test name
Test status
Simulation time 1757669219 ps
CPU time 13.77 seconds
Started Mar 17 02:16:53 PM PDT 24
Finished Mar 17 02:17:07 PM PDT 24
Peak memory 248888 kb
Host smart-ab772e2a-a66d-405a-a8ff-32061721e071
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35942
90488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.3594290488
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.2575938484
Short name T279
Test name
Test status
Simulation time 149714541979 ps
CPU time 1787.4 seconds
Started Mar 17 02:16:59 PM PDT 24
Finished Mar 17 02:46:46 PM PDT 24
Peak memory 273120 kb
Host smart-905043bb-56e7-4391-a050-7b60998b91b5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575938484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.2575938484
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.1293596708
Short name T579
Test name
Test status
Simulation time 4926626155 ps
CPU time 264.14 seconds
Started Mar 17 02:17:02 PM PDT 24
Finished Mar 17 02:21:26 PM PDT 24
Peak memory 251408 kb
Host smart-7dcf8c2f-4b03-4389-a765-1716ef1c159a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12935
96708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.1293596708
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.1521585935
Short name T564
Test name
Test status
Simulation time 490764932 ps
CPU time 33.71 seconds
Started Mar 17 02:17:00 PM PDT 24
Finished Mar 17 02:17:33 PM PDT 24
Peak memory 255736 kb
Host smart-ab37f687-5b9f-4b1e-80b7-00e98fefab17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15215
85935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.1521585935
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.2868712937
Short name T101
Test name
Test status
Simulation time 22026240604 ps
CPU time 1417.44 seconds
Started Mar 17 02:17:06 PM PDT 24
Finished Mar 17 02:40:44 PM PDT 24
Peak memory 273468 kb
Host smart-c65f6f1a-30da-409d-ab69-d398d95cf845
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868712937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.2868712937
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.1354542958
Short name T664
Test name
Test status
Simulation time 8038274715 ps
CPU time 349.12 seconds
Started Mar 17 02:17:04 PM PDT 24
Finished Mar 17 02:22:53 PM PDT 24
Peak memory 248236 kb
Host smart-4cb22e5c-b41b-4f02-a8b4-6e2764ff1a83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354542958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.1354542958
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.18976002
Short name T692
Test name
Test status
Simulation time 110387939 ps
CPU time 14.94 seconds
Started Mar 17 02:16:58 PM PDT 24
Finished Mar 17 02:17:13 PM PDT 24
Peak memory 254224 kb
Host smart-f990a853-cc16-4c1e-bbc3-82d304a8c780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18976
002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.18976002
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.2308664435
Short name T561
Test name
Test status
Simulation time 249757340 ps
CPU time 14.88 seconds
Started Mar 17 02:17:00 PM PDT 24
Finished Mar 17 02:17:15 PM PDT 24
Peak memory 247524 kb
Host smart-d748972c-f4ad-4ab2-98b6-34e6006d2221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23086
64435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.2308664435
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.1404300260
Short name T586
Test name
Test status
Simulation time 1413874670 ps
CPU time 48.21 seconds
Started Mar 17 02:16:59 PM PDT 24
Finished Mar 17 02:17:47 PM PDT 24
Peak memory 248852 kb
Host smart-c28481ea-224a-48f2-8a51-e3f4a6822183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14043
00260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.1404300260
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.2993019529
Short name T694
Test name
Test status
Simulation time 101527373 ps
CPU time 9.73 seconds
Started Mar 17 02:17:00 PM PDT 24
Finished Mar 17 02:17:10 PM PDT 24
Peak memory 249140 kb
Host smart-0b5b3649-9567-4b92-b900-48e395adf49f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29930
19529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.2993019529
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.2073768451
Short name T275
Test name
Test status
Simulation time 170718437825 ps
CPU time 2514.74 seconds
Started Mar 17 02:17:05 PM PDT 24
Finished Mar 17 02:59:00 PM PDT 24
Peak memory 289396 kb
Host smart-085e68ec-81c4-46b1-a7b4-763609d28f1a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073768451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.2073768451
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.2089730765
Short name T238
Test name
Test status
Simulation time 47081164 ps
CPU time 3.89 seconds
Started Mar 17 02:14:54 PM PDT 24
Finished Mar 17 02:14:58 PM PDT 24
Peak memory 249024 kb
Host smart-4a99c739-148f-49d8-8725-86e9dbeaf160
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2089730765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.2089730765
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.1868876800
Short name T539
Test name
Test status
Simulation time 139381781125 ps
CPU time 2337.1 seconds
Started Mar 17 02:14:52 PM PDT 24
Finished Mar 17 02:53:49 PM PDT 24
Peak memory 281660 kb
Host smart-6a5d779b-bf41-4be9-9fde-8d46ab3e4d35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868876800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.1868876800
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.3111708548
Short name T399
Test name
Test status
Simulation time 2592819250 ps
CPU time 147.64 seconds
Started Mar 17 02:14:49 PM PDT 24
Finished Mar 17 02:17:17 PM PDT 24
Peak memory 257032 kb
Host smart-0f39f849-85de-46c5-a806-f41a814543d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31117
08548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.3111708548
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.3846977121
Short name T393
Test name
Test status
Simulation time 349542340 ps
CPU time 33.8 seconds
Started Mar 17 02:14:49 PM PDT 24
Finished Mar 17 02:15:23 PM PDT 24
Peak memory 255984 kb
Host smart-25da74ea-6be3-40f9-938f-bdc5ab97779a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38469
77121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.3846977121
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.607909476
Short name T396
Test name
Test status
Simulation time 35363810651 ps
CPU time 783.63 seconds
Started Mar 17 02:15:04 PM PDT 24
Finished Mar 17 02:28:09 PM PDT 24
Peak memory 267400 kb
Host smart-e84c9086-c291-46fe-a86e-fbcd76cb7e41
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607909476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.607909476
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.1882563055
Short name T600
Test name
Test status
Simulation time 8796108043 ps
CPU time 371.89 seconds
Started Mar 17 02:15:05 PM PDT 24
Finished Mar 17 02:21:18 PM PDT 24
Peak memory 247116 kb
Host smart-866e0443-7adc-4bdc-ac07-b58226bcb974
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882563055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.1882563055
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.3989867047
Short name T601
Test name
Test status
Simulation time 240678079 ps
CPU time 21.88 seconds
Started Mar 17 02:14:52 PM PDT 24
Finished Mar 17 02:15:14 PM PDT 24
Peak memory 248768 kb
Host smart-770eef45-061f-49de-ba5e-a21120e5e03c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39898
67047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.3989867047
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.704378948
Short name T473
Test name
Test status
Simulation time 313710706 ps
CPU time 26.94 seconds
Started Mar 17 02:14:47 PM PDT 24
Finished Mar 17 02:15:15 PM PDT 24
Peak memory 255424 kb
Host smart-746bad24-67c4-46ce-9920-995a63cb2115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70437
8948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.704378948
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.4034763909
Short name T35
Test name
Test status
Simulation time 1384635781 ps
CPU time 23.18 seconds
Started Mar 17 02:14:55 PM PDT 24
Finished Mar 17 02:15:18 PM PDT 24
Peak memory 273932 kb
Host smart-7ee334a0-578d-4105-b319-38eb4accb268
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4034763909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.4034763909
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.4220600337
Short name T84
Test name
Test status
Simulation time 249226202 ps
CPU time 5.51 seconds
Started Mar 17 02:14:48 PM PDT 24
Finished Mar 17 02:14:55 PM PDT 24
Peak memory 239084 kb
Host smart-ced75e89-ae71-4479-8204-30f57ac16b2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42206
00337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.4220600337
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.327974050
Short name T79
Test name
Test status
Simulation time 1148264347 ps
CPU time 18.71 seconds
Started Mar 17 02:14:49 PM PDT 24
Finished Mar 17 02:15:09 PM PDT 24
Peak memory 248784 kb
Host smart-9d04fda7-0aa6-41aa-b701-e90df14f0fb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32797
4050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.327974050
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.3236984177
Short name T281
Test name
Test status
Simulation time 114386927005 ps
CPU time 2151.61 seconds
Started Mar 17 02:14:58 PM PDT 24
Finished Mar 17 02:50:50 PM PDT 24
Peak memory 289924 kb
Host smart-c7a042a7-d694-46a6-b52f-45f04f90656d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236984177 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.3236984177
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.3572414579
Short name T550
Test name
Test status
Simulation time 30494899491 ps
CPU time 2285.04 seconds
Started Mar 17 02:17:09 PM PDT 24
Finished Mar 17 02:55:14 PM PDT 24
Peak memory 289556 kb
Host smart-a6bd6656-57dd-4299-b918-b5a6852e358f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572414579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.3572414579
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.4145700649
Short name T584
Test name
Test status
Simulation time 21318263768 ps
CPU time 203.53 seconds
Started Mar 17 02:17:15 PM PDT 24
Finished Mar 17 02:20:38 PM PDT 24
Peak memory 256684 kb
Host smart-f7a7ab37-b7a9-4a55-b5ea-385dda1e8887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41457
00649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.4145700649
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.2132159226
Short name T402
Test name
Test status
Simulation time 3546110122 ps
CPU time 58.53 seconds
Started Mar 17 02:17:10 PM PDT 24
Finished Mar 17 02:18:09 PM PDT 24
Peak memory 248976 kb
Host smart-0566f20e-e62b-4c30-95d6-38473419c20b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21321
59226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.2132159226
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.89844679
Short name T318
Test name
Test status
Simulation time 28617648360 ps
CPU time 1790.81 seconds
Started Mar 17 02:17:10 PM PDT 24
Finished Mar 17 02:47:01 PM PDT 24
Peak memory 273088 kb
Host smart-d5da73bf-fb35-4cc7-9928-1bff47599eb5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89844679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.89844679
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.937828655
Short name T67
Test name
Test status
Simulation time 62681557032 ps
CPU time 1534.36 seconds
Started Mar 17 02:17:09 PM PDT 24
Finished Mar 17 02:42:44 PM PDT 24
Peak memory 288844 kb
Host smart-e783f633-263e-4b70-a7ef-497c77e8bd7e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937828655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.937828655
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.3394646647
Short name T320
Test name
Test status
Simulation time 13048381113 ps
CPU time 550.2 seconds
Started Mar 17 02:17:13 PM PDT 24
Finished Mar 17 02:26:24 PM PDT 24
Peak memory 247992 kb
Host smart-9c173247-1fdf-45d3-a4cf-4cb998e4cf97
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394646647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.3394646647
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.415603433
Short name T43
Test name
Test status
Simulation time 1279069249 ps
CPU time 14.98 seconds
Started Mar 17 02:17:15 PM PDT 24
Finished Mar 17 02:17:30 PM PDT 24
Peak memory 248836 kb
Host smart-f48ec0b3-7361-4870-8e34-c117343a8277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41560
3433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.415603433
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.1504343425
Short name T311
Test name
Test status
Simulation time 1037149548 ps
CPU time 35.86 seconds
Started Mar 17 02:17:10 PM PDT 24
Finished Mar 17 02:17:46 PM PDT 24
Peak memory 256988 kb
Host smart-ecdd834e-b98a-423b-a5b9-a5c5d528591a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15043
43425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.1504343425
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.333403783
Short name T648
Test name
Test status
Simulation time 1017498878 ps
CPU time 40.7 seconds
Started Mar 17 02:17:10 PM PDT 24
Finished Mar 17 02:17:51 PM PDT 24
Peak memory 247956 kb
Host smart-2e0cfcb4-071b-43fd-a6a4-da9a9321bef3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33340
3783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.333403783
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.913631291
Short name T83
Test name
Test status
Simulation time 3949949221 ps
CPU time 66.64 seconds
Started Mar 17 02:17:04 PM PDT 24
Finished Mar 17 02:18:11 PM PDT 24
Peak memory 256020 kb
Host smart-c0623140-e472-4f49-8484-0e5d20fc0c42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91363
1291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.913631291
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.3682851694
Short name T300
Test name
Test status
Simulation time 27685397176 ps
CPU time 1340.93 seconds
Started Mar 17 02:17:15 PM PDT 24
Finished Mar 17 02:39:37 PM PDT 24
Peak memory 289544 kb
Host smart-d620c60c-1a5a-4899-8ad2-da5ffec08404
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682851694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.3682851694
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.4142954014
Short name T65
Test name
Test status
Simulation time 21713230026 ps
CPU time 304.65 seconds
Started Mar 17 02:17:17 PM PDT 24
Finished Mar 17 02:22:22 PM PDT 24
Peak memory 256828 kb
Host smart-efad67f5-bbbb-4e80-b898-292324cd9023
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41429
54014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.4142954014
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.2642625024
Short name T440
Test name
Test status
Simulation time 641845829 ps
CPU time 40.14 seconds
Started Mar 17 02:17:14 PM PDT 24
Finished Mar 17 02:17:54 PM PDT 24
Peak memory 254844 kb
Host smart-2c734f98-6680-4cfb-b340-183ceef41e50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26426
25024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.2642625024
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.2955050694
Short name T350
Test name
Test status
Simulation time 54764273211 ps
CPU time 2436.47 seconds
Started Mar 17 02:17:14 PM PDT 24
Finished Mar 17 02:57:51 PM PDT 24
Peak memory 287228 kb
Host smart-09343f2c-8af0-438c-ae85-76f45e0974bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955050694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.2955050694
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.1010081446
Short name T676
Test name
Test status
Simulation time 36239293430 ps
CPU time 1607.68 seconds
Started Mar 17 02:17:15 PM PDT 24
Finished Mar 17 02:44:03 PM PDT 24
Peak memory 273472 kb
Host smart-6f379b6e-a07f-40d2-95bf-7ef913b831a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010081446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.1010081446
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.491945265
Short name T325
Test name
Test status
Simulation time 20513815127 ps
CPU time 217.79 seconds
Started Mar 17 02:17:15 PM PDT 24
Finished Mar 17 02:20:53 PM PDT 24
Peak memory 247808 kb
Host smart-5ecc2941-7a99-4401-b159-335fe4d96fb2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491945265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.491945265
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.2411746013
Short name T381
Test name
Test status
Simulation time 2225655502 ps
CPU time 25.4 seconds
Started Mar 17 02:17:15 PM PDT 24
Finished Mar 17 02:17:40 PM PDT 24
Peak memory 254484 kb
Host smart-a923a888-b481-49e3-aa8d-d69689b90aef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24117
46013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2411746013
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.3548539606
Short name T376
Test name
Test status
Simulation time 475336183 ps
CPU time 6.86 seconds
Started Mar 17 02:17:15 PM PDT 24
Finished Mar 17 02:17:22 PM PDT 24
Peak memory 247404 kb
Host smart-190ed42c-d50a-4ddc-85ee-9a6e52791f8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35485
39606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.3548539606
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.2760264998
Short name T689
Test name
Test status
Simulation time 1323816782 ps
CPU time 31.66 seconds
Started Mar 17 02:17:16 PM PDT 24
Finished Mar 17 02:17:47 PM PDT 24
Peak memory 255416 kb
Host smart-09f7b10c-e07b-4bca-ac26-4f1306c8df3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27602
64998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.2760264998
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.969666060
Short name T551
Test name
Test status
Simulation time 1558500962 ps
CPU time 11.27 seconds
Started Mar 17 02:17:11 PM PDT 24
Finished Mar 17 02:17:22 PM PDT 24
Peak memory 248888 kb
Host smart-9d997436-26f5-4508-9a2e-9008de355ed7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96966
6060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.969666060
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.721351802
Short name T17
Test name
Test status
Simulation time 702170694 ps
CPU time 23.27 seconds
Started Mar 17 02:17:15 PM PDT 24
Finished Mar 17 02:17:38 PM PDT 24
Peak memory 255652 kb
Host smart-c6e54c84-9306-4082-b580-36caa587ef3f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721351802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_han
dler_stress_all.721351802
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.3718183839
Short name T595
Test name
Test status
Simulation time 101716892037 ps
CPU time 1303.17 seconds
Started Mar 17 02:17:28 PM PDT 24
Finished Mar 17 02:39:11 PM PDT 24
Peak memory 271484 kb
Host smart-bdffcd11-3c40-4328-a060-0550068fd40e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718183839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.3718183839
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.1065061893
Short name T216
Test name
Test status
Simulation time 2042182587 ps
CPU time 168.88 seconds
Started Mar 17 02:17:22 PM PDT 24
Finished Mar 17 02:20:12 PM PDT 24
Peak memory 257008 kb
Host smart-7126edd2-c646-4b4c-b72f-e25fbb61ab5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10650
61893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.1065061893
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.546414582
Short name T253
Test name
Test status
Simulation time 754933934 ps
CPU time 52.48 seconds
Started Mar 17 02:17:21 PM PDT 24
Finished Mar 17 02:18:14 PM PDT 24
Peak memory 255700 kb
Host smart-96a8a0ae-c63a-4bcb-adca-b62d91ba52da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54641
4582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.546414582
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.2249998871
Short name T333
Test name
Test status
Simulation time 183873069578 ps
CPU time 2167.62 seconds
Started Mar 17 02:17:29 PM PDT 24
Finished Mar 17 02:53:37 PM PDT 24
Peak memory 281708 kb
Host smart-c30beb40-27e9-4149-8fc0-fa7a6bff5ec7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249998871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.2249998871
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.844679668
Short name T406
Test name
Test status
Simulation time 106725090380 ps
CPU time 1297.26 seconds
Started Mar 17 02:17:28 PM PDT 24
Finished Mar 17 02:39:06 PM PDT 24
Peak memory 265312 kb
Host smart-69ff9383-31ac-4c63-8fac-d8718ca0d1d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844679668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.844679668
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.3650847293
Short name T652
Test name
Test status
Simulation time 18749575932 ps
CPU time 556.26 seconds
Started Mar 17 02:17:27 PM PDT 24
Finished Mar 17 02:26:44 PM PDT 24
Peak memory 247792 kb
Host smart-80448e20-7b74-433b-a085-bbf5f321e7f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650847293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.3650847293
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.2088464225
Short name T641
Test name
Test status
Simulation time 2106555515 ps
CPU time 29.28 seconds
Started Mar 17 02:17:22 PM PDT 24
Finished Mar 17 02:17:52 PM PDT 24
Peak memory 256728 kb
Host smart-f0b2ada4-d9e1-4985-aff4-4b45a34778e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20884
64225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.2088464225
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.3684984605
Short name T433
Test name
Test status
Simulation time 13724733096 ps
CPU time 45.33 seconds
Started Mar 17 02:17:22 PM PDT 24
Finished Mar 17 02:18:08 PM PDT 24
Peak memory 255324 kb
Host smart-ee654905-098e-4551-84d0-4fcfcb8e027d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36849
84605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.3684984605
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.4178567650
Short name T66
Test name
Test status
Simulation time 1504752705 ps
CPU time 34.02 seconds
Started Mar 17 02:17:28 PM PDT 24
Finished Mar 17 02:18:02 PM PDT 24
Peak memory 255796 kb
Host smart-d5ed6fbb-6cd4-4eed-8d77-fb16c447cf31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41785
67650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.4178567650
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.930281919
Short name T27
Test name
Test status
Simulation time 1231216151 ps
CPU time 31.55 seconds
Started Mar 17 02:17:15 PM PDT 24
Finished Mar 17 02:17:47 PM PDT 24
Peak memory 248960 kb
Host smart-899e0d6d-dda1-420e-87c1-f742eddfce9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93028
1919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.930281919
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.934571468
Short name T317
Test name
Test status
Simulation time 55676463049 ps
CPU time 1297.47 seconds
Started Mar 17 02:17:28 PM PDT 24
Finished Mar 17 02:39:06 PM PDT 24
Peak memory 286792 kb
Host smart-78789a7a-0401-4802-beb8-c8644abd83fe
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934571468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_han
dler_stress_all.934571468
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.3188902158
Short name T643
Test name
Test status
Simulation time 16463455601 ps
CPU time 1079.75 seconds
Started Mar 17 02:17:28 PM PDT 24
Finished Mar 17 02:35:28 PM PDT 24
Peak memory 272404 kb
Host smart-8675372d-8d2f-4fba-9319-fd58dbadac8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188902158 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.3188902158
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.1219927513
Short name T596
Test name
Test status
Simulation time 113285458394 ps
CPU time 3121.67 seconds
Started Mar 17 02:17:29 PM PDT 24
Finished Mar 17 03:09:31 PM PDT 24
Peak memory 289668 kb
Host smart-44a4ed47-147e-4f66-8237-efb76b383ce4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219927513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.1219927513
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.3841993530
Short name T21
Test name
Test status
Simulation time 222374799 ps
CPU time 12.49 seconds
Started Mar 17 02:17:28 PM PDT 24
Finished Mar 17 02:17:41 PM PDT 24
Peak memory 256132 kb
Host smart-4fc257cb-b654-4eeb-939a-c099a5d89856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38419
93530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.3841993530
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.2444205336
Short name T534
Test name
Test status
Simulation time 3131785741 ps
CPU time 51.5 seconds
Started Mar 17 02:17:28 PM PDT 24
Finished Mar 17 02:18:19 PM PDT 24
Peak memory 254516 kb
Host smart-4467b581-62b8-4155-856a-9a7ac7238ee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24442
05336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.2444205336
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.4266438507
Short name T354
Test name
Test status
Simulation time 38234875293 ps
CPU time 2284.49 seconds
Started Mar 17 02:17:33 PM PDT 24
Finished Mar 17 02:55:38 PM PDT 24
Peak memory 288912 kb
Host smart-7d66d3e9-1b82-4710-87bc-0c0c49ff0b30
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266438507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.4266438507
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.2595036204
Short name T658
Test name
Test status
Simulation time 108960319049 ps
CPU time 1773.68 seconds
Started Mar 17 02:17:32 PM PDT 24
Finished Mar 17 02:47:07 PM PDT 24
Peak memory 271552 kb
Host smart-68306494-b768-4658-a308-7bf1a6ff343b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595036204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.2595036204
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.623796107
Short name T341
Test name
Test status
Simulation time 12976298068 ps
CPU time 268.59 seconds
Started Mar 17 02:17:28 PM PDT 24
Finished Mar 17 02:21:57 PM PDT 24
Peak memory 247940 kb
Host smart-296c4e89-fe11-4134-98ea-42dd71226e84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623796107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.623796107
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.3358429292
Short name T33
Test name
Test status
Simulation time 2700098132 ps
CPU time 54.09 seconds
Started Mar 17 02:17:27 PM PDT 24
Finished Mar 17 02:18:21 PM PDT 24
Peak memory 255276 kb
Host smart-0fa82259-96b7-46e4-9784-2914c469458b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33584
29292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.3358429292
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.3121160527
Short name T390
Test name
Test status
Simulation time 306658697 ps
CPU time 23.78 seconds
Started Mar 17 02:17:27 PM PDT 24
Finished Mar 17 02:17:51 PM PDT 24
Peak memory 248764 kb
Host smart-0253aee1-3233-4e33-8aae-a69123b747f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31211
60527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.3121160527
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.1363030540
Short name T565
Test name
Test status
Simulation time 141199179 ps
CPU time 9.83 seconds
Started Mar 17 02:17:28 PM PDT 24
Finished Mar 17 02:17:38 PM PDT 24
Peak memory 257004 kb
Host smart-1b682de4-2f51-4d17-a5b4-0eb9868493c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13630
30540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.1363030540
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.1829587312
Short name T612
Test name
Test status
Simulation time 17574044543 ps
CPU time 306.77 seconds
Started Mar 17 02:17:34 PM PDT 24
Finished Mar 17 02:22:41 PM PDT 24
Peak memory 256988 kb
Host smart-1d65b33b-0868-4ca8-8af8-ecab725255aa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829587312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.1829587312
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.3144390657
Short name T513
Test name
Test status
Simulation time 135074979049 ps
CPU time 2142.15 seconds
Started Mar 17 02:17:39 PM PDT 24
Finished Mar 17 02:53:21 PM PDT 24
Peak memory 281628 kb
Host smart-b8a94e21-a882-4465-b46f-2db5215fb0da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144390657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.3144390657
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.1933431505
Short name T388
Test name
Test status
Simulation time 57369949240 ps
CPU time 308.68 seconds
Started Mar 17 02:17:45 PM PDT 24
Finished Mar 17 02:22:55 PM PDT 24
Peak memory 257036 kb
Host smart-fece5122-f4cf-4ee4-b2c3-9c68ca101ff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19334
31505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1933431505
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.2560920738
Short name T667
Test name
Test status
Simulation time 2004106074 ps
CPU time 63.28 seconds
Started Mar 17 02:17:45 PM PDT 24
Finished Mar 17 02:18:49 PM PDT 24
Peak memory 255680 kb
Host smart-1bbfd27b-7b2a-427b-a21d-12574423c6db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25609
20738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.2560920738
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.1725098753
Short name T603
Test name
Test status
Simulation time 18398373167 ps
CPU time 1170.47 seconds
Started Mar 17 02:17:44 PM PDT 24
Finished Mar 17 02:37:15 PM PDT 24
Peak memory 288300 kb
Host smart-6e2a170f-eeee-4f08-bbf6-5b8e13335e32
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725098753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1725098753
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.810040388
Short name T321
Test name
Test status
Simulation time 21110568259 ps
CPU time 245.27 seconds
Started Mar 17 02:17:45 PM PDT 24
Finished Mar 17 02:21:51 PM PDT 24
Peak memory 248116 kb
Host smart-f703c209-428a-4ef3-803e-fb631ea580a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810040388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.810040388
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.538903458
Short name T503
Test name
Test status
Simulation time 138672909 ps
CPU time 5.64 seconds
Started Mar 17 02:17:35 PM PDT 24
Finished Mar 17 02:17:41 PM PDT 24
Peak memory 240672 kb
Host smart-ed4368ed-e6d9-4176-8835-1e75153d3f38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53890
3458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.538903458
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.1103192162
Short name T604
Test name
Test status
Simulation time 386276648 ps
CPU time 33.2 seconds
Started Mar 17 02:17:33 PM PDT 24
Finished Mar 17 02:18:07 PM PDT 24
Peak memory 248088 kb
Host smart-7a00f1ff-cfa7-4c37-9efa-15eb90a2ba95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11031
92162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.1103192162
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.784269730
Short name T114
Test name
Test status
Simulation time 108744136 ps
CPU time 13.18 seconds
Started Mar 17 02:17:39 PM PDT 24
Finished Mar 17 02:17:52 PM PDT 24
Peak memory 248880 kb
Host smart-08ebd97c-c090-415a-a8b7-11e6b2c3eed6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78426
9730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.784269730
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.3596549587
Short name T705
Test name
Test status
Simulation time 44113021 ps
CPU time 4.01 seconds
Started Mar 17 02:17:33 PM PDT 24
Finished Mar 17 02:17:38 PM PDT 24
Peak memory 240620 kb
Host smart-eba9fc18-6607-48f6-87ba-63597ebddfd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35965
49587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.3596549587
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.4037896570
Short name T287
Test name
Test status
Simulation time 79838156431 ps
CPU time 1854.58 seconds
Started Mar 17 02:17:40 PM PDT 24
Finished Mar 17 02:48:35 PM PDT 24
Peak memory 289772 kb
Host smart-97c26501-f279-4c7a-9b7e-d886762b9c98
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037896570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.4037896570
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.344895612
Short name T255
Test name
Test status
Simulation time 29183720771 ps
CPU time 835.51 seconds
Started Mar 17 02:17:45 PM PDT 24
Finished Mar 17 02:31:41 PM PDT 24
Peak memory 265236 kb
Host smart-84b29344-8027-4de3-ae63-07b6d294781e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344895612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.344895612
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.2822137587
Short name T485
Test name
Test status
Simulation time 5665992436 ps
CPU time 143.86 seconds
Started Mar 17 02:17:44 PM PDT 24
Finished Mar 17 02:20:08 PM PDT 24
Peak memory 256620 kb
Host smart-1afe19a9-cc31-40d9-ab54-a263ada0046b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28221
37587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.2822137587
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.861038588
Short name T453
Test name
Test status
Simulation time 817243491 ps
CPU time 55.37 seconds
Started Mar 17 02:17:44 PM PDT 24
Finished Mar 17 02:18:40 PM PDT 24
Peak memory 255452 kb
Host smart-e9c59924-1a5f-4ad4-9736-24c5ac4014ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86103
8588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.861038588
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.457166589
Short name T493
Test name
Test status
Simulation time 20903851986 ps
CPU time 1803.17 seconds
Started Mar 17 02:17:44 PM PDT 24
Finished Mar 17 02:47:48 PM PDT 24
Peak memory 288988 kb
Host smart-a5cef664-42c7-4780-a845-f061c2320a02
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457166589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.457166589
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.1248743348
Short name T443
Test name
Test status
Simulation time 102238307111 ps
CPU time 1913.28 seconds
Started Mar 17 02:17:50 PM PDT 24
Finished Mar 17 02:49:43 PM PDT 24
Peak memory 273412 kb
Host smart-c7d84473-5348-4f7e-8506-b59d65be7763
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248743348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.1248743348
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.3763481702
Short name T137
Test name
Test status
Simulation time 12974865057 ps
CPU time 241.9 seconds
Started Mar 17 02:17:45 PM PDT 24
Finished Mar 17 02:21:47 PM PDT 24
Peak memory 248108 kb
Host smart-c6173f52-a211-4235-96ca-c5498b85da89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763481702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.3763481702
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.261059097
Short name T140
Test name
Test status
Simulation time 945366843 ps
CPU time 53.16 seconds
Started Mar 17 02:17:44 PM PDT 24
Finished Mar 17 02:18:38 PM PDT 24
Peak memory 248904 kb
Host smart-07f9d040-31b1-48e7-8fe5-384f480fd240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26105
9097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.261059097
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.2510854640
Short name T533
Test name
Test status
Simulation time 3695972732 ps
CPU time 50.74 seconds
Started Mar 17 02:17:43 PM PDT 24
Finished Mar 17 02:18:34 PM PDT 24
Peak memory 256004 kb
Host smart-4126ee15-027b-4095-b80b-fa8111445b6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25108
54640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.2510854640
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.695187019
Short name T289
Test name
Test status
Simulation time 1117424659 ps
CPU time 15.11 seconds
Started Mar 17 02:17:43 PM PDT 24
Finished Mar 17 02:17:58 PM PDT 24
Peak memory 255844 kb
Host smart-6a05e72a-7b94-4910-ab15-3dbb0b0b66c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69518
7019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.695187019
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.1055613876
Short name T221
Test name
Test status
Simulation time 37827230 ps
CPU time 5.97 seconds
Started Mar 17 02:17:44 PM PDT 24
Finished Mar 17 02:17:50 PM PDT 24
Peak memory 248784 kb
Host smart-47825c1f-d9b0-436c-b0a3-21e5a72434c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10556
13876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.1055613876
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.522608566
Short name T30
Test name
Test status
Simulation time 57775705763 ps
CPU time 3510.39 seconds
Started Mar 17 02:17:50 PM PDT 24
Finished Mar 17 03:16:21 PM PDT 24
Peak memory 289244 kb
Host smart-6cf62c18-fdad-4da9-affb-830131e61420
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522608566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_han
dler_stress_all.522608566
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.3091181155
Short name T264
Test name
Test status
Simulation time 90372941451 ps
CPU time 2861.2 seconds
Started Mar 17 02:17:50 PM PDT 24
Finished Mar 17 03:05:32 PM PDT 24
Peak memory 305688 kb
Host smart-751f8dca-d9e8-4c29-b691-f06f7c31933b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091181155 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.3091181155
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.2876412179
Short name T258
Test name
Test status
Simulation time 21859390873 ps
CPU time 1180.74 seconds
Started Mar 17 02:17:56 PM PDT 24
Finished Mar 17 02:37:37 PM PDT 24
Peak memory 272292 kb
Host smart-4097210d-592a-42d5-a0df-39d13d50ef03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876412179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2876412179
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.1804643390
Short name T428
Test name
Test status
Simulation time 23478169235 ps
CPU time 128.59 seconds
Started Mar 17 02:17:56 PM PDT 24
Finished Mar 17 02:20:05 PM PDT 24
Peak memory 256764 kb
Host smart-b10b31de-36f3-4047-b2f1-4bcae8394238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18046
43390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.1804643390
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.64709774
Short name T267
Test name
Test status
Simulation time 461500880 ps
CPU time 26.6 seconds
Started Mar 17 02:17:56 PM PDT 24
Finished Mar 17 02:18:24 PM PDT 24
Peak memory 247412 kb
Host smart-bcc77203-3547-456f-986e-5ac2799047e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64709
774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.64709774
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.3284124654
Short name T356
Test name
Test status
Simulation time 157736887821 ps
CPU time 2605.65 seconds
Started Mar 17 02:18:01 PM PDT 24
Finished Mar 17 03:01:28 PM PDT 24
Peak memory 289236 kb
Host smart-4029d2da-68bc-4d0b-9780-971fd62a745f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284124654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3284124654
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.2422659681
Short name T70
Test name
Test status
Simulation time 151763487527 ps
CPU time 2492.19 seconds
Started Mar 17 02:18:01 PM PDT 24
Finished Mar 17 02:59:34 PM PDT 24
Peak memory 273508 kb
Host smart-245e336c-af8f-4d7f-83b9-652e51740a8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422659681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.2422659681
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.2257293878
Short name T427
Test name
Test status
Simulation time 7594226788 ps
CPU time 167.77 seconds
Started Mar 17 02:17:56 PM PDT 24
Finished Mar 17 02:20:44 PM PDT 24
Peak memory 247848 kb
Host smart-1351448f-fceb-42f7-b871-9f8c1838dfe5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257293878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.2257293878
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.933420421
Short name T529
Test name
Test status
Simulation time 706258295 ps
CPU time 31.48 seconds
Started Mar 17 02:17:50 PM PDT 24
Finished Mar 17 02:18:22 PM PDT 24
Peak memory 248868 kb
Host smart-9ed75453-9485-478b-9f50-3b8301d80bdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93342
0421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.933420421
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.1108218801
Short name T559
Test name
Test status
Simulation time 1314944228 ps
CPU time 21.55 seconds
Started Mar 17 02:17:51 PM PDT 24
Finished Mar 17 02:18:12 PM PDT 24
Peak memory 254992 kb
Host smart-0fca3ab5-3688-4bbd-99d8-1febaaffcc12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11082
18801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.1108218801
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.3942832552
Short name T563
Test name
Test status
Simulation time 597781617 ps
CPU time 5.53 seconds
Started Mar 17 02:17:57 PM PDT 24
Finished Mar 17 02:18:04 PM PDT 24
Peak memory 239164 kb
Host smart-6202aa77-30cb-4e1b-991c-a91366f15317
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39428
32552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.3942832552
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.2308317449
Short name T218
Test name
Test status
Simulation time 1420190024 ps
CPU time 16.89 seconds
Started Mar 17 02:17:49 PM PDT 24
Finished Mar 17 02:18:06 PM PDT 24
Peak memory 248816 kb
Host smart-5d799336-d8bb-438f-b81b-8ebc999ba177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23083
17449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.2308317449
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.2260444975
Short name T283
Test name
Test status
Simulation time 428494437758 ps
CPU time 4078.76 seconds
Started Mar 17 02:18:03 PM PDT 24
Finished Mar 17 03:26:02 PM PDT 24
Peak memory 300864 kb
Host smart-eb2041ab-e248-4a45-a53e-c26818ebb116
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260444975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.2260444975
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.2845304633
Short name T620
Test name
Test status
Simulation time 19558912986 ps
CPU time 1503.61 seconds
Started Mar 17 02:18:09 PM PDT 24
Finished Mar 17 02:43:13 PM PDT 24
Peak memory 281640 kb
Host smart-33c79d18-a7e4-4ca3-b483-9d45558c52c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845304633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.2845304633
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.1581564975
Short name T636
Test name
Test status
Simulation time 1461943678 ps
CPU time 102.16 seconds
Started Mar 17 02:18:09 PM PDT 24
Finished Mar 17 02:19:51 PM PDT 24
Peak memory 256656 kb
Host smart-41f528bd-434b-4501-b427-62d50cc37c26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15815
64975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.1581564975
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.4282945334
Short name T644
Test name
Test status
Simulation time 1956777073 ps
CPU time 50.12 seconds
Started Mar 17 02:18:09 PM PDT 24
Finished Mar 17 02:19:00 PM PDT 24
Peak memory 249088 kb
Host smart-fd710f65-3a90-4caf-adff-e60ee6d4a531
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42829
45334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.4282945334
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.1511085946
Short name T219
Test name
Test status
Simulation time 69273169925 ps
CPU time 2468.53 seconds
Started Mar 17 02:18:09 PM PDT 24
Finished Mar 17 02:59:18 PM PDT 24
Peak memory 281712 kb
Host smart-a3a801f5-5210-4c80-95d9-c9628e02661a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511085946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.1511085946
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.3518651604
Short name T49
Test name
Test status
Simulation time 68714135058 ps
CPU time 1846.89 seconds
Started Mar 17 02:18:11 PM PDT 24
Finished Mar 17 02:48:58 PM PDT 24
Peak memory 273520 kb
Host smart-7cf63d38-887f-4b03-894f-5a06ff0fa192
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518651604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.3518651604
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.3284298835
Short name T330
Test name
Test status
Simulation time 21273872645 ps
CPU time 245.86 seconds
Started Mar 17 02:18:09 PM PDT 24
Finished Mar 17 02:22:15 PM PDT 24
Peak memory 247996 kb
Host smart-1e847df0-1b76-415b-9d7f-9144c87eb3a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284298835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.3284298835
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.3929952915
Short name T444
Test name
Test status
Simulation time 1450801485 ps
CPU time 27.13 seconds
Started Mar 17 02:18:03 PM PDT 24
Finished Mar 17 02:18:31 PM PDT 24
Peak memory 256060 kb
Host smart-04c019ac-5769-4ef5-9b15-1a827ecfba9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39299
52915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.3929952915
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.223235676
Short name T663
Test name
Test status
Simulation time 202626589 ps
CPU time 17.11 seconds
Started Mar 17 02:18:02 PM PDT 24
Finished Mar 17 02:18:19 PM PDT 24
Peak memory 248740 kb
Host smart-011180ad-8086-4fbf-8972-97dd8ea50f8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22323
5676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.223235676
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.1113962189
Short name T468
Test name
Test status
Simulation time 812831930 ps
CPU time 24.58 seconds
Started Mar 17 02:18:10 PM PDT 24
Finished Mar 17 02:18:34 PM PDT 24
Peak memory 254940 kb
Host smart-1cd12c06-38c9-4a7b-8bea-b716d649ca50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11139
62189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.1113962189
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.3630727176
Short name T678
Test name
Test status
Simulation time 904377872 ps
CPU time 24.21 seconds
Started Mar 17 02:18:03 PM PDT 24
Finished Mar 17 02:18:28 PM PDT 24
Peak memory 249120 kb
Host smart-58407e9d-d7ea-47f8-87d7-42ea50660298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36307
27176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.3630727176
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.3565768499
Short name T129
Test name
Test status
Simulation time 43441955686 ps
CPU time 2513.58 seconds
Started Mar 17 02:18:12 PM PDT 24
Finished Mar 17 03:00:06 PM PDT 24
Peak memory 286000 kb
Host smart-c0465d3a-5ef1-4fb2-a669-a9ebc475fd4b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565768499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.3565768499
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.3632437196
Short name T478
Test name
Test status
Simulation time 9961750000 ps
CPU time 1149.63 seconds
Started Mar 17 02:18:15 PM PDT 24
Finished Mar 17 02:37:25 PM PDT 24
Peak memory 281688 kb
Host smart-8363d2c2-f9c9-4fa7-9d8d-46839c53e690
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632437196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.3632437196
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.1041998046
Short name T378
Test name
Test status
Simulation time 1277022712 ps
CPU time 89.03 seconds
Started Mar 17 02:18:15 PM PDT 24
Finished Mar 17 02:19:44 PM PDT 24
Peak memory 248556 kb
Host smart-d71b718f-57f1-4608-82a2-e20e8ba98054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10419
98046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.1041998046
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.2919268412
Short name T420
Test name
Test status
Simulation time 352810008 ps
CPU time 39.1 seconds
Started Mar 17 02:18:14 PM PDT 24
Finished Mar 17 02:18:53 PM PDT 24
Peak memory 255444 kb
Host smart-9e1b67c8-638b-4720-a7fc-6ef0811776ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29192
68412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.2919268412
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.3920027510
Short name T581
Test name
Test status
Simulation time 69196187890 ps
CPU time 2073.16 seconds
Started Mar 17 02:18:16 PM PDT 24
Finished Mar 17 02:52:49 PM PDT 24
Peak memory 287004 kb
Host smart-96f65f10-5bce-456f-b3dc-7b64721e2c12
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920027510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.3920027510
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.3640045845
Short name T690
Test name
Test status
Simulation time 40777747022 ps
CPU time 380.75 seconds
Started Mar 17 02:18:14 PM PDT 24
Finished Mar 17 02:24:35 PM PDT 24
Peak memory 248932 kb
Host smart-61fbf1ce-fd31-4d53-8db1-1a3a7c50ea9e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640045845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.3640045845
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.3627530211
Short name T562
Test name
Test status
Simulation time 1414182683 ps
CPU time 31.86 seconds
Started Mar 17 02:18:17 PM PDT 24
Finished Mar 17 02:18:48 PM PDT 24
Peak memory 256152 kb
Host smart-ec131ea5-1516-4aad-8a69-8778cd117804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36275
30211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.3627530211
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.2948169533
Short name T222
Test name
Test status
Simulation time 293402629 ps
CPU time 38.84 seconds
Started Mar 17 02:18:16 PM PDT 24
Finished Mar 17 02:18:55 PM PDT 24
Peak memory 247680 kb
Host smart-418fd9c3-be0f-4531-b0a4-b7be66f7bbb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29481
69533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.2948169533
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.3030493319
Short name T491
Test name
Test status
Simulation time 165362498 ps
CPU time 4.79 seconds
Started Mar 17 02:18:14 PM PDT 24
Finished Mar 17 02:18:19 PM PDT 24
Peak memory 239156 kb
Host smart-3fbf13bc-669d-4cf2-9c57-62a334397f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30304
93319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3030493319
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.2117298284
Short name T251
Test name
Test status
Simulation time 464187709 ps
CPU time 7.51 seconds
Started Mar 17 02:18:09 PM PDT 24
Finished Mar 17 02:18:17 PM PDT 24
Peak memory 248820 kb
Host smart-275494d6-6729-418c-8b92-efcced53071d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21172
98284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.2117298284
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.404837629
Short name T609
Test name
Test status
Simulation time 65643616771 ps
CPU time 1066.96 seconds
Started Mar 17 02:18:24 PM PDT 24
Finished Mar 17 02:36:11 PM PDT 24
Peak memory 289340 kb
Host smart-6d9c1c64-a33b-44f6-a964-c7f188c551ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404837629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.404837629
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.644540594
Short name T484
Test name
Test status
Simulation time 976903009 ps
CPU time 26.43 seconds
Started Mar 17 02:18:21 PM PDT 24
Finished Mar 17 02:18:47 PM PDT 24
Peak memory 256732 kb
Host smart-9a939e02-4673-4f9b-9e12-0eddc00d165b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64454
0594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.644540594
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.1627865357
Short name T510
Test name
Test status
Simulation time 233969765 ps
CPU time 20.65 seconds
Started Mar 17 02:18:23 PM PDT 24
Finished Mar 17 02:18:44 PM PDT 24
Peak memory 255320 kb
Host smart-875d3e4e-be58-43c4-96fc-c78c4ecc0915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16278
65357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.1627865357
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.3569129807
Short name T451
Test name
Test status
Simulation time 20625220452 ps
CPU time 1171.4 seconds
Started Mar 17 02:18:20 PM PDT 24
Finished Mar 17 02:37:52 PM PDT 24
Peak memory 269424 kb
Host smart-bef3364f-11dc-4de4-9ad8-682b22fba3fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569129807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.3569129807
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.1300465348
Short name T42
Test name
Test status
Simulation time 929843501908 ps
CPU time 3391.02 seconds
Started Mar 17 02:18:21 PM PDT 24
Finished Mar 17 03:14:52 PM PDT 24
Peak memory 289856 kb
Host smart-61a89444-08a5-475b-b281-0ce8f501c1d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300465348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.1300465348
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.3323661257
Short name T522
Test name
Test status
Simulation time 56041319955 ps
CPU time 585.96 seconds
Started Mar 17 02:18:21 PM PDT 24
Finished Mar 17 02:28:07 PM PDT 24
Peak memory 246832 kb
Host smart-f150b490-a9a8-470f-b9b4-11461bf2f2d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323661257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.3323661257
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.654969971
Short name T504
Test name
Test status
Simulation time 1844350307 ps
CPU time 50.42 seconds
Started Mar 17 02:18:22 PM PDT 24
Finished Mar 17 02:19:13 PM PDT 24
Peak memory 255468 kb
Host smart-6ac8d2b2-3b6f-4d37-9169-516c777161a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65496
9971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.654969971
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.2659016120
Short name T517
Test name
Test status
Simulation time 757367362 ps
CPU time 16.23 seconds
Started Mar 17 02:18:20 PM PDT 24
Finished Mar 17 02:18:37 PM PDT 24
Peak memory 255900 kb
Host smart-9e15dee6-747f-418b-9936-c9af543b6d6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26590
16120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2659016120
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.1473359279
Short name T570
Test name
Test status
Simulation time 3323384565 ps
CPU time 54.37 seconds
Started Mar 17 02:18:22 PM PDT 24
Finished Mar 17 02:19:16 PM PDT 24
Peak memory 248884 kb
Host smart-19e3b893-84f0-428b-883b-f30ea53fd27b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14733
59279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.1473359279
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.3516551423
Short name T488
Test name
Test status
Simulation time 2735198971 ps
CPU time 45.04 seconds
Started Mar 17 02:18:23 PM PDT 24
Finished Mar 17 02:19:08 PM PDT 24
Peak memory 248888 kb
Host smart-9926ac1e-31d2-4b8e-a3f5-6d339d8dd6e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35165
51423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.3516551423
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.4155189630
Short name T134
Test name
Test status
Simulation time 46825073753 ps
CPU time 2803.96 seconds
Started Mar 17 02:18:26 PM PDT 24
Finished Mar 17 03:05:11 PM PDT 24
Peak memory 286784 kb
Host smart-68042fb4-cdb6-4b0f-80b8-7462b850d196
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155189630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.4155189630
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.1670764267
Short name T76
Test name
Test status
Simulation time 59909417467 ps
CPU time 3755.89 seconds
Started Mar 17 02:18:26 PM PDT 24
Finished Mar 17 03:21:02 PM PDT 24
Peak memory 282440 kb
Host smart-afb9c5c4-4d56-45c8-ad17-d6325820c40a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670764267 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.1670764267
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.3145352294
Short name T19
Test name
Test status
Simulation time 61503900 ps
CPU time 3.26 seconds
Started Mar 17 02:15:00 PM PDT 24
Finished Mar 17 02:15:03 PM PDT 24
Peak memory 248968 kb
Host smart-c3591015-6cd6-43b7-bda9-032a21cc677b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3145352294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.3145352294
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.1519749557
Short name T686
Test name
Test status
Simulation time 67096734395 ps
CPU time 777.97 seconds
Started Mar 17 02:14:56 PM PDT 24
Finished Mar 17 02:27:54 PM PDT 24
Peak memory 273024 kb
Host smart-f7625f0c-4c6a-4e37-8ed6-e67d9678c649
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519749557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.1519749557
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.2402301480
Short name T625
Test name
Test status
Simulation time 194198383 ps
CPU time 11.91 seconds
Started Mar 17 02:15:05 PM PDT 24
Finished Mar 17 02:15:18 PM PDT 24
Peak memory 251708 kb
Host smart-72b1e8d0-1fa7-4867-9701-4451fa297267
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2402301480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.2402301480
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.3550283217
Short name T413
Test name
Test status
Simulation time 58817305656 ps
CPU time 381.35 seconds
Started Mar 17 02:14:58 PM PDT 24
Finished Mar 17 02:21:19 PM PDT 24
Peak memory 257048 kb
Host smart-84649acf-77b9-4b94-87f3-29d0ac6729fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35502
83217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.3550283217
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.800092547
Short name T407
Test name
Test status
Simulation time 1263216305 ps
CPU time 39.59 seconds
Started Mar 17 02:14:54 PM PDT 24
Finished Mar 17 02:15:34 PM PDT 24
Peak memory 255808 kb
Host smart-494ec748-bcd7-4688-8be3-43a4c120201d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80009
2547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.800092547
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.2295831252
Short name T541
Test name
Test status
Simulation time 142984850539 ps
CPU time 1258.84 seconds
Started Mar 17 02:14:56 PM PDT 24
Finished Mar 17 02:35:56 PM PDT 24
Peak memory 286292 kb
Host smart-51e09597-30df-4afe-8e8a-f08584794da6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295831252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.2295831252
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.473533508
Short name T665
Test name
Test status
Simulation time 43119559505 ps
CPU time 451.82 seconds
Started Mar 17 02:14:57 PM PDT 24
Finished Mar 17 02:22:29 PM PDT 24
Peak memory 248148 kb
Host smart-b84fc9fe-f6f4-4ce4-8dc7-a625e7311ab2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473533508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.473533508
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.1724327609
Short name T613
Test name
Test status
Simulation time 1297571973 ps
CPU time 39.57 seconds
Started Mar 17 02:15:02 PM PDT 24
Finished Mar 17 02:15:42 PM PDT 24
Peak memory 248844 kb
Host smart-b6855538-355e-4bbd-8229-e94b5c59043a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17243
27609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.1724327609
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.282078889
Short name T53
Test name
Test status
Simulation time 1043925384 ps
CPU time 22.75 seconds
Started Mar 17 02:14:55 PM PDT 24
Finished Mar 17 02:15:17 PM PDT 24
Peak memory 255916 kb
Host smart-70ce3a36-9db7-43d8-a8d2-1c27e534ca5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28207
8889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.282078889
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.2453231915
Short name T11
Test name
Test status
Simulation time 890463510 ps
CPU time 28.13 seconds
Started Mar 17 02:15:05 PM PDT 24
Finished Mar 17 02:15:33 PM PDT 24
Peak memory 273428 kb
Host smart-1a8d2cc7-4ed3-4fd4-a4d7-f0a02ca50d31
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2453231915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.2453231915
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.638161165
Short name T115
Test name
Test status
Simulation time 610206094 ps
CPU time 43.36 seconds
Started Mar 17 02:14:53 PM PDT 24
Finished Mar 17 02:15:37 PM PDT 24
Peak memory 255376 kb
Host smart-13beac3e-b710-4090-8b6a-9716fb99f7df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63816
1165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.638161165
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.539532498
Short name T212
Test name
Test status
Simulation time 728099940 ps
CPU time 14.1 seconds
Started Mar 17 02:14:57 PM PDT 24
Finished Mar 17 02:15:11 PM PDT 24
Peak memory 248868 kb
Host smart-0e3b59cb-0ae5-4d48-9236-85385acca9ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53953
2498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.539532498
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.3188966
Short name T60
Test name
Test status
Simulation time 30221644850 ps
CPU time 2064.05 seconds
Started Mar 17 02:14:56 PM PDT 24
Finished Mar 17 02:49:20 PM PDT 24
Peak memory 282744 kb
Host smart-8738dbec-08ab-46cb-af60-a2734bee18d8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handl
er_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handle
r_stress_all.3188966
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.832815741
Short name T555
Test name
Test status
Simulation time 25801364509 ps
CPU time 1176.44 seconds
Started Mar 17 02:18:28 PM PDT 24
Finished Mar 17 02:38:05 PM PDT 24
Peak memory 286624 kb
Host smart-8d5035dc-02bd-45a2-bdd1-31aa1f893277
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832815741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.832815741
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.229370442
Short name T512
Test name
Test status
Simulation time 3817608938 ps
CPU time 159.22 seconds
Started Mar 17 02:18:28 PM PDT 24
Finished Mar 17 02:21:07 PM PDT 24
Peak memory 257064 kb
Host smart-cde66ae6-b57f-4787-8f9a-42be97b96e22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22937
0442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.229370442
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.1400755227
Short name T470
Test name
Test status
Simulation time 225505146 ps
CPU time 7.74 seconds
Started Mar 17 02:18:26 PM PDT 24
Finished Mar 17 02:18:34 PM PDT 24
Peak memory 249428 kb
Host smart-30ccda49-6bd2-4c24-bb93-fcdb79ce31f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14007
55227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.1400755227
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.3515249856
Short name T571
Test name
Test status
Simulation time 9189843347 ps
CPU time 828.62 seconds
Started Mar 17 02:18:32 PM PDT 24
Finished Mar 17 02:32:20 PM PDT 24
Peak memory 265428 kb
Host smart-137ff18c-92d3-464b-9355-e82636d37f7e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515249856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.3515249856
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.3275015755
Short name T144
Test name
Test status
Simulation time 95081988786 ps
CPU time 1491.35 seconds
Started Mar 17 02:18:32 PM PDT 24
Finished Mar 17 02:43:23 PM PDT 24
Peak memory 273440 kb
Host smart-65142513-f614-491d-a674-16c7a35f9023
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275015755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.3275015755
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.2293252382
Short name T328
Test name
Test status
Simulation time 8512286180 ps
CPU time 168.4 seconds
Started Mar 17 02:18:31 PM PDT 24
Finished Mar 17 02:21:20 PM PDT 24
Peak memory 248220 kb
Host smart-c233ae5b-d310-4d88-9ee0-18c0bf119911
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293252382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.2293252382
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.1049015567
Short name T476
Test name
Test status
Simulation time 692078203 ps
CPU time 49.54 seconds
Started Mar 17 02:18:26 PM PDT 24
Finished Mar 17 02:19:16 PM PDT 24
Peak memory 257004 kb
Host smart-84e196df-2c71-44bf-9522-2f79fd1b4750
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10490
15567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.1049015567
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.2196889757
Short name T301
Test name
Test status
Simulation time 2422247824 ps
CPU time 10.25 seconds
Started Mar 17 02:18:27 PM PDT 24
Finished Mar 17 02:18:38 PM PDT 24
Peak memory 251248 kb
Host smart-62c2625f-5cb8-4bec-9b89-e4d14de79a92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21968
89757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.2196889757
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.3717247648
Short name T671
Test name
Test status
Simulation time 425328337 ps
CPU time 10.62 seconds
Started Mar 17 02:18:28 PM PDT 24
Finished Mar 17 02:18:39 PM PDT 24
Peak memory 254536 kb
Host smart-6295a40a-879a-4b3d-a568-266602cc8a10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37172
47648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.3717247648
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.3510010674
Short name T593
Test name
Test status
Simulation time 735285010 ps
CPU time 46.09 seconds
Started Mar 17 02:18:26 PM PDT 24
Finished Mar 17 02:19:12 PM PDT 24
Peak memory 248856 kb
Host smart-bd36bb75-fa07-456f-afeb-a501aa579bd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35100
10674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.3510010674
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.130789342
Short name T271
Test name
Test status
Simulation time 24895743294 ps
CPU time 487.21 seconds
Started Mar 17 02:18:38 PM PDT 24
Finished Mar 17 02:26:45 PM PDT 24
Peak memory 265340 kb
Host smart-c8c30b36-d1f2-43ec-87d6-377e41ca6ea5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130789342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_han
dler_stress_all.130789342
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.3824952248
Short name T71
Test name
Test status
Simulation time 12757272357 ps
CPU time 1165.59 seconds
Started Mar 17 02:18:44 PM PDT 24
Finished Mar 17 02:38:10 PM PDT 24
Peak memory 270532 kb
Host smart-27a595a9-5102-4888-82e7-463aee901e9e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824952248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.3824952248
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.2015080805
Short name T697
Test name
Test status
Simulation time 2325015526 ps
CPU time 126.7 seconds
Started Mar 17 02:18:42 PM PDT 24
Finished Mar 17 02:20:48 PM PDT 24
Peak memory 256784 kb
Host smart-2b564609-9399-4b15-b57c-523cf7588d0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20150
80805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.2015080805
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.494013035
Short name T249
Test name
Test status
Simulation time 2108180131 ps
CPU time 39.43 seconds
Started Mar 17 02:18:44 PM PDT 24
Finished Mar 17 02:19:24 PM PDT 24
Peak memory 255520 kb
Host smart-b58364d8-8bf8-4e53-bd5a-3d1b0d703bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49401
3035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.494013035
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.3201787935
Short name T646
Test name
Test status
Simulation time 7963580233 ps
CPU time 922.1 seconds
Started Mar 17 02:18:43 PM PDT 24
Finished Mar 17 02:34:05 PM PDT 24
Peak memory 267332 kb
Host smart-d67d1ad4-b370-478f-9c24-b024fab8b61f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201787935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.3201787935
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.2599284072
Short name T466
Test name
Test status
Simulation time 52201693588 ps
CPU time 1074.22 seconds
Started Mar 17 02:18:48 PM PDT 24
Finished Mar 17 02:36:42 PM PDT 24
Peak memory 271684 kb
Host smart-11856389-e870-4c64-a438-13d4931b91cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599284072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.2599284072
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.3050157389
Short name T121
Test name
Test status
Simulation time 25761718319 ps
CPU time 572.46 seconds
Started Mar 17 02:18:43 PM PDT 24
Finished Mar 17 02:28:16 PM PDT 24
Peak memory 247852 kb
Host smart-02a4ba68-176c-4cac-a0db-c6d73ae32dd8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050157389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.3050157389
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.3322475233
Short name T688
Test name
Test status
Simulation time 637992606 ps
CPU time 22.34 seconds
Started Mar 17 02:18:37 PM PDT 24
Finished Mar 17 02:18:59 PM PDT 24
Peak memory 254912 kb
Host smart-d7dd76a0-2ac6-4828-a708-a8b29bff0d92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33224
75233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.3322475233
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.4076876066
Short name T436
Test name
Test status
Simulation time 645085604 ps
CPU time 32.77 seconds
Started Mar 17 02:18:44 PM PDT 24
Finished Mar 17 02:19:16 PM PDT 24
Peak memory 255436 kb
Host smart-81b51e8d-ebda-43e2-9ecd-f03cf34b6d0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40768
76066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.4076876066
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.2970113910
Short name T1
Test name
Test status
Simulation time 226293076 ps
CPU time 14.9 seconds
Started Mar 17 02:18:43 PM PDT 24
Finished Mar 17 02:18:58 PM PDT 24
Peak memory 248824 kb
Host smart-05679b6e-5be8-4206-8ab4-360617713e5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29701
13910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.2970113910
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.439386019
Short name T490
Test name
Test status
Simulation time 660462798 ps
CPU time 45.19 seconds
Started Mar 17 02:18:38 PM PDT 24
Finished Mar 17 02:19:24 PM PDT 24
Peak memory 257072 kb
Host smart-1e9e2b6d-13b4-480c-a83a-4e002566fbb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43938
6019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.439386019
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.381072924
Short name T691
Test name
Test status
Simulation time 227234983164 ps
CPU time 2930.55 seconds
Started Mar 17 02:18:49 PM PDT 24
Finished Mar 17 03:07:40 PM PDT 24
Peak memory 300608 kb
Host smart-b83d530c-bf3f-4a0c-96b4-13643b41e597
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381072924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_han
dler_stress_all.381072924
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.1103547965
Short name T80
Test name
Test status
Simulation time 481304643859 ps
CPU time 1729.57 seconds
Started Mar 17 02:18:57 PM PDT 24
Finished Mar 17 02:47:47 PM PDT 24
Peak memory 273136 kb
Host smart-2886a69f-5d90-442e-8939-cedeab555b7c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103547965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.1103547965
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.668012907
Short name T591
Test name
Test status
Simulation time 1929164900 ps
CPU time 148.08 seconds
Started Mar 17 02:18:54 PM PDT 24
Finished Mar 17 02:21:23 PM PDT 24
Peak memory 250964 kb
Host smart-9feab701-45d7-46bc-b67c-3439115d76fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66801
2907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.668012907
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.1415951997
Short name T626
Test name
Test status
Simulation time 541926052 ps
CPU time 17.26 seconds
Started Mar 17 02:18:56 PM PDT 24
Finished Mar 17 02:19:13 PM PDT 24
Peak memory 255232 kb
Host smart-7316a1ff-e462-4016-a390-f4d25337035a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14159
51997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.1415951997
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.172569600
Short name T675
Test name
Test status
Simulation time 55204259023 ps
CPU time 1461.54 seconds
Started Mar 17 02:19:03 PM PDT 24
Finished Mar 17 02:43:25 PM PDT 24
Peak memory 285508 kb
Host smart-246160ce-5056-4e81-a589-604b0643e838
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172569600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.172569600
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.927258021
Short name T516
Test name
Test status
Simulation time 10340173036 ps
CPU time 984.56 seconds
Started Mar 17 02:19:04 PM PDT 24
Finished Mar 17 02:35:30 PM PDT 24
Peak memory 273040 kb
Host smart-95721931-9954-41d5-9537-968dc657a392
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927258021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.927258021
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.3010716205
Short name T680
Test name
Test status
Simulation time 7346144830 ps
CPU time 263.55 seconds
Started Mar 17 02:19:05 PM PDT 24
Finished Mar 17 02:23:28 PM PDT 24
Peak memory 247816 kb
Host smart-9586635a-0d6f-4f5e-a266-439b07c54437
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010716205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.3010716205
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.2832646776
Short name T605
Test name
Test status
Simulation time 190525097 ps
CPU time 16.21 seconds
Started Mar 17 02:18:51 PM PDT 24
Finished Mar 17 02:19:07 PM PDT 24
Peak memory 254000 kb
Host smart-4d04fbca-4305-43a3-af8c-f9135fa6d3fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28326
46776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.2832646776
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.97525258
Short name T118
Test name
Test status
Simulation time 2850681064 ps
CPU time 30.65 seconds
Started Mar 17 02:18:54 PM PDT 24
Finished Mar 17 02:19:25 PM PDT 24
Peak memory 255400 kb
Host smart-dc211d1f-3c74-435e-aaac-965b6ded8c12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97525
258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.97525258
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.782124366
Short name T577
Test name
Test status
Simulation time 240000681 ps
CPU time 23.33 seconds
Started Mar 17 02:18:48 PM PDT 24
Finished Mar 17 02:19:12 PM PDT 24
Peak memory 248816 kb
Host smart-c62e78e9-e773-47a6-a654-7796e1d6e8f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78212
4366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.782124366
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.163975041
Short name T82
Test name
Test status
Simulation time 33375175344 ps
CPU time 1600.8 seconds
Started Mar 17 02:19:04 PM PDT 24
Finished Mar 17 02:45:45 PM PDT 24
Peak memory 298304 kb
Host smart-3088b87d-9335-4acc-b1d2-eff2db758217
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163975041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_han
dler_stress_all.163975041
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.3195218313
Short name T587
Test name
Test status
Simulation time 73607063468 ps
CPU time 849.99 seconds
Started Mar 17 02:19:11 PM PDT 24
Finished Mar 17 02:33:21 PM PDT 24
Peak memory 273440 kb
Host smart-527dab82-ba28-4063-aa16-eb1e53ab871c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195218313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.3195218313
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.3672654128
Short name T384
Test name
Test status
Simulation time 12933465133 ps
CPU time 158.54 seconds
Started Mar 17 02:19:12 PM PDT 24
Finished Mar 17 02:21:51 PM PDT 24
Peak memory 256632 kb
Host smart-c036ffd6-dfc9-4ade-9e32-11731cf59372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36726
54128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.3672654128
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.444765725
Short name T633
Test name
Test status
Simulation time 1088517511 ps
CPU time 28.99 seconds
Started Mar 17 02:19:11 PM PDT 24
Finished Mar 17 02:19:40 PM PDT 24
Peak memory 247516 kb
Host smart-3c010d53-099a-4351-b2cd-027f259b1252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44476
5725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.444765725
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.76134051
Short name T349
Test name
Test status
Simulation time 166795661681 ps
CPU time 2457.76 seconds
Started Mar 17 02:19:11 PM PDT 24
Finished Mar 17 03:00:09 PM PDT 24
Peak memory 289252 kb
Host smart-ff85f33b-9471-4589-a78c-82eedd45808e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76134051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.76134051
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.802215535
Short name T590
Test name
Test status
Simulation time 32524957169 ps
CPU time 1708.21 seconds
Started Mar 17 02:19:11 PM PDT 24
Finished Mar 17 02:47:39 PM PDT 24
Peak memory 289344 kb
Host smart-22b7fbce-8aff-4a6e-826a-a5ee10b75179
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802215535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.802215535
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.666367016
Short name T309
Test name
Test status
Simulation time 234970886 ps
CPU time 5.43 seconds
Started Mar 17 02:19:05 PM PDT 24
Finished Mar 17 02:19:11 PM PDT 24
Peak memory 240696 kb
Host smart-6788c507-7412-4ce6-969c-0e2cb88f5ce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66636
7016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.666367016
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.4171475450
Short name T622
Test name
Test status
Simulation time 5264517426 ps
CPU time 62.89 seconds
Started Mar 17 02:19:06 PM PDT 24
Finished Mar 17 02:20:09 PM PDT 24
Peak memory 256036 kb
Host smart-b1a4a947-6fe2-4f54-9f4c-68b6e39042ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41714
75450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.4171475450
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.1297612759
Short name T576
Test name
Test status
Simulation time 643358609 ps
CPU time 14.44 seconds
Started Mar 17 02:19:08 PM PDT 24
Finished Mar 17 02:19:23 PM PDT 24
Peak memory 248824 kb
Host smart-3f66f820-8708-45e9-ba69-92f96ae1b9ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12976
12759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.1297612759
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.3478750667
Short name T589
Test name
Test status
Simulation time 74842340253 ps
CPU time 1053.31 seconds
Started Mar 17 02:19:15 PM PDT 24
Finished Mar 17 02:36:48 PM PDT 24
Peak memory 265320 kb
Host smart-1d995693-1528-444c-b75d-da406de77f05
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478750667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.3478750667
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.1853269966
Short name T29
Test name
Test status
Simulation time 21097015724 ps
CPU time 1364.55 seconds
Started Mar 17 02:19:11 PM PDT 24
Finished Mar 17 02:41:56 PM PDT 24
Peak memory 273572 kb
Host smart-38d3b6ed-39e6-447e-802e-47cd423ce04a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853269966 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.1853269966
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.200516387
Short name T304
Test name
Test status
Simulation time 17053500178 ps
CPU time 1423.21 seconds
Started Mar 17 02:19:16 PM PDT 24
Finished Mar 17 02:43:00 PM PDT 24
Peak memory 289376 kb
Host smart-e8c645c2-0f46-4ad5-923e-c15a209d3fb4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200516387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.200516387
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.3664279175
Short name T2
Test name
Test status
Simulation time 270092380 ps
CPU time 8.12 seconds
Started Mar 17 02:19:17 PM PDT 24
Finished Mar 17 02:19:25 PM PDT 24
Peak memory 254088 kb
Host smart-c6dd983a-f7c3-4f29-b1a5-4d96e5e860e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36642
79175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.3664279175
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.3900170313
Short name T631
Test name
Test status
Simulation time 391806925 ps
CPU time 9.57 seconds
Started Mar 17 02:19:19 PM PDT 24
Finished Mar 17 02:19:29 PM PDT 24
Peak memory 251432 kb
Host smart-db23da38-bd69-4deb-88e5-a619117a16a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39001
70313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.3900170313
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.3924811927
Short name T361
Test name
Test status
Simulation time 12438959825 ps
CPU time 1387.75 seconds
Started Mar 17 02:19:23 PM PDT 24
Finished Mar 17 02:42:31 PM PDT 24
Peak memory 289140 kb
Host smart-9af39cf4-1fe0-4966-91ca-49d91338920a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924811927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.3924811927
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.3779582750
Short name T292
Test name
Test status
Simulation time 56291454821 ps
CPU time 1197.82 seconds
Started Mar 17 02:19:24 PM PDT 24
Finished Mar 17 02:39:22 PM PDT 24
Peak memory 287188 kb
Host smart-afb41855-b076-4a2e-91e2-d7a0ad1ec141
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779582750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.3779582750
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.1429319466
Short name T618
Test name
Test status
Simulation time 5518123809 ps
CPU time 66.74 seconds
Started Mar 17 02:19:26 PM PDT 24
Finished Mar 17 02:20:33 PM PDT 24
Peak memory 247776 kb
Host smart-9b84c541-ef7a-4af2-959e-50bf71f572bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429319466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.1429319466
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.1252539021
Short name T424
Test name
Test status
Simulation time 260345948 ps
CPU time 29.69 seconds
Started Mar 17 02:19:15 PM PDT 24
Finished Mar 17 02:19:45 PM PDT 24
Peak memory 255264 kb
Host smart-36fe0ccb-5a44-463c-abe5-79a6f1cd536c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12525
39021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.1252539021
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.3609056134
Short name T105
Test name
Test status
Simulation time 901707075 ps
CPU time 26.31 seconds
Started Mar 17 02:19:16 PM PDT 24
Finished Mar 17 02:19:43 PM PDT 24
Peak memory 247360 kb
Host smart-d7c9858a-204c-4218-a757-71668bb420ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36090
56134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.3609056134
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.1119572150
Short name T482
Test name
Test status
Simulation time 3572849038 ps
CPU time 64.44 seconds
Started Mar 17 02:19:18 PM PDT 24
Finished Mar 17 02:20:23 PM PDT 24
Peak memory 247736 kb
Host smart-6ec9b992-baa3-4ac3-bd36-3694df4e1a87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11195
72150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.1119572150
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.492148418
Short name T446
Test name
Test status
Simulation time 443333273 ps
CPU time 7.33 seconds
Started Mar 17 02:19:10 PM PDT 24
Finished Mar 17 02:19:18 PM PDT 24
Peak memory 248884 kb
Host smart-e98c0f17-c9e9-44c9-9b4a-25d34ed4d430
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49214
8418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.492148418
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.3403726060
Short name T547
Test name
Test status
Simulation time 8695270504 ps
CPU time 185.01 seconds
Started Mar 17 02:19:23 PM PDT 24
Finished Mar 17 02:22:28 PM PDT 24
Peak memory 257112 kb
Host smart-5a087c34-db0d-4eb7-9128-21b1a9ac40fa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403726060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.3403726060
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.2597009417
Short name T497
Test name
Test status
Simulation time 124580517527 ps
CPU time 2298.21 seconds
Started Mar 17 02:19:38 PM PDT 24
Finished Mar 17 02:57:57 PM PDT 24
Peak memory 286988 kb
Host smart-73297aaf-0b5e-4644-ac97-cb06f1861018
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597009417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.2597009417
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.960467846
Short name T457
Test name
Test status
Simulation time 2470768316 ps
CPU time 37.19 seconds
Started Mar 17 02:19:40 PM PDT 24
Finished Mar 17 02:20:17 PM PDT 24
Peak memory 256040 kb
Host smart-e894b872-d74a-4b5a-b134-a5612c8d34d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96046
7846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.960467846
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.1197266726
Short name T20
Test name
Test status
Simulation time 1041167721 ps
CPU time 20.37 seconds
Started Mar 17 02:19:38 PM PDT 24
Finished Mar 17 02:19:58 PM PDT 24
Peak memory 249284 kb
Host smart-46a4c67e-1cd6-4c05-8d73-8ada65337042
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11972
66726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.1197266726
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.2354973423
Short name T693
Test name
Test status
Simulation time 117252507444 ps
CPU time 3420.66 seconds
Started Mar 17 02:19:47 PM PDT 24
Finished Mar 17 03:16:48 PM PDT 24
Peak memory 287980 kb
Host smart-b38b5f2b-70dd-42fa-bfa8-5500b28d1a19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354973423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.2354973423
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.2624170620
Short name T408
Test name
Test status
Simulation time 58130285550 ps
CPU time 833.93 seconds
Started Mar 17 02:19:45 PM PDT 24
Finished Mar 17 02:33:39 PM PDT 24
Peak memory 273404 kb
Host smart-bc8b3ebc-6049-4d67-b491-4bee67ee634f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624170620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.2624170620
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.2810909838
Short name T335
Test name
Test status
Simulation time 27704959871 ps
CPU time 311.86 seconds
Started Mar 17 02:19:46 PM PDT 24
Finished Mar 17 02:24:58 PM PDT 24
Peak memory 247836 kb
Host smart-d0d3e2c4-17d7-46f7-8ea7-da5096951d58
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810909838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.2810909838
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.2451791647
Short name T430
Test name
Test status
Simulation time 338531445 ps
CPU time 11.13 seconds
Started Mar 17 02:19:31 PM PDT 24
Finished Mar 17 02:19:43 PM PDT 24
Peak memory 248776 kb
Host smart-877f4a91-4338-4bec-89a5-27688d76ec9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24517
91647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.2451791647
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.191475478
Short name T410
Test name
Test status
Simulation time 1061740520 ps
CPU time 12.94 seconds
Started Mar 17 02:19:30 PM PDT 24
Finished Mar 17 02:19:43 PM PDT 24
Peak memory 249240 kb
Host smart-6f5bc477-2b23-4ff2-be28-7baa798f4fda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19147
5478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.191475478
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.2823180751
Short name T276
Test name
Test status
Simulation time 1188987477 ps
CPU time 19.32 seconds
Started Mar 17 02:19:36 PM PDT 24
Finished Mar 17 02:19:55 PM PDT 24
Peak memory 254480 kb
Host smart-1a07360f-062d-451c-9b14-9b62db2c00bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28231
80751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.2823180751
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.2890629343
Short name T615
Test name
Test status
Simulation time 141195389 ps
CPU time 9.91 seconds
Started Mar 17 02:19:33 PM PDT 24
Finished Mar 17 02:19:43 PM PDT 24
Peak memory 250984 kb
Host smart-e8e9d4f8-32b4-4a5b-a85f-b5d6fb165df2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28906
29343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.2890629343
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.2793983697
Short name T111
Test name
Test status
Simulation time 394200804520 ps
CPU time 2139.48 seconds
Started Mar 17 02:19:47 PM PDT 24
Finished Mar 17 02:55:27 PM PDT 24
Peak memory 281656 kb
Host smart-cc950564-5150-45d1-a1b3-fb97c1ced17d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793983697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.2793983697
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.828941618
Short name T611
Test name
Test status
Simulation time 82242207911 ps
CPU time 1927.39 seconds
Started Mar 17 02:19:49 PM PDT 24
Finished Mar 17 02:51:57 PM PDT 24
Peak memory 288828 kb
Host smart-d476b523-73d7-4be5-91f1-3e499d0fe0c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828941618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.828941618
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.2109397664
Short name T142
Test name
Test status
Simulation time 25393409911 ps
CPU time 126.59 seconds
Started Mar 17 02:19:49 PM PDT 24
Finished Mar 17 02:21:56 PM PDT 24
Peak memory 256592 kb
Host smart-2320fe96-5405-4324-b44c-fa69303c1cef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21093
97664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.2109397664
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.3569501931
Short name T461
Test name
Test status
Simulation time 325714681 ps
CPU time 22.35 seconds
Started Mar 17 02:19:49 PM PDT 24
Finished Mar 17 02:20:11 PM PDT 24
Peak memory 254860 kb
Host smart-1b506b05-a1c0-456f-8eb3-17807f423139
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35695
01931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.3569501931
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.1548776545
Short name T16
Test name
Test status
Simulation time 35626646968 ps
CPU time 2202.98 seconds
Started Mar 17 02:19:49 PM PDT 24
Finished Mar 17 02:56:32 PM PDT 24
Peak memory 273460 kb
Host smart-27765035-686b-4d31-bb0e-813e02d0c1ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548776545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.1548776545
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.4258241704
Short name T401
Test name
Test status
Simulation time 1784678868 ps
CPU time 27.96 seconds
Started Mar 17 02:19:50 PM PDT 24
Finished Mar 17 02:20:18 PM PDT 24
Peak memory 256048 kb
Host smart-e0383fa0-959e-48bc-9054-2d72a0fcfb5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42582
41704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.4258241704
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.983153233
Short name T415
Test name
Test status
Simulation time 294427307 ps
CPU time 33.9 seconds
Started Mar 17 02:19:50 PM PDT 24
Finished Mar 17 02:20:24 PM PDT 24
Peak memory 247644 kb
Host smart-750ac880-cbb1-45ef-8bca-c1aac9fa3ba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98315
3233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.983153233
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.894216714
Short name T400
Test name
Test status
Simulation time 197889760 ps
CPU time 18.34 seconds
Started Mar 17 02:19:44 PM PDT 24
Finished Mar 17 02:20:03 PM PDT 24
Peak memory 248824 kb
Host smart-101a488e-c313-4c00-8ef5-77fffa84c866
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89421
6714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.894216714
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.974813168
Short name T392
Test name
Test status
Simulation time 7769547092 ps
CPU time 535.94 seconds
Started Mar 17 02:19:51 PM PDT 24
Finished Mar 17 02:28:47 PM PDT 24
Peak memory 257080 kb
Host smart-145c8b6f-4603-4e96-af3b-d0db93076ad7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974813168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_han
dler_stress_all.974813168
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.61942167
Short name T607
Test name
Test status
Simulation time 195435503963 ps
CPU time 2960.71 seconds
Started Mar 17 02:19:55 PM PDT 24
Finished Mar 17 03:09:16 PM PDT 24
Peak memory 281824 kb
Host smart-72b60eb2-c2f0-4b97-bd23-c9719d69e3bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61942167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.61942167
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.1657821522
Short name T505
Test name
Test status
Simulation time 1063312035 ps
CPU time 64.83 seconds
Started Mar 17 02:19:56 PM PDT 24
Finished Mar 17 02:21:01 PM PDT 24
Peak memory 256536 kb
Host smart-61aa464f-a4f9-4105-ac4e-cf5e2e679df3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16578
21522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.1657821522
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.3733095304
Short name T594
Test name
Test status
Simulation time 129569759 ps
CPU time 8.34 seconds
Started Mar 17 02:19:53 PM PDT 24
Finished Mar 17 02:20:01 PM PDT 24
Peak memory 249828 kb
Host smart-363ce8fa-54a5-454f-992f-ac2470fe17be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37330
95304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.3733095304
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.1751048532
Short name T319
Test name
Test status
Simulation time 196640831002 ps
CPU time 3064.51 seconds
Started Mar 17 02:19:59 PM PDT 24
Finished Mar 17 03:11:04 PM PDT 24
Peak memory 289152 kb
Host smart-912ac75c-fdeb-4597-b912-2d8a620bcc50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751048532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.1751048532
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.3711338693
Short name T469
Test name
Test status
Simulation time 29554565740 ps
CPU time 1438.46 seconds
Started Mar 17 02:20:00 PM PDT 24
Finished Mar 17 02:43:59 PM PDT 24
Peak memory 289400 kb
Host smart-4abb7fd3-7be2-4051-8bf9-ae938ed1b76d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711338693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3711338693
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.2255199239
Short name T344
Test name
Test status
Simulation time 87194859738 ps
CPU time 513.02 seconds
Started Mar 17 02:19:59 PM PDT 24
Finished Mar 17 02:28:32 PM PDT 24
Peak memory 248076 kb
Host smart-21b85324-86ea-4202-96e3-6ad7319219cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255199239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.2255199239
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.3607028735
Short name T703
Test name
Test status
Simulation time 903407693 ps
CPU time 27.16 seconds
Started Mar 17 02:19:49 PM PDT 24
Finished Mar 17 02:20:16 PM PDT 24
Peak memory 248880 kb
Host smart-52fc3251-02a0-4d38-8be5-72dd2b3dfc1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36070
28735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.3607028735
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.391429339
Short name T120
Test name
Test status
Simulation time 1265719482 ps
CPU time 40.32 seconds
Started Mar 17 02:19:54 PM PDT 24
Finished Mar 17 02:20:35 PM PDT 24
Peak memory 255884 kb
Host smart-f180f9f3-d566-49cb-8ad7-f3e51fffba06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39142
9339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.391429339
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.2784631528
Short name T509
Test name
Test status
Simulation time 457216473 ps
CPU time 9.62 seconds
Started Mar 17 02:19:53 PM PDT 24
Finished Mar 17 02:20:02 PM PDT 24
Peak memory 255688 kb
Host smart-ba3b465b-0863-4c24-ae76-619f94eed777
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27846
31528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.2784631528
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.4182581202
Short name T647
Test name
Test status
Simulation time 257828520 ps
CPU time 4.85 seconds
Started Mar 17 02:19:51 PM PDT 24
Finished Mar 17 02:19:56 PM PDT 24
Peak memory 240660 kb
Host smart-17472510-29e0-4250-bdbf-3093e7472ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41825
81202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.4182581202
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.3300766357
Short name T414
Test name
Test status
Simulation time 3621759636 ps
CPU time 247.65 seconds
Started Mar 17 02:19:59 PM PDT 24
Finished Mar 17 02:24:07 PM PDT 24
Peak memory 257112 kb
Host smart-c2056a98-0faa-4e0c-b4c9-575689e27b5d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300766357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.3300766357
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.1908086166
Short name T572
Test name
Test status
Simulation time 144950029930 ps
CPU time 2153.9 seconds
Started Mar 17 02:20:16 PM PDT 24
Finished Mar 17 02:56:10 PM PDT 24
Peak memory 273448 kb
Host smart-c270c32d-59c2-4d1c-ae43-00ce38c4ff87
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908086166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.1908086166
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.2060408738
Short name T523
Test name
Test status
Simulation time 2200630473 ps
CPU time 122.36 seconds
Started Mar 17 02:20:12 PM PDT 24
Finished Mar 17 02:22:15 PM PDT 24
Peak memory 248956 kb
Host smart-5ce672a0-9b1f-43ab-81c6-9bbb1bf66ef6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20604
08738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.2060408738
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.2029301667
Short name T434
Test name
Test status
Simulation time 98100275 ps
CPU time 15.07 seconds
Started Mar 17 02:20:13 PM PDT 24
Finished Mar 17 02:20:28 PM PDT 24
Peak memory 248696 kb
Host smart-b0d6bf24-28e2-4648-ab13-d95d1bceb483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20293
01667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.2029301667
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.2894149333
Short name T674
Test name
Test status
Simulation time 33119161814 ps
CPU time 2246.73 seconds
Started Mar 17 02:20:19 PM PDT 24
Finished Mar 17 02:57:46 PM PDT 24
Peak memory 287740 kb
Host smart-252fdcfb-ca74-4b06-ad4a-9de864d7935f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894149333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.2894149333
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2699779341
Short name T437
Test name
Test status
Simulation time 15819258647 ps
CPU time 1556.18 seconds
Started Mar 17 02:20:17 PM PDT 24
Finished Mar 17 02:46:14 PM PDT 24
Peak memory 289300 kb
Host smart-9203fff3-5454-4548-9732-09ded2f0d7ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699779341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2699779341
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.3119029526
Short name T327
Test name
Test status
Simulation time 7448964994 ps
CPU time 285.21 seconds
Started Mar 17 02:20:18 PM PDT 24
Finished Mar 17 02:25:04 PM PDT 24
Peak memory 247780 kb
Host smart-6f2ee645-d125-40c4-86f8-676d734cf44b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119029526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.3119029526
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.1233713331
Short name T520
Test name
Test status
Simulation time 356919508 ps
CPU time 23.21 seconds
Started Mar 17 02:20:05 PM PDT 24
Finished Mar 17 02:20:28 PM PDT 24
Peak memory 248832 kb
Host smart-58f2a233-6fee-4fdd-a2b0-ac34890a80aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12337
13331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.1233713331
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.1641141369
Short name T77
Test name
Test status
Simulation time 834207097 ps
CPU time 62.28 seconds
Started Mar 17 02:20:05 PM PDT 24
Finished Mar 17 02:21:07 PM PDT 24
Peak memory 256028 kb
Host smart-966e8a4a-d18a-4555-8625-2ff68b3523d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16411
41369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.1641141369
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.3224571566
Short name T502
Test name
Test status
Simulation time 161257675 ps
CPU time 11.65 seconds
Started Mar 17 02:20:17 PM PDT 24
Finished Mar 17 02:20:30 PM PDT 24
Peak memory 249188 kb
Host smart-0c041e98-1e8f-4c3e-88b8-1a59cf3e489b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32245
71566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.3224571566
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.3789856072
Short name T649
Test name
Test status
Simulation time 199390924 ps
CPU time 28.1 seconds
Started Mar 17 02:20:05 PM PDT 24
Finished Mar 17 02:20:34 PM PDT 24
Peak memory 256068 kb
Host smart-eb5758db-a70f-4f1b-8dc3-683f1227f73a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37898
56072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.3789856072
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.1007332421
Short name T660
Test name
Test status
Simulation time 66223339634 ps
CPU time 1169.23 seconds
Started Mar 17 02:20:18 PM PDT 24
Finished Mar 17 02:39:48 PM PDT 24
Peak memory 273144 kb
Host smart-559cbd1b-79bc-4649-b96b-00a40aa6070a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007332421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.1007332421
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.155898000
Short name T124
Test name
Test status
Simulation time 11036736103 ps
CPU time 1276.38 seconds
Started Mar 17 02:20:18 PM PDT 24
Finished Mar 17 02:41:35 PM PDT 24
Peak memory 281712 kb
Host smart-8d0de5d8-244e-47fc-9751-4b9b88cb2223
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155898000 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.155898000
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.3977298224
Short name T673
Test name
Test status
Simulation time 12322913484 ps
CPU time 172.14 seconds
Started Mar 17 02:20:30 PM PDT 24
Finished Mar 17 02:23:22 PM PDT 24
Peak memory 249912 kb
Host smart-6b807a2c-fe9a-47f0-934a-9fc092d3ed9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39772
98224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.3977298224
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.4283869552
Short name T86
Test name
Test status
Simulation time 509239530 ps
CPU time 33.38 seconds
Started Mar 17 02:20:29 PM PDT 24
Finished Mar 17 02:21:03 PM PDT 24
Peak memory 248744 kb
Host smart-5f846d56-cb8f-419e-a307-a00661a9b3db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42838
69552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.4283869552
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.1847377299
Short name T336
Test name
Test status
Simulation time 50232169394 ps
CPU time 1704.11 seconds
Started Mar 17 02:20:35 PM PDT 24
Finished Mar 17 02:48:59 PM PDT 24
Peak memory 273464 kb
Host smart-ed433c01-2e2e-474e-bd73-e1d32cd84132
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847377299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.1847377299
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.3238411101
Short name T538
Test name
Test status
Simulation time 85144469759 ps
CPU time 1661.97 seconds
Started Mar 17 02:20:36 PM PDT 24
Finished Mar 17 02:48:18 PM PDT 24
Peak memory 273520 kb
Host smart-d915d91a-260c-4266-adcb-04d290450db2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238411101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.3238411101
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.1604783096
Short name T337
Test name
Test status
Simulation time 7944733929 ps
CPU time 100.36 seconds
Started Mar 17 02:20:29 PM PDT 24
Finished Mar 17 02:22:10 PM PDT 24
Peak memory 248064 kb
Host smart-0a3e26fa-f97f-491f-9318-cf1d1266ab86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604783096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.1604783096
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.2687264031
Short name T683
Test name
Test status
Simulation time 693451177 ps
CPU time 12.48 seconds
Started Mar 17 02:20:29 PM PDT 24
Finished Mar 17 02:20:41 PM PDT 24
Peak memory 255688 kb
Host smart-fa45b3b7-b15c-4d19-a9e2-dc2df1c0d9bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26872
64031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.2687264031
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.2862628323
Short name T544
Test name
Test status
Simulation time 2332996014 ps
CPU time 38.47 seconds
Started Mar 17 02:20:24 PM PDT 24
Finished Mar 17 02:21:03 PM PDT 24
Peak memory 256252 kb
Host smart-589195e6-5811-4bb9-aab0-2014e527f9f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28626
28323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.2862628323
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.3546280113
Short name T669
Test name
Test status
Simulation time 1029862811 ps
CPU time 34.98 seconds
Started Mar 17 02:20:28 PM PDT 24
Finished Mar 17 02:21:03 PM PDT 24
Peak memory 249336 kb
Host smart-462b76cc-4ca9-4624-9bdd-55791043db1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35462
80113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.3546280113
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.177251676
Short name T439
Test name
Test status
Simulation time 4466662721 ps
CPU time 81.68 seconds
Started Mar 17 02:20:24 PM PDT 24
Finished Mar 17 02:21:46 PM PDT 24
Peak memory 249128 kb
Host smart-3f5f5dca-f931-4ce7-8682-331f04ec36f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17725
1676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.177251676
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.1036085007
Short name T58
Test name
Test status
Simulation time 10562972376 ps
CPU time 1382.9 seconds
Started Mar 17 02:20:35 PM PDT 24
Finished Mar 17 02:43:38 PM PDT 24
Peak memory 289844 kb
Host smart-b37db8ca-709a-48c5-b7d4-a198e48a1d3f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036085007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.1036085007
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.234813117
Short name T208
Test name
Test status
Simulation time 19800672970 ps
CPU time 2188.54 seconds
Started Mar 17 02:20:34 PM PDT 24
Finished Mar 17 02:57:03 PM PDT 24
Peak memory 305696 kb
Host smart-af6ddf9f-be9e-41b0-9acf-4b8e72a7d9e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234813117 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.234813117
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.4011078376
Short name T236
Test name
Test status
Simulation time 33113705 ps
CPU time 3.69 seconds
Started Mar 17 02:14:55 PM PDT 24
Finished Mar 17 02:14:59 PM PDT 24
Peak memory 249008 kb
Host smart-9fd4346b-cd6b-4419-9acd-e4d90ba24c9b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4011078376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.4011078376
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.4196010900
Short name T63
Test name
Test status
Simulation time 19807865498 ps
CPU time 1287.59 seconds
Started Mar 17 02:15:05 PM PDT 24
Finished Mar 17 02:36:34 PM PDT 24
Peak memory 273496 kb
Host smart-4aec56af-88a9-4eaa-864a-693dd5cfdfb3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196010900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.4196010900
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.2442179006
Short name T471
Test name
Test status
Simulation time 950256178 ps
CPU time 12.07 seconds
Started Mar 17 02:14:56 PM PDT 24
Finished Mar 17 02:15:08 PM PDT 24
Peak memory 240616 kb
Host smart-f0e056d5-7d42-4e2a-9dbd-a3b14f597439
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2442179006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.2442179006
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.3500842534
Short name T449
Test name
Test status
Simulation time 3053421131 ps
CPU time 175.22 seconds
Started Mar 17 02:14:56 PM PDT 24
Finished Mar 17 02:17:51 PM PDT 24
Peak memory 256760 kb
Host smart-5945d9ce-523e-441b-b3d0-3a1bb78d1ef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35008
42534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3500842534
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.464408328
Short name T81
Test name
Test status
Simulation time 629417431 ps
CPU time 15.87 seconds
Started Mar 17 02:14:53 PM PDT 24
Finished Mar 17 02:15:09 PM PDT 24
Peak memory 254616 kb
Host smart-d4aaf555-caa6-4873-a74b-73708ddcf2f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46440
8328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.464408328
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.2676383019
Short name T46
Test name
Test status
Simulation time 53958693325 ps
CPU time 1084.18 seconds
Started Mar 17 02:15:05 PM PDT 24
Finished Mar 17 02:33:10 PM PDT 24
Peak memory 273532 kb
Host smart-3b8e3256-ae92-4808-91d7-7cc8b68dd04a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676383019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2676383019
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.2880539852
Short name T220
Test name
Test status
Simulation time 104532278244 ps
CPU time 1717.09 seconds
Started Mar 17 02:14:56 PM PDT 24
Finished Mar 17 02:43:33 PM PDT 24
Peak memory 269368 kb
Host smart-d13a5399-516b-4bd6-9948-ea5f1a30b68c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880539852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.2880539852
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.2080024820
Short name T545
Test name
Test status
Simulation time 41474111469 ps
CPU time 473.43 seconds
Started Mar 17 02:14:55 PM PDT 24
Finished Mar 17 02:22:48 PM PDT 24
Peak memory 247828 kb
Host smart-868b9005-73f3-47a1-a77b-2641d9eb6260
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080024820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.2080024820
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.3703478279
Short name T508
Test name
Test status
Simulation time 420246920 ps
CPU time 30.21 seconds
Started Mar 17 02:14:56 PM PDT 24
Finished Mar 17 02:15:26 PM PDT 24
Peak memory 256016 kb
Host smart-c43c3a45-da33-451d-a641-3639b58ce7d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37034
78279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3703478279
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.1341587669
Short name T511
Test name
Test status
Simulation time 887963547 ps
CPU time 24.48 seconds
Started Mar 17 02:14:55 PM PDT 24
Finished Mar 17 02:15:19 PM PDT 24
Peak memory 247364 kb
Host smart-076e9da8-2e0a-44f3-82d7-2731eaac32a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13415
87669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.1341587669
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.1790969368
Short name T295
Test name
Test status
Simulation time 899907719 ps
CPU time 51.14 seconds
Started Mar 17 02:15:00 PM PDT 24
Finished Mar 17 02:15:51 PM PDT 24
Peak memory 255852 kb
Host smart-ef684edc-3b05-40b5-a1d8-43b427fd9aa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17909
69368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.1790969368
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.98765409
Short name T525
Test name
Test status
Simulation time 32131311 ps
CPU time 5.17 seconds
Started Mar 17 02:15:02 PM PDT 24
Finished Mar 17 02:15:08 PM PDT 24
Peak memory 248840 kb
Host smart-321e4fc5-91b0-4759-aa8e-73e78ff1c976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98765
409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.98765409
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.583579575
Short name T122
Test name
Test status
Simulation time 264350555033 ps
CPU time 4084.1 seconds
Started Mar 17 02:14:55 PM PDT 24
Finished Mar 17 03:22:59 PM PDT 24
Peak memory 305688 kb
Host smart-652552e2-9248-47c8-8dd1-48f1bb312bcc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583579575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_hand
ler_stress_all.583579575
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.2011751513
Short name T695
Test name
Test status
Simulation time 84317633243 ps
CPU time 2274.7 seconds
Started Mar 17 02:14:55 PM PDT 24
Finished Mar 17 02:52:50 PM PDT 24
Peak memory 300784 kb
Host smart-3bacfe41-fc17-49e6-86ca-05aede14b062
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011751513 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.2011751513
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.3027123680
Short name T248
Test name
Test status
Simulation time 137021324 ps
CPU time 4 seconds
Started Mar 17 02:15:02 PM PDT 24
Finished Mar 17 02:15:07 PM PDT 24
Peak memory 249072 kb
Host smart-2a196bd6-0738-4313-b436-a2f1b70dc056
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3027123680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.3027123680
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.261958532
Short name T55
Test name
Test status
Simulation time 88213075762 ps
CPU time 2195.89 seconds
Started Mar 17 02:15:01 PM PDT 24
Finished Mar 17 02:51:37 PM PDT 24
Peak memory 281768 kb
Host smart-7da7e866-0da3-42fb-afa7-13f9fa624513
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261958532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.261958532
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.3146114246
Short name T368
Test name
Test status
Simulation time 331794478 ps
CPU time 10.14 seconds
Started Mar 17 02:15:02 PM PDT 24
Finished Mar 17 02:15:12 PM PDT 24
Peak memory 240676 kb
Host smart-8c2aa8bd-9e67-417b-94ac-bacd267ba2fd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3146114246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.3146114246
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.44579916
Short name T549
Test name
Test status
Simulation time 4229568469 ps
CPU time 244.01 seconds
Started Mar 17 02:15:02 PM PDT 24
Finished Mar 17 02:19:07 PM PDT 24
Peak memory 256596 kb
Host smart-365b8938-f8a0-45d5-b9a1-55f24d73733a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44579
916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.44579916
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.2301914872
Short name T412
Test name
Test status
Simulation time 444789713 ps
CPU time 8.47 seconds
Started Mar 17 02:15:00 PM PDT 24
Finished Mar 17 02:15:08 PM PDT 24
Peak memory 248832 kb
Host smart-7929b408-f39e-430e-835a-9a399be7962e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23019
14872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.2301914872
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.97290511
Short name T475
Test name
Test status
Simulation time 19454517997 ps
CPU time 911.15 seconds
Started Mar 17 02:15:04 PM PDT 24
Finished Mar 17 02:30:16 PM PDT 24
Peak memory 265308 kb
Host smart-4ee3d6b8-4e50-4686-bdb2-c04ffa4ef344
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97290511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.97290511
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.1335586354
Short name T448
Test name
Test status
Simulation time 111726440131 ps
CPU time 739.47 seconds
Started Mar 17 02:15:01 PM PDT 24
Finished Mar 17 02:27:21 PM PDT 24
Peak memory 272716 kb
Host smart-5244e3ff-fdb2-4c83-8d3d-367cbb6f0da2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335586354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.1335586354
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.2560800910
Short name T116
Test name
Test status
Simulation time 62439630922 ps
CPU time 507.58 seconds
Started Mar 17 02:15:02 PM PDT 24
Finished Mar 17 02:23:30 PM PDT 24
Peak memory 248100 kb
Host smart-c27e4e76-eb4d-46ed-b42c-83158420939f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560800910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.2560800910
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.1819885414
Short name T447
Test name
Test status
Simulation time 248518654 ps
CPU time 16.37 seconds
Started Mar 17 02:15:01 PM PDT 24
Finished Mar 17 02:15:18 PM PDT 24
Peak memory 248872 kb
Host smart-471839f5-2c65-455b-bbe7-de1702386379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18198
85414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.1819885414
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.1720520487
Short name T26
Test name
Test status
Simulation time 1063110323 ps
CPU time 18.34 seconds
Started Mar 17 02:14:56 PM PDT 24
Finished Mar 17 02:15:15 PM PDT 24
Peak memory 248816 kb
Host smart-fcc80813-f5f5-4948-8684-11784a88e17c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17205
20487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1720520487
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.2290738307
Short name T681
Test name
Test status
Simulation time 819127673 ps
CPU time 52.34 seconds
Started Mar 17 02:15:01 PM PDT 24
Finished Mar 17 02:15:53 PM PDT 24
Peak memory 255964 kb
Host smart-6f64bc24-d7de-4a44-bb7c-1d913afba822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22907
38307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.2290738307
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.1267663494
Short name T383
Test name
Test status
Simulation time 391946540 ps
CPU time 32.31 seconds
Started Mar 17 02:15:00 PM PDT 24
Finished Mar 17 02:15:32 PM PDT 24
Peak memory 248840 kb
Host smart-95f0e2df-0bf3-432a-a163-664757b9ca8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12676
63494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.1267663494
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.1610278682
Short name T209
Test name
Test status
Simulation time 62165375487 ps
CPU time 5501.81 seconds
Started Mar 17 02:15:01 PM PDT 24
Finished Mar 17 03:46:44 PM PDT 24
Peak memory 298156 kb
Host smart-6b00574c-c1dc-4661-8004-a1456833cf81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610278682 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.1610278682
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.2647918564
Short name T237
Test name
Test status
Simulation time 46329986 ps
CPU time 4.03 seconds
Started Mar 17 02:15:01 PM PDT 24
Finished Mar 17 02:15:05 PM PDT 24
Peak memory 249068 kb
Host smart-95a7a001-f8d4-4dd8-92b0-d91395819dcf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2647918564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.2647918564
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.470451380
Short name T278
Test name
Test status
Simulation time 40660204809 ps
CPU time 2515.15 seconds
Started Mar 17 02:15:02 PM PDT 24
Finished Mar 17 02:56:57 PM PDT 24
Peak memory 285888 kb
Host smart-688356a6-1613-4165-a320-9b6f687e51ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470451380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.470451380
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.3515822263
Short name T429
Test name
Test status
Simulation time 2332624549 ps
CPU time 48.99 seconds
Started Mar 17 02:15:01 PM PDT 24
Finished Mar 17 02:15:51 PM PDT 24
Peak memory 240760 kb
Host smart-963d472a-0ec3-4a11-98b2-8bbd2453018d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3515822263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.3515822263
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.2140070023
Short name T455
Test name
Test status
Simulation time 1713163592 ps
CPU time 33.98 seconds
Started Mar 17 02:15:02 PM PDT 24
Finished Mar 17 02:15:37 PM PDT 24
Peak memory 255548 kb
Host smart-8bd98cd1-b620-44af-8a48-9d2281eb88fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21400
70023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.2140070023
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.1815601947
Short name T459
Test name
Test status
Simulation time 542145215 ps
CPU time 32.74 seconds
Started Mar 17 02:15:02 PM PDT 24
Finished Mar 17 02:15:36 PM PDT 24
Peak memory 255300 kb
Host smart-3f01fdca-3ddf-4e55-a3bd-54f924a693e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18156
01947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.1815601947
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.1221119827
Short name T359
Test name
Test status
Simulation time 24396142600 ps
CPU time 1660.1 seconds
Started Mar 17 02:15:01 PM PDT 24
Finished Mar 17 02:42:42 PM PDT 24
Peak memory 273196 kb
Host smart-afe90b42-1192-4655-bbc7-4a7c4f612b63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221119827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.1221119827
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.1013039555
Short name T569
Test name
Test status
Simulation time 32902293079 ps
CPU time 1148.01 seconds
Started Mar 17 02:15:01 PM PDT 24
Finished Mar 17 02:34:09 PM PDT 24
Peak memory 273320 kb
Host smart-8844c4b6-5e47-4d7f-bc58-d1d24d5093a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013039555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.1013039555
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.1962003172
Short name T629
Test name
Test status
Simulation time 2886394258 ps
CPU time 122.16 seconds
Started Mar 17 02:15:01 PM PDT 24
Finished Mar 17 02:17:04 PM PDT 24
Peak memory 248100 kb
Host smart-c529337c-7a94-43eb-8b44-82e9f87caea5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962003172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.1962003172
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.3918285375
Short name T426
Test name
Test status
Simulation time 298427248 ps
CPU time 7.9 seconds
Started Mar 17 02:15:01 PM PDT 24
Finished Mar 17 02:15:10 PM PDT 24
Peak memory 252388 kb
Host smart-9864d467-6926-403e-9b8e-eeb36f582605
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39182
85375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3918285375
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.1958179551
Short name T585
Test name
Test status
Simulation time 630959106 ps
CPU time 45.12 seconds
Started Mar 17 02:15:03 PM PDT 24
Finished Mar 17 02:15:49 PM PDT 24
Peak memory 255488 kb
Host smart-7d7b2bb5-e742-49fd-b0d8-f396909554b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19581
79551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.1958179551
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.2645185731
Short name T74
Test name
Test status
Simulation time 109856272 ps
CPU time 13.06 seconds
Started Mar 17 02:15:02 PM PDT 24
Finished Mar 17 02:15:15 PM PDT 24
Peak memory 255652 kb
Host smart-e679ff73-5eff-4a17-a0df-3919f2319cb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26451
85731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.2645185731
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.869820978
Short name T119
Test name
Test status
Simulation time 3462387530 ps
CPU time 55.68 seconds
Started Mar 17 02:15:01 PM PDT 24
Finished Mar 17 02:15:57 PM PDT 24
Peak memory 248860 kb
Host smart-bd455cf0-d29b-4279-b1e1-ec42e673a5aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86982
0978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.869820978
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.2833769863
Short name T245
Test name
Test status
Simulation time 154275861 ps
CPU time 3.3 seconds
Started Mar 17 02:15:06 PM PDT 24
Finished Mar 17 02:15:10 PM PDT 24
Peak memory 249104 kb
Host smart-0343b3ca-07b8-456b-b6e3-9e526a364fdf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2833769863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.2833769863
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.2673920382
Short name T102
Test name
Test status
Simulation time 100188423768 ps
CPU time 2756.44 seconds
Started Mar 17 02:15:07 PM PDT 24
Finished Mar 17 03:01:04 PM PDT 24
Peak memory 281660 kb
Host smart-f276aff7-163b-4db5-8396-fae9998043c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673920382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.2673920382
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.141394138
Short name T419
Test name
Test status
Simulation time 5118781492 ps
CPU time 57.36 seconds
Started Mar 17 02:15:06 PM PDT 24
Finished Mar 17 02:16:03 PM PDT 24
Peak memory 240644 kb
Host smart-38910033-4a05-4900-a281-d0dc788faea3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=141394138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.141394138
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.2079813790
Short name T454
Test name
Test status
Simulation time 2336872504 ps
CPU time 141.2 seconds
Started Mar 17 02:15:08 PM PDT 24
Finished Mar 17 02:17:30 PM PDT 24
Peak memory 257032 kb
Host smart-60ac641a-70b4-4fae-8ed5-99f87889b424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20798
13790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.2079813790
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.2701602339
Short name T423
Test name
Test status
Simulation time 868111272 ps
CPU time 31.24 seconds
Started Mar 17 02:15:09 PM PDT 24
Finished Mar 17 02:15:40 PM PDT 24
Peak memory 255392 kb
Host smart-45d6833d-b437-4c30-bbc4-a816e57a7ef3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27016
02339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.2701602339
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.928547939
Short name T638
Test name
Test status
Simulation time 10820765544 ps
CPU time 62.57 seconds
Started Mar 17 02:15:07 PM PDT 24
Finished Mar 17 02:16:10 PM PDT 24
Peak memory 256024 kb
Host smart-ea1026f3-b283-4ef3-91dc-fd5cf87c5a40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92854
7939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.928547939
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.793954500
Short name T546
Test name
Test status
Simulation time 724006293 ps
CPU time 33.66 seconds
Started Mar 17 02:15:04 PM PDT 24
Finished Mar 17 02:15:39 PM PDT 24
Peak memory 255896 kb
Host smart-2f1b7272-05c4-4d33-b040-ada6159b3372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79395
4500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.793954500
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.885672711
Short name T499
Test name
Test status
Simulation time 148293635 ps
CPU time 10.09 seconds
Started Mar 17 02:15:07 PM PDT 24
Finished Mar 17 02:15:17 PM PDT 24
Peak memory 247596 kb
Host smart-3f839a3b-1af1-43b4-89b0-5a01ce1a9503
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88567
2711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.885672711
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.3764394951
Short name T701
Test name
Test status
Simulation time 1952799196 ps
CPU time 48.16 seconds
Started Mar 17 02:15:07 PM PDT 24
Finished Mar 17 02:15:56 PM PDT 24
Peak memory 249028 kb
Host smart-e0093803-11c0-4450-9f2a-8b1ba267ee86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37643
94951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.3764394951
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.3668404433
Short name T272
Test name
Test status
Simulation time 12781398719 ps
CPU time 1233.28 seconds
Started Mar 17 02:15:08 PM PDT 24
Finished Mar 17 02:35:42 PM PDT 24
Peak memory 281728 kb
Host smart-d933e44d-7680-4ac6-97fc-b49a728b0af2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668404433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.3668404433
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.593218169
Short name T244
Test name
Test status
Simulation time 109425804 ps
CPU time 4.26 seconds
Started Mar 17 02:15:14 PM PDT 24
Finished Mar 17 02:15:18 PM PDT 24
Peak memory 249116 kb
Host smart-f740e221-06f6-4ac2-bcfc-bcad12b558db
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=593218169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.593218169
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.1966906554
Short name T75
Test name
Test status
Simulation time 37600259371 ps
CPU time 2167.23 seconds
Started Mar 17 02:15:07 PM PDT 24
Finished Mar 17 02:51:14 PM PDT 24
Peak memory 273412 kb
Host smart-5b7c15bb-137f-46e0-a68b-b74c887d49bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966906554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.1966906554
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.2266783944
Short name T13
Test name
Test status
Simulation time 1933850820 ps
CPU time 17.4 seconds
Started Mar 17 02:15:17 PM PDT 24
Finished Mar 17 02:15:35 PM PDT 24
Peak memory 240676 kb
Host smart-2984f9d9-0fc6-447d-b7b0-64ff380b22d0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2266783944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.2266783944
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.3288144246
Short name T223
Test name
Test status
Simulation time 1811179824 ps
CPU time 90 seconds
Started Mar 17 02:15:05 PM PDT 24
Finished Mar 17 02:16:35 PM PDT 24
Peak memory 256648 kb
Host smart-b2f2cd39-e11b-4099-92b7-9a9c20df0a9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32881
44246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.3288144246
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.502541342
Short name T567
Test name
Test status
Simulation time 4553946958 ps
CPU time 66.76 seconds
Started Mar 17 02:15:08 PM PDT 24
Finished Mar 17 02:16:14 PM PDT 24
Peak memory 255788 kb
Host smart-afb06089-3f4f-4af2-b10b-79102ebd88c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50254
1342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.502541342
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.622352557
Short name T352
Test name
Test status
Simulation time 35676305734 ps
CPU time 1579.78 seconds
Started Mar 17 02:15:09 PM PDT 24
Finished Mar 17 02:41:29 PM PDT 24
Peak memory 265260 kb
Host smart-bcb2590e-2c21-4ebb-9a9d-f44bc4885f63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622352557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.622352557
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.4236138393
Short name T598
Test name
Test status
Simulation time 28192192315 ps
CPU time 653.38 seconds
Started Mar 17 02:15:09 PM PDT 24
Finished Mar 17 02:26:02 PM PDT 24
Peak memory 272876 kb
Host smart-3f06cb3e-becd-42de-bc14-0c8e3702c229
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236138393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.4236138393
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.606782875
Short name T99
Test name
Test status
Simulation time 6652355376 ps
CPU time 257.35 seconds
Started Mar 17 02:15:09 PM PDT 24
Finished Mar 17 02:19:26 PM PDT 24
Peak memory 248912 kb
Host smart-e3c99d77-c20a-4ed4-af6b-3907ce3ad214
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606782875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.606782875
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.261490986
Short name T403
Test name
Test status
Simulation time 857065858 ps
CPU time 27.3 seconds
Started Mar 17 02:15:08 PM PDT 24
Finished Mar 17 02:15:36 PM PDT 24
Peak memory 248888 kb
Host smart-e4eea764-985f-4461-b498-e8d76c1c3464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26149
0986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.261490986
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.157731249
Short name T486
Test name
Test status
Simulation time 372448732 ps
CPU time 26.59 seconds
Started Mar 17 02:15:07 PM PDT 24
Finished Mar 17 02:15:34 PM PDT 24
Peak memory 255340 kb
Host smart-27a198f6-415d-4822-a354-6459d3471d29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15773
1249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.157731249
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.1270784745
Short name T431
Test name
Test status
Simulation time 1036771312 ps
CPU time 21.48 seconds
Started Mar 17 02:15:06 PM PDT 24
Finished Mar 17 02:15:28 PM PDT 24
Peak memory 255544 kb
Host smart-41eb1ff4-6e69-4ff3-bc81-5f404f470a14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12707
84745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.1270784745
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.3222320902
Short name T668
Test name
Test status
Simulation time 1132072189 ps
CPU time 16.94 seconds
Started Mar 17 02:15:08 PM PDT 24
Finished Mar 17 02:15:25 PM PDT 24
Peak memory 248760 kb
Host smart-91c513a7-0672-495b-bbe5-44b643df454b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32223
20902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.3222320902
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.2851972609
Short name T515
Test name
Test status
Simulation time 11854116744 ps
CPU time 594.5 seconds
Started Mar 17 02:15:14 PM PDT 24
Finished Mar 17 02:25:09 PM PDT 24
Peak memory 265264 kb
Host smart-42c1cb45-bf65-4f6d-8212-ead3ab725f20
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851972609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.2851972609
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.828556882
Short name T273
Test name
Test status
Simulation time 53134875863 ps
CPU time 1833.82 seconds
Started Mar 17 02:15:13 PM PDT 24
Finished Mar 17 02:45:48 PM PDT 24
Peak memory 299276 kb
Host smart-d5aee058-36b7-434b-9dc7-e6441bde9da7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828556882 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.828556882
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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