Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	75215	1			T5	3425		T15	1310		T24	4902
class_i[0x1]	74119	1			T4	15		T5	15		T9	24
class_i[0x2]	38438	1			T1	1		T4	10		T5	9
class_i[0x3]	42421	1			T1	4		T4	21		T5	14

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	56763	1			T1	2		T4	14		T5	858
alert[0x1]	57399	1			T4	6		T5	839		T9	11
alert[0x2]	57260	1			T1	1		T4	10		T5	931
alert[0x3]	58771	1			T1	2		T4	16		T5	835

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

229926

1

T4

46

T5

3463

T9

24

esc_ping_fail

267

1

T1

5

T9

11

T10

3

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	56685	1			T4	14		T5	858		T9	10
esc_integrity_fail	alert[0x1]	57329	1			T4	6		T5	839		T9	8
esc_integrity_fail	alert[0x2]	57196	1			T4	10		T5	931		T9	3
esc_integrity_fail	alert[0x3]	58716	1			T4	16		T5	835		T9	3
esc_ping_fail	alert[0x0]	78	1			T1	2		T9	5		T10	3
esc_ping_fail	alert[0x1]	70	1			T9	3		T302	2		T204	3
esc_ping_fail	alert[0x2]	64	1			T1	1		T9	2		T204	1
esc_ping_fail	alert[0x3]	55	1			T1	2		T9	1		T302	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	75131	1			T5	3425		T15	1310		T24	4902
esc_integrity_fail	class_i[0x1]	74070	1			T4	15		T5	15		T9	24
esc_integrity_fail	class_i[0x2]	38359	1			T4	10		T5	9		T15	16
esc_integrity_fail	class_i[0x3]	42366	1			T4	21		T5	14		T15	41
esc_ping_fail	class_i[0x0]	84	1			T204	1		T280	1		T194	2
esc_ping_fail	class_i[0x1]	49	1			T302	1		T204	8		T280	2
esc_ping_fail	class_i[0x2]	79	1			T1	1		T9	10		T302	1
esc_ping_fail	class_i[0x3]	55	1			T1	4		T9	1		T10	3