Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	2	38	95.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	2	38	95.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	75	1			T16	2		T24	2		T63	1
class_index[0x1]	51	1			T15	1		T20	1		T16	1
class_index[0x2]	72	1			T19	4		T15	2		T62	1
class_index[0x3]	68	1			T15	2		T55	1		T62	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	100	1			T15	5		T55	1		T62	1
intr_timeout_cnt[1]	58	1			T19	4		T20	1		T24	2
intr_timeout_cnt[2]	30	1			T55	1		T62	1		T24	1
intr_timeout_cnt[3]	14	1			T59	1		T41	1		T248	1
intr_timeout_cnt[4]	15	1			T16	1		T24	1		T52	1
intr_timeout_cnt[5]	16	1			T16	1		T63	1		T64	1
intr_timeout_cnt[6]	8	1			T63	1		T108	1		T51	1
intr_timeout_cnt[7]	11	1			T108	1		T72	1		T175	4
intr_timeout_cnt[8]	11	1			T16	1		T249	1		T250	1
intr_timeout_cnt[9]	3	1			T102	1		T251	1		T252	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	2	38	95.00	2

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x1]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[6]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	30	1			T24	1		T43	5		T69	1
class_index[0x0]	intr_timeout_cnt[1]	17	1			T63	1		T49	1		T174	1
class_index[0x0]	intr_timeout_cnt[2]	5	1			T24	1		T67	1		T253	1
class_index[0x0]	intr_timeout_cnt[3]	3	1			T254	1		T255	1		T80	1
class_index[0x0]	intr_timeout_cnt[4]	5	1			T52	1		T198	1		T256	1
class_index[0x0]	intr_timeout_cnt[5]	5	1			T16	1		T103	1		T257	1
class_index[0x0]	intr_timeout_cnt[6]	1	1			T51	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[7]	5	1			T72	1		T175	3		T258	1
class_index[0x0]	intr_timeout_cnt[8]	3	1			T16	1		T252	2		-	-
class_index[0x0]	intr_timeout_cnt[9]	1	1			T251	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	17	1			T15	1		T55	1		T70	2
class_index[0x1]	intr_timeout_cnt[1]	13	1			T20	1		T24	1		T41	2
class_index[0x1]	intr_timeout_cnt[2]	5	1			T68	1		T52	1		T53	1
class_index[0x1]	intr_timeout_cnt[3]	2	1			T41	1		T103	1		-	-
class_index[0x1]	intr_timeout_cnt[4]	3	1			T16	1		T259	1		T260	1
class_index[0x1]	intr_timeout_cnt[5]	3	1			T261	1		T240	1		T259	1
class_index[0x1]	intr_timeout_cnt[6]	2	1			T63	1		T261	1		-	-
class_index[0x1]	intr_timeout_cnt[7]	2	1			T104	1		T262	1		-	-
class_index[0x1]	intr_timeout_cnt[8]	4	1			T249	1		T98	1		T263	1
class_index[0x2]	intr_timeout_cnt[0]	30	1			T15	2		T82	1		T96	1
class_index[0x2]	intr_timeout_cnt[1]	17	1			T19	4		T24	1		T95	1
class_index[0x2]	intr_timeout_cnt[2]	7	1			T62	1		T59	1		T61	1
class_index[0x2]	intr_timeout_cnt[3]	3	1			T256	1		T264	2		-	-
class_index[0x2]	intr_timeout_cnt[4]	6	1			T24	1		T174	1		T261	1
class_index[0x2]	intr_timeout_cnt[5]	4	1			T64	1		T72	1		T98	1
class_index[0x2]	intr_timeout_cnt[7]	1	1			T108	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[8]	3	1			T250	1		T254	1		T264	1
class_index[0x2]	intr_timeout_cnt[9]	1	1			T102	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	23	1			T15	2		T62	1		T24	1
class_index[0x3]	intr_timeout_cnt[1]	11	1			T42	1		T263	1		T86	2
class_index[0x3]	intr_timeout_cnt[2]	13	1			T55	1		T63	1		T109	1
class_index[0x3]	intr_timeout_cnt[3]	6	1			T59	1		T248	1		T97	3
class_index[0x3]	intr_timeout_cnt[4]	1	1			T265	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[5]	4	1			T63	1		T49	1		T175	1
class_index[0x3]	intr_timeout_cnt[6]	5	1			T108	1		T88	3		T266	1
class_index[0x3]	intr_timeout_cnt[7]	3	1			T175	1		T104	1		T267	1
class_index[0x3]	intr_timeout_cnt[8]	1	1			T98	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	1	1			T252	1		-	-		-	-