Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	357722	1			T1	29		T2	31		T3	23
all_values[1]	357722	1			T1	29		T2	31		T3	23
all_values[2]	357722	1			T1	29		T2	31		T3	23
all_values[3]	357722	1			T1	29		T2	31		T3	23

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

711463

1

T2

60

T3

39

T17

18

auto[1]

719425

1

T1

116

T2

64

T3

53

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

844695

1

T1

102

T2

109

T3

48

auto[1]

586193

1

T1

14

T2

15

T3

44

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	100354	1			T2	7		T3	8		T17	1
all_values[0]	auto[0]	auto[1]	77340	1			T2	6		T3	7		T17	1
all_values[0]	auto[1]	auto[0]	102189	1			T1	29		T2	9		T3	4
all_values[0]	auto[1]	auto[1]	77839	1			T2	9		T3	4		T17	2
all_values[1]	auto[0]	auto[0]	107121	1			T2	16		T3	3		T17	4
all_values[1]	auto[0]	auto[1]	70860	1			T3	3		T4	312		T5	340
all_values[1]	auto[1]	auto[0]	108707	1			T1	21		T2	15		T3	9
all_values[1]	auto[1]	auto[1]	71034	1			T1	8		T3	8		T4	318
all_values[2]	auto[0]	auto[0]	104917	1			T2	17		T3	3		T17	5
all_values[2]	auto[0]	auto[1]	72817	1			T3	3		T4	327		T5	320
all_values[2]	auto[1]	auto[0]	106645	1			T1	28		T2	14		T3	9
all_values[2]	auto[1]	auto[1]	73343	1			T1	1		T3	8		T4	308
all_values[3]	auto[0]	auto[0]	106709	1			T2	14		T3	6		T17	7
all_values[3]	auto[0]	auto[1]	71345	1			T3	6		T4	323		T5	333
all_values[3]	auto[1]	auto[0]	108053	1			T1	24		T2	17		T3	6
all_values[3]	auto[1]	auto[1]	71615	1			T1	5		T3	5		T4	293