Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	357722	1			T1	29		T2	31		T3	23
all_pins[1]	357722	1			T1	29		T2	31		T3	23
all_pins[2]	357722	1			T1	29		T2	31		T3	23
all_pins[3]	357722	1			T1	29		T2	31		T3	23

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1137057	1			T1	102		T2	115		T3	67
values[0x1]	293831	1			T1	14		T2	9		T3	25
transitions[0x0=>0x1]	194656	1			T1	14		T2	8		T3	14
transitions[0x1=>0x0]	194905	1			T1	14		T2	9		T3	14

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	279883	1			T1	29		T2	22		T3	19
all_pins[0]	values[0x1]	77839	1			T2	9		T3	4		T17	2
all_pins[0]	transitions[0x0=>0x1]	77166	1			T2	8		T3	4		T17	2
all_pins[0]	transitions[0x1=>0x0]	71191	1			T1	5		T3	5		T4	293
all_pins[1]	values[0x0]	286688	1			T1	21		T2	31		T3	15
all_pins[1]	values[0x1]	71034	1			T1	8		T3	8		T4	318
all_pins[1]	transitions[0x0=>0x1]	37992	1			T1	8		T3	6		T4	153
all_pins[1]	transitions[0x1=>0x0]	44797	1			T2	9		T3	2		T17	2
all_pins[2]	values[0x0]	284379	1			T1	28		T2	31		T3	15
all_pins[2]	values[0x1]	73343	1			T1	1		T3	8		T4	308
all_pins[2]	transitions[0x0=>0x1]	40701	1			T1	1		T3	2		T4	154
all_pins[2]	transitions[0x1=>0x0]	38392	1			T1	8		T3	2		T4	164
all_pins[3]	values[0x0]	286107	1			T1	24		T2	31		T3	18
all_pins[3]	values[0x1]	71615	1			T1	5		T3	5		T4	293
all_pins[3]	transitions[0x0=>0x1]	38797	1			T1	5		T3	2		T4	155
all_pins[3]	transitions[0x1=>0x0]	40525	1			T1	1		T3	5		T4	170