Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	281	1			T152	4		T153	4		T154	7
all_values[1]	281	1			T152	4		T153	4		T154	7
all_values[2]	281	1			T152	4		T153	4		T154	7
all_values[3]	281	1			T152	4		T153	4		T154	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

633

1

T152

9

T153

10

T154

10

auto[1]

491

1

T152

7

T153

6

T154

18

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

449

1

T152

5

T153

8

T154

6

auto[1]

675

1

T152

11

T153

8

T154

22

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

656

1

T152

9

T153

10

T154

11

auto[1]

468

1

T152

7

T153

6

T154

17

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

71

1

T152

2

T153

4

T154

1

all_values[0]

auto[0]

auto[0]

auto[1]

28

1

T152

1

T154

1

T341

1

all_values[0]

auto[0]

auto[1]

auto[0]

46

1

T239

4

T342

2

T343

1

all_values[0]

auto[0]

auto[1]

auto[1]

27

1

T154

2

T239

1

T344

1

all_values[0]

auto[1]

auto[0]

auto[1]

69

1

T152

1

T342

2

T343

1

all_values[0]

auto[1]

auto[1]

auto[1]

40

1

T154

3

T239

1

T344

1

all_values[1]

auto[0]

auto[0]

auto[0]

74

1

T153

1

T154

1

T239

3

all_values[1]

auto[0]

auto[0]

auto[1]

24

1

T343

1

T345

1

T346

2

all_values[1]

auto[0]

auto[1]

auto[0]

42

1

T342

1

T343

1

T347

2

all_values[1]

auto[0]

auto[1]

auto[1]

27

1

T152

1

T153

1

T154

1

all_values[1]

auto[1]

auto[0]

auto[1]

53

1

T152

1

T154

4

T239

2

all_values[1]

auto[1]

auto[1]

auto[1]

61

1

T152

2

T153

2

T154

1

all_values[2]

auto[0]

auto[0]

auto[0]

77

1

T152

2

T153

2

T239

1

all_values[2]

auto[0]

auto[0]

auto[1]

21

1

T347

1

T346

1

T348

1

all_values[2]

auto[0]

auto[1]

auto[0]

46

1

T152

1

T153

1

T154

3

all_values[2]

auto[0]

auto[1]

auto[1]

20

1

T341

1

T346

1

T349

1

all_values[2]

auto[1]

auto[0]

auto[1]

72

1

T152

1

T153

1

T239

4

all_values[2]

auto[1]

auto[1]

auto[1]

45

1

T154

4

T239

1

T342

1

all_values[3]

auto[0]

auto[0]

auto[0]

40

1

T154

1

T239

2

T343

2

all_values[3]

auto[0]

auto[0]

auto[1]

30

1

T153

1

T154

1

T341

1

all_values[3]

auto[0]

auto[1]

auto[0]

53

1

T239

2

T343

5

T344

2

all_values[3]

auto[0]

auto[1]

auto[1]

30

1

T152

2

T342

2

T347

1

all_values[3]

auto[1]

auto[0]

auto[1]

74

1

T152

1

T153

1

T154

1

all_values[3]

auto[1]

auto[1]

auto[1]

54

1

T152

1

T153

2

T154

4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal