Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	96610	1			T4	281		T5	891		T7	1049
accum_cnt_1000	241950	1			T4	566		T5	1003		T6	508
accum_cnt_100	29810	1			T2	8		T4	37		T5	1067
accum_cnt_50	58594	1			T2	9		T3	29		T4	27
accum_cnt_10	181289	1			T1	28		T2	2		T3	30
accum_cnt_0	387061	1			T1	68		T2	57		T3	9

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	263222	1			T1	24		T2	19		T3	17
class_index[0x1]	263222	1			T1	24		T2	19		T3	17
class_index[0x2]	263222	1			T1	24		T2	19		T3	17
class_index[0x3]	263222	1			T1	24		T2	19		T3	17

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	25340	1			T7	482		T32	514		T62	149
class_index[0x0]	accum_cnt_1000	66858	1			T7	578		T15	1		T16	74
class_index[0x0]	accum_cnt_100	7833	1			T2	8		T7	28		T15	16
class_index[0x0]	accum_cnt_50	17410	1			T2	9		T3	10		T7	22
class_index[0x0]	accum_cnt_10	38053	1			T2	2		T3	6		T17	3
class_index[0x0]	accum_cnt_0	91206	1			T1	24		T3	1		T17	1
class_index[0x1]	accum_cnt_2000	25825	1			T4	281		T16	37		T111	546
class_index[0x1]	accum_cnt_1000	58798	1			T4	566		T6	508		T15	12
class_index[0x1]	accum_cnt_100	7949	1			T4	37		T5	1006		T6	66
class_index[0x1]	accum_cnt_50	12422	1			T4	27		T5	1		T6	67
class_index[0x1]	accum_cnt_10	47688	1			T3	13		T4	31		T5	2
class_index[0x1]	accum_cnt_0	93199	1			T1	24		T2	19		T3	4
class_index[0x2]	accum_cnt_2000	23602	1			T5	387		T62	84		T24	650
class_index[0x2]	accum_cnt_1000	57877	1			T5	557		T14	290		T15	26
class_index[0x2]	accum_cnt_100	6809	1			T5	35		T14	154		T15	9
class_index[0x2]	accum_cnt_50	14154	1			T3	9		T5	20		T14	122
class_index[0x2]	accum_cnt_10	43852	1			T1	4		T3	6		T5	8
class_index[0x2]	accum_cnt_0	105701	1			T1	20		T2	19		T3	2
class_index[0x3]	accum_cnt_2000	21843	1			T5	504		T7	567		T32	109
class_index[0x3]	accum_cnt_1000	58417	1			T5	446		T7	495		T16	516
class_index[0x3]	accum_cnt_100	7219	1			T5	26		T7	28		T15	26
class_index[0x3]	accum_cnt_50	14608	1			T3	10		T5	22		T7	16
class_index[0x3]	accum_cnt_10	51696	1			T1	24		T3	5		T4	2
class_index[0x3]	accum_cnt_0	96955	1			T2	19		T3	2		T17	4