Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	7950	1			T9	1		T32	116		T280	1
alert[0x1]	4574	1			T9	1		T16	8		T32	15
alert[0x2]	9599	1			T5	18		T16	4		T302	1
alert[0x3]	10113	1			T1	1		T5	25		T15	14
alert[0x4]	5786	1			T5	28		T9	1		T32	237
alert[0x5]	5261	1			T9	1		T24	21		T60	27
alert[0x6]	7682	1			T5	648		T9	1		T32	1805
alert[0x7]	2214	1			T16	1		T62	6		T204	2
alert[0x8]	6259	1			T6	1		T280	2		T93	36
alert[0x9]	9538	1			T9	1		T107	1		T204	1
alert[0xa]	5062	1			T5	2128		T9	1		T24	186
alert[0xb]	6274	1			T5	26		T15	19		T27	7
alert[0xc]	8821	1			T9	1		T32	573		T41	28
alert[0xd]	3799	1			T15	33		T24	913		T93	10
alert[0xe]	5228	1			T5	80		T32	133		T302	1
alert[0xf]	8175	1			T32	135		T59	1		T27	5
alert[0x10]	4747	1			T5	1		T15	1		T24	5
alert[0x11]	6119	1			T27	31		T41	7		T43	311
alert[0x12]	9497	1			T10	1		T59	19		T27	81
alert[0x13]	7289	1			T15	2		T16	1		T302	1
alert[0x14]	8061	1			T5	20		T9	1		T15	2
alert[0x15]	5828	1			T1	1		T15	25		T24	47
alert[0x16]	7288	1			T15	2		T16	7		T32	9
alert[0x17]	2383	1			T32	16		T24	38		T280	1
alert[0x18]	4513	1			T24	37		T280	1		T47	747
alert[0x19]	17998	1			T1	1		T15	1		T24	534
alert[0x1a]	2921	1			T9	1		T15	12		T24	1
alert[0x1b]	6928	1			T27	405		T41	128		T66	110
alert[0x1c]	6388	1			T1	1		T32	15		T41	830
alert[0x1d]	1878	1			T5	1		T24	1		T27	5
alert[0x1e]	6072	1			T5	25		T32	98		T24	115
alert[0x1f]	4269	1			T9	1		T27	135		T66	17
alert[0x20]	10688	1			T1	1		T5	27		T9	1
alert[0x21]	8897	1			T5	4		T204	1		T280	1
alert[0x22]	6987	1			T5	15		T9	1		T32	8
alert[0x23]	8840	1			T1	1		T5	1111		T32	127
alert[0x24]	12140	1			T24	1836		T27	939		T66	13
alert[0x25]	6229	1			T5	24		T15	11		T32	270
alert[0x26]	4057	1			T9	1		T16	7		T32	111
alert[0x27]	11593	1			T15	38		T24	3		T60	1
alert[0x28]	8660	1			T5	520		T15	8		T37	1
alert[0x29]	12714	1			T16	3		T32	26		T28	1
alert[0x2a]	16774	1			T204	3		T27	46		T43	251
alert[0x2b]	6365	1			T5	24		T32	131		T24	30
alert[0x2c]	16167	1			T1	1		T5	342		T32	3105
alert[0x2d]	5924	1			T4	1		T5	1064		T24	14
alert[0x2e]	5833	1			T32	35		T27	12		T41	240
alert[0x2f]	5553	1			T5	29		T15	4		T16	2
alert[0x30]	10379	1			T9	1		T24	838		T27	114
alert[0x31]	11472	1			T32	3103		T27	187		T41	1965
alert[0x32]	7323	1			T9	1		T24	5		T27	114
alert[0x33]	4895	1			T5	15		T32	88		T10	1
alert[0x34]	8130	1			T5	2		T9	1		T32	78
alert[0x35]	9404	1			T1	1		T16	3		T27	98
alert[0x36]	4556	1			T15	24		T32	235		T24	7
alert[0x37]	17846	1			T5	1		T32	6		T107	38
alert[0x38]	4710	1			T9	1		T15	2		T27	184
alert[0x39]	9836	1			T16	2		T32	2		T24	20
alert[0x3a]	4912	1			T15	3		T32	11		T62	4
alert[0x3b]	3227	1			T32	56		T302	1		T204	1
alert[0x3c]	14853	1			T1	1		T5	309		T32	32
alert[0x3d]	6164	1			T5	463		T24	8		T93	12
alert[0x3e]	7282	1			T5	173		T15	7		T107	1
alert[0x3f]	8024	1			T5	30		T15	7		T32	12
alert[0x40]	9990	1			T9	1		T24	8		T280	1

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	167397	1			T9	1		T16	14		T107	24
class_i[0x1]	144652	1			T1	8		T4	1		T5	7153
class_i[0x2]	109737	1			T15	86		T16	16		T62	10
class_i[0x3]	77152	1			T1	1		T6	1		T9	1

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

498274

1

T4

1

T5

7153

T15

215

alert_ping_fail

664

1

T1

9

T6

1

T9

19

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	7936	1			T32	116		T66	397		T45	2
alert_integrity_fail	alert[0x1]	4566	1			T16	8		T32	15		T24	5
alert_integrity_fail	alert[0x2]	9590	1			T5	18		T16	4		T63	2
alert_integrity_fail	alert[0x3]	10105	1			T5	25		T15	14		T32	33
alert_integrity_fail	alert[0x4]	5777	1			T5	28		T32	237		T24	23
alert_integrity_fail	alert[0x5]	5245	1			T24	21		T60	27		T27	195
alert_integrity_fail	alert[0x6]	7665	1			T5	648		T32	1805		T24	149
alert_integrity_fail	alert[0x7]	2196	1			T16	1		T62	6		T93	1
alert_integrity_fail	alert[0x8]	6241	1			T93	36		T27	262		T66	65
alert_integrity_fail	alert[0x9]	9527	1			T107	1		T28	12		T41	398
alert_integrity_fail	alert[0xa]	5050	1			T5	2128		T24	186		T60	36
alert_integrity_fail	alert[0xb]	6266	1			T5	26		T15	19		T27	7
alert_integrity_fail	alert[0xc]	8811	1			T32	573		T41	28		T66	243
alert_integrity_fail	alert[0xd]	3790	1			T15	33		T24	913		T93	10
alert_integrity_fail	alert[0xe]	5222	1			T5	80		T32	133		T60	18
alert_integrity_fail	alert[0xf]	8164	1			T32	135		T59	1		T27	5
alert_integrity_fail	alert[0x10]	4739	1			T5	1		T15	1		T24	5
alert_integrity_fail	alert[0x11]	6117	1			T27	31		T41	7		T43	311
alert_integrity_fail	alert[0x12]	9487	1			T59	19		T27	81		T41	36
alert_integrity_fail	alert[0x13]	7281	1			T15	2		T16	1		T27	438
alert_integrity_fail	alert[0x14]	8055	1			T5	20		T15	2		T24	130
alert_integrity_fail	alert[0x15]	5809	1			T15	25		T24	47		T41	36
alert_integrity_fail	alert[0x16]	7271	1			T15	2		T16	7		T32	9
alert_integrity_fail	alert[0x17]	2373	1			T32	16		T24	38		T27	10
alert_integrity_fail	alert[0x18]	4502	1			T24	37		T47	747		T273	326
alert_integrity_fail	alert[0x19]	17989	1			T15	1		T24	534		T27	26
alert_integrity_fail	alert[0x1a]	2914	1			T15	12		T24	1		T41	163
alert_integrity_fail	alert[0x1b]	6917	1			T27	405		T41	128		T66	110
alert_integrity_fail	alert[0x1c]	6381	1			T32	15		T41	830		T43	28
alert_integrity_fail	alert[0x1d]	1868	1			T5	1		T24	1		T27	5
alert_integrity_fail	alert[0x1e]	6062	1			T5	25		T32	98		T24	115
alert_integrity_fail	alert[0x1f]	4252	1			T27	135		T66	17		T43	1240
alert_integrity_fail	alert[0x20]	10677	1			T5	27		T32	166		T41	1831
alert_integrity_fail	alert[0x21]	8890	1			T5	4		T27	544		T66	3
alert_integrity_fail	alert[0x22]	6979	1			T5	15		T32	8		T107	1
alert_integrity_fail	alert[0x23]	8829	1			T5	1111		T32	127		T24	12
alert_integrity_fail	alert[0x24]	12129	1			T24	1836		T27	939		T66	13
alert_integrity_fail	alert[0x25]	6220	1			T5	24		T15	11		T32	270
alert_integrity_fail	alert[0x26]	4047	1			T16	7		T32	111		T27	48
alert_integrity_fail	alert[0x27]	11582	1			T15	38		T24	3		T60	1
alert_integrity_fail	alert[0x28]	8643	1			T5	520		T15	8		T59	1
alert_integrity_fail	alert[0x29]	12705	1			T16	3		T32	26		T28	1
alert_integrity_fail	alert[0x2a]	16760	1			T27	46		T43	251		T105	1
alert_integrity_fail	alert[0x2b]	6356	1			T5	24		T32	131		T24	30
alert_integrity_fail	alert[0x2c]	16159	1			T5	342		T32	3105		T24	5490
alert_integrity_fail	alert[0x2d]	5918	1			T4	1		T5	1064		T24	14
alert_integrity_fail	alert[0x2e]	5824	1			T32	35		T27	12		T41	240
alert_integrity_fail	alert[0x2f]	5543	1			T5	29		T15	4		T16	2
alert_integrity_fail	alert[0x30]	10367	1			T24	838		T27	114		T66	44
alert_integrity_fail	alert[0x31]	11461	1			T32	3103		T27	187		T41	1965
alert_integrity_fail	alert[0x32]	7314	1			T24	5		T27	114		T66	16
alert_integrity_fail	alert[0x33]	4884	1			T5	15		T32	88		T60	18
alert_integrity_fail	alert[0x34]	8120	1			T5	2		T32	78		T24	12
alert_integrity_fail	alert[0x35]	9390	1			T16	3		T27	98		T66	92
alert_integrity_fail	alert[0x36]	4548	1			T15	24		T32	235		T24	7
alert_integrity_fail	alert[0x37]	17841	1			T5	1		T32	6		T107	38
alert_integrity_fail	alert[0x38]	4706	1			T15	2		T27	184		T43	596
alert_integrity_fail	alert[0x39]	9825	1			T16	2		T32	2		T24	20
alert_integrity_fail	alert[0x3a]	4906	1			T15	3		T32	11		T62	4
alert_integrity_fail	alert[0x3b]	3216	1			T32	56		T60	15		T27	94
alert_integrity_fail	alert[0x3c]	14839	1			T5	309		T32	32		T27	12
alert_integrity_fail	alert[0x3d]	6152	1			T5	463		T24	8		T93	12
alert_integrity_fail	alert[0x3e]	7271	1			T5	173		T15	7		T107	1
alert_integrity_fail	alert[0x3f]	8021	1			T5	30		T15	7		T32	12
alert_integrity_fail	alert[0x40]	9984	1			T24	8		T93	2		T66	249
alert_ping_fail	alert[0x0]	14	1			T9	1		T280	1		T303	1
alert_ping_fail	alert[0x1]	8	1			T9	1		T10	1		T302	1
alert_ping_fail	alert[0x2]	9	1			T302	1		T245	1		T304	1
alert_ping_fail	alert[0x3]	8	1			T1	1		T244	1		T305	1
alert_ping_fail	alert[0x4]	9	1			T9	1		T280	1		T194	1
alert_ping_fail	alert[0x5]	16	1			T9	1		T90	1		T304	1
alert_ping_fail	alert[0x6]	17	1			T9	1		T37	1		T10	1
alert_ping_fail	alert[0x7]	18	1			T204	2		T280	2		T304	1
alert_ping_fail	alert[0x8]	18	1			T6	1		T280	2		T300	1
alert_ping_fail	alert[0x9]	11	1			T9	1		T204	1		T275	2
alert_ping_fail	alert[0xa]	12	1			T9	1		T280	1		T300	1
alert_ping_fail	alert[0xb]	8	1			T306	1		T307	1		T308	1
alert_ping_fail	alert[0xc]	10	1			T9	1		T242	1		T245	1
alert_ping_fail	alert[0xd]	9	1			T194	1		T304	1		T309	1
alert_ping_fail	alert[0xe]	6	1			T302	1		T304	1		T305	1
alert_ping_fail	alert[0xf]	11	1			T242	1		T245	1		T310	1
alert_ping_fail	alert[0x10]	8	1			T302	1		T311	1		T312	1
alert_ping_fail	alert[0x11]	2	1			T194	1		T242	1		-	-
alert_ping_fail	alert[0x12]	10	1			T10	1		T245	1		T305	1
alert_ping_fail	alert[0x13]	8	1			T302	1		T300	1		T305	1
alert_ping_fail	alert[0x14]	6	1			T9	1		T295	1		T313	1
alert_ping_fail	alert[0x15]	19	1			T1	1		T302	2		T204	1
alert_ping_fail	alert[0x16]	17	1			T302	1		T314	1		T296	1
alert_ping_fail	alert[0x17]	10	1			T280	1		T303	1		T245	1
alert_ping_fail	alert[0x18]	11	1			T280	1		T275	1		T312	1
alert_ping_fail	alert[0x19]	9	1			T1	1		T315	1		T316	1
alert_ping_fail	alert[0x1a]	7	1			T9	1		T317	1		T308	1
alert_ping_fail	alert[0x1b]	11	1			T244	1		T305	1		T317	1
alert_ping_fail	alert[0x1c]	7	1			T1	1		T275	1		T245	1
alert_ping_fail	alert[0x1d]	10	1			T194	1		T275	1		T313	1
alert_ping_fail	alert[0x1e]	10	1			T302	1		T314	2		T318	1
alert_ping_fail	alert[0x1f]	17	1			T9	1		T295	1		T314	1
alert_ping_fail	alert[0x20]	11	1			T1	1		T9	1		T303	1
alert_ping_fail	alert[0x21]	7	1			T204	1		T280	1		T245	1
alert_ping_fail	alert[0x22]	8	1			T9	1		T204	1		T319	1
alert_ping_fail	alert[0x23]	11	1			T1	1		T194	2		T313	1
alert_ping_fail	alert[0x24]	11	1			T320	1		T311	1		T307	1
alert_ping_fail	alert[0x25]	9	1			T204	1		T275	1		T244	1
alert_ping_fail	alert[0x26]	10	1			T9	1		T245	1		T304	1
alert_ping_fail	alert[0x27]	11	1			T242	2		T244	1		T310	1
alert_ping_fail	alert[0x28]	17	1			T37	1		T275	1		T244	1
alert_ping_fail	alert[0x29]	9	1			T303	1		T244	2		T245	1
alert_ping_fail	alert[0x2a]	14	1			T204	3		T299	1		T245	2
alert_ping_fail	alert[0x2b]	9	1			T280	1		T275	1		T321	1
alert_ping_fail	alert[0x2c]	8	1			T1	1		T10	1		T244	1
alert_ping_fail	alert[0x2d]	6	1			T204	1		T303	1		T269	1
alert_ping_fail	alert[0x2e]	9	1			T303	1		T315	2		T322	1
alert_ping_fail	alert[0x2f]	10	1			T10	2		T321	1		T323	1
alert_ping_fail	alert[0x30]	12	1			T9	1		T303	1		T194	1
alert_ping_fail	alert[0x31]	11	1			T194	1		T245	1		T321	1
alert_ping_fail	alert[0x32]	9	1			T9	1		T275	1		T304	1
alert_ping_fail	alert[0x33]	11	1			T10	1		T204	1		T303	1
alert_ping_fail	alert[0x34]	10	1			T9	1		T304	1		T305	1
alert_ping_fail	alert[0x35]	14	1			T1	1		T320	1		T304	1
alert_ping_fail	alert[0x36]	8	1			T303	1		T315	1		T305	1
alert_ping_fail	alert[0x37]	5	1			T10	1		T314	1		T311	1
alert_ping_fail	alert[0x38]	4	1			T9	1		T313	1		T324	1
alert_ping_fail	alert[0x39]	11	1			T204	1		T275	1		T244	1
alert_ping_fail	alert[0x3a]	6	1			T242	1		T244	1		T311	1
alert_ping_fail	alert[0x3b]	11	1			T302	1		T204	1		T194	2
alert_ping_fail	alert[0x3c]	14	1			T1	1		T321	2		T305	1
alert_ping_fail	alert[0x3d]	12	1			T242	1		T244	1		T310	1
alert_ping_fail	alert[0x3e]	11	1			T10	1		T302	1		T244	1
alert_ping_fail	alert[0x3f]	3	1			T245	1		T325	1		T326	1
alert_ping_fail	alert[0x40]	6	1			T9	1		T280	1		T304	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	167240	1			T16	14		T107	24		T24	11777
alert_integrity_fail	class_i[0x1]	144490	1			T4	1		T5	7153		T24	174
alert_integrity_fail	class_i[0x2]	109586	1			T15	86		T16	16		T62	10
alert_integrity_fail	class_i[0x3]	76958	1			T15	129		T16	8		T32	10787
alert_ping_fail	class_i[0x0]	157	1			T9	1		T10	9		T204	1
alert_ping_fail	class_i[0x1]	162	1			T1	8		T9	17		T37	2
alert_ping_fail	class_i[0x2]	151	1			T302	7		T204	1		T280	2
alert_ping_fail	class_i[0x3]	194	1			T1	1		T6	1		T9	1