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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.66 99.99 98.68 99.97 100.00 100.00 99.38 99.60


Total test records in report: 832
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T771 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.2850100871 Apr 02 12:38:10 PM PDT 24 Apr 02 12:38:15 PM PDT 24 227601758 ps
T139 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1762958873 Apr 02 12:38:02 PM PDT 24 Apr 02 12:43:48 PM PDT 24 19636564047 ps
T772 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1260438333 Apr 02 12:38:02 PM PDT 24 Apr 02 12:38:03 PM PDT 24 29172404 ps
T137 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3974935211 Apr 02 12:38:11 PM PDT 24 Apr 02 12:40:53 PM PDT 24 2412025717 ps
T773 /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.1462381216 Apr 02 12:38:17 PM PDT 24 Apr 02 12:38:19 PM PDT 24 7646767 ps
T122 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.281792751 Apr 02 12:38:12 PM PDT 24 Apr 02 12:44:54 PM PDT 24 30218106033 ps
T774 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.592284809 Apr 02 12:38:17 PM PDT 24 Apr 02 12:38:18 PM PDT 24 6443269 ps
T143 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3505722562 Apr 02 12:38:15 PM PDT 24 Apr 02 12:40:05 PM PDT 24 2962764719 ps
T173 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.1329301447 Apr 02 12:38:08 PM PDT 24 Apr 02 12:38:12 PM PDT 24 116158858 ps
T775 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3743263884 Apr 02 12:37:54 PM PDT 24 Apr 02 12:42:07 PM PDT 24 17862742340 ps
T776 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3377188769 Apr 02 12:38:31 PM PDT 24 Apr 02 12:38:34 PM PDT 24 17296939 ps
T777 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1184276424 Apr 02 12:38:08 PM PDT 24 Apr 02 12:38:18 PM PDT 24 130858350 ps
T135 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3599173857 Apr 02 12:38:10 PM PDT 24 Apr 02 12:43:20 PM PDT 24 12861841991 ps
T778 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.1069570514 Apr 02 12:38:14 PM PDT 24 Apr 02 12:38:15 PM PDT 24 7306840 ps
T779 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2631662474 Apr 02 12:38:02 PM PDT 24 Apr 02 12:38:39 PM PDT 24 1921717583 ps
T780 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1751574680 Apr 02 12:38:28 PM PDT 24 Apr 02 12:38:39 PM PDT 24 506764451 ps
T781 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1600592060 Apr 02 12:38:00 PM PDT 24 Apr 02 12:38:03 PM PDT 24 26216353 ps
T782 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.4293900835 Apr 02 12:38:11 PM PDT 24 Apr 02 12:38:23 PM PDT 24 131081844 ps
T783 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3150421090 Apr 02 12:38:17 PM PDT 24 Apr 02 12:38:18 PM PDT 24 13558413 ps
T784 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.3031129094 Apr 02 12:38:14 PM PDT 24 Apr 02 12:38:32 PM PDT 24 982848178 ps
T785 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.2382589248 Apr 02 12:38:00 PM PDT 24 Apr 02 12:38:02 PM PDT 24 12268097 ps
T786 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3551583104 Apr 02 12:38:09 PM PDT 24 Apr 02 12:38:26 PM PDT 24 248954947 ps
T787 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.710390967 Apr 02 12:38:02 PM PDT 24 Apr 02 12:38:04 PM PDT 24 11772224 ps
T788 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.2758831728 Apr 02 12:38:02 PM PDT 24 Apr 02 12:38:08 PM PDT 24 63885825 ps
T148 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.2750260394 Apr 02 12:38:28 PM PDT 24 Apr 02 12:40:29 PM PDT 24 1751436517 ps
T789 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.379738752 Apr 02 12:37:57 PM PDT 24 Apr 02 12:38:21 PM PDT 24 194584330 ps
T790 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.688787475 Apr 02 12:38:03 PM PDT 24 Apr 02 12:40:11 PM PDT 24 27995069823 ps
T791 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.3546889601 Apr 02 12:38:15 PM PDT 24 Apr 02 12:38:24 PM PDT 24 505860629 ps
T792 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.3586624203 Apr 02 12:38:17 PM PDT 24 Apr 02 12:38:19 PM PDT 24 15622379 ps
T793 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.3765204264 Apr 02 12:37:59 PM PDT 24 Apr 02 12:38:03 PM PDT 24 30301432 ps
T794 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2963432206 Apr 02 12:38:19 PM PDT 24 Apr 02 12:38:25 PM PDT 24 35546470 ps
T795 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.3758004186 Apr 02 12:37:59 PM PDT 24 Apr 02 12:38:07 PM PDT 24 289459394 ps
T796 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.575067268 Apr 02 12:38:31 PM PDT 24 Apr 02 12:38:34 PM PDT 24 10868453 ps
T797 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.1044435687 Apr 02 12:38:16 PM PDT 24 Apr 02 12:38:36 PM PDT 24 1080952367 ps
T798 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1163505532 Apr 02 12:37:56 PM PDT 24 Apr 02 12:38:07 PM PDT 24 354557411 ps
T155 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.3720459353 Apr 02 12:38:09 PM PDT 24 Apr 02 12:38:12 PM PDT 24 114554045 ps
T799 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.709415032 Apr 02 12:38:11 PM PDT 24 Apr 02 12:38:14 PM PDT 24 17377145 ps
T800 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2019704107 Apr 02 12:37:50 PM PDT 24 Apr 02 12:37:56 PM PDT 24 72328464 ps
T123 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3855290755 Apr 02 12:38:11 PM PDT 24 Apr 02 12:39:57 PM PDT 24 1685260102 ps
T167 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1766316250 Apr 02 12:37:57 PM PDT 24 Apr 02 12:38:00 PM PDT 24 33840426 ps
T801 /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.3302900563 Apr 02 12:38:11 PM PDT 24 Apr 02 12:38:13 PM PDT 24 10996614 ps
T802 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2923188681 Apr 02 12:38:16 PM PDT 24 Apr 02 12:38:22 PM PDT 24 41499181 ps
T803 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.861084138 Apr 02 12:38:18 PM PDT 24 Apr 02 12:38:37 PM PDT 24 1046243752 ps
T147 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1352935979 Apr 02 12:38:01 PM PDT 24 Apr 02 12:46:25 PM PDT 24 28688321604 ps
T804 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3916737253 Apr 02 12:38:10 PM PDT 24 Apr 02 12:38:29 PM PDT 24 165377197 ps
T357 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.500076585 Apr 02 12:38:13 PM PDT 24 Apr 02 12:42:49 PM PDT 24 8385079408 ps
T805 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.4266621827 Apr 02 12:37:58 PM PDT 24 Apr 02 12:42:10 PM PDT 24 6852190549 ps
T145 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2320767426 Apr 02 12:38:07 PM PDT 24 Apr 02 12:47:51 PM PDT 24 4881483150 ps
T132 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3630886390 Apr 02 12:38:03 PM PDT 24 Apr 02 12:39:29 PM PDT 24 912074107 ps
T159 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.2610986927 Apr 02 12:38:11 PM PDT 24 Apr 02 12:38:13 PM PDT 24 49701087 ps
T806 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1232736804 Apr 02 12:38:02 PM PDT 24 Apr 02 12:41:23 PM PDT 24 1724426916 ps
T807 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3461892736 Apr 02 12:37:51 PM PDT 24 Apr 02 12:38:01 PM PDT 24 366241690 ps
T808 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.4078777016 Apr 02 12:38:07 PM PDT 24 Apr 02 12:38:12 PM PDT 24 424570945 ps
T809 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3659808877 Apr 02 12:38:28 PM PDT 24 Apr 02 12:39:01 PM PDT 24 1053626773 ps
T810 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3468068068 Apr 02 12:38:13 PM PDT 24 Apr 02 12:38:17 PM PDT 24 150474930 ps
T811 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1345148104 Apr 02 12:38:14 PM PDT 24 Apr 02 12:38:24 PM PDT 24 182483057 ps
T812 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.2406242238 Apr 02 12:38:29 PM PDT 24 Apr 02 12:38:31 PM PDT 24 8013828 ps
T813 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.3289559507 Apr 02 12:38:10 PM PDT 24 Apr 02 12:38:17 PM PDT 24 383207465 ps
T146 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.3279935264 Apr 02 12:37:54 PM PDT 24 Apr 02 12:40:36 PM PDT 24 4749152990 ps
T814 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.678785669 Apr 02 12:38:15 PM PDT 24 Apr 02 12:38:16 PM PDT 24 20770435 ps
T815 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3658603586 Apr 02 12:38:21 PM PDT 24 Apr 02 12:38:23 PM PDT 24 6715263 ps
T816 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.2841463393 Apr 02 12:38:13 PM PDT 24 Apr 02 12:38:17 PM PDT 24 359319561 ps
T817 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1584096953 Apr 02 12:38:17 PM PDT 24 Apr 02 12:38:19 PM PDT 24 46351080 ps
T144 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.2196906996 Apr 02 12:38:05 PM PDT 24 Apr 02 12:39:44 PM PDT 24 3250187306 ps
T818 /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.1140364652 Apr 02 12:38:15 PM PDT 24 Apr 02 12:38:16 PM PDT 24 6746411 ps
T819 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1048013268 Apr 02 12:38:14 PM PDT 24 Apr 02 12:38:15 PM PDT 24 12253419 ps
T820 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.1362299865 Apr 02 12:38:16 PM PDT 24 Apr 02 12:38:56 PM PDT 24 596595465 ps
T358 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3879493620 Apr 02 12:38:28 PM PDT 24 Apr 02 12:43:23 PM PDT 24 2268844444 ps
T821 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.548614673 Apr 02 12:38:06 PM PDT 24 Apr 02 12:38:13 PM PDT 24 116571843 ps
T822 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.4173667914 Apr 02 12:38:02 PM PDT 24 Apr 02 12:38:45 PM PDT 24 5293867801 ps
T823 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.3617360083 Apr 02 12:38:05 PM PDT 24 Apr 02 12:38:06 PM PDT 24 13435509 ps
T824 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1529269144 Apr 02 12:38:17 PM PDT 24 Apr 02 12:42:54 PM PDT 24 24015113689 ps
T171 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1082205222 Apr 02 12:38:21 PM PDT 24 Apr 02 12:38:23 PM PDT 24 59837996 ps
T134 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1048508071 Apr 02 12:37:56 PM PDT 24 Apr 02 12:40:55 PM PDT 24 5140023580 ps
T825 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.650070130 Apr 02 12:38:07 PM PDT 24 Apr 02 12:38:15 PM PDT 24 815624932 ps
T826 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.1758777167 Apr 02 12:38:17 PM PDT 24 Apr 02 12:38:31 PM PDT 24 1431072418 ps
T827 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.806132684 Apr 02 12:38:17 PM PDT 24 Apr 02 12:38:19 PM PDT 24 9096661 ps
T828 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.3895964576 Apr 02 12:37:59 PM PDT 24 Apr 02 12:38:04 PM PDT 24 401799108 ps
T829 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.315463719 Apr 02 12:38:17 PM PDT 24 Apr 02 12:38:24 PM PDT 24 231519741 ps
T830 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.1131779728 Apr 02 12:38:10 PM PDT 24 Apr 02 12:38:18 PM PDT 24 358333593 ps
T831 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.1838321872 Apr 02 12:38:01 PM PDT 24 Apr 02 12:38:15 PM PDT 24 350315837 ps
T832 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.769915023 Apr 02 12:38:10 PM PDT 24 Apr 02 12:38:43 PM PDT 24 499476739 ps

Test location /workspace/coverage/default/47.alert_handler_entropy.2748143353
Short name T5
Test name
Test status
Simulation time 40990284059 ps
CPU time 2407.16 seconds
Started Apr 02 01:02:21 PM PDT 24
Finished Apr 02 01:42:28 PM PDT 24
Peak memory 272796 kb
Host smart-afbe9234-fc6b-4a92-b810-26d96ca4639e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748143353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.2748143353
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.1731133470
Short name T24
Test name
Test status
Simulation time 209805643529 ps
CPU time 5085.42 seconds
Started Apr 02 01:01:17 PM PDT 24
Finished Apr 02 02:26:05 PM PDT 24
Peak memory 353996 kb
Host smart-48dd67f0-fe80-46f5-9471-435fb223351a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731133470 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.1731133470
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.905617379
Short name T29
Test name
Test status
Simulation time 2368083535 ps
CPU time 11.13 seconds
Started Apr 02 01:00:58 PM PDT 24
Finished Apr 02 01:01:10 PM PDT 24
Peak memory 269628 kb
Host smart-df8130e5-7dc0-4a6e-ac2c-f0731cf9d33a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=905617379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.905617379
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.56854246
Short name T4
Test name
Test status
Simulation time 107011517770 ps
CPU time 1595.76 seconds
Started Apr 02 01:00:47 PM PDT 24
Finished Apr 02 01:27:24 PM PDT 24
Peak memory 273436 kb
Host smart-c68f91ca-1fe1-401a-ad93-d68e06b3be8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56854246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.56854246
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2466047981
Short name T113
Test name
Test status
Simulation time 34249658799 ps
CPU time 569.55 seconds
Started Apr 02 12:38:03 PM PDT 24
Finished Apr 02 12:47:32 PM PDT 24
Peak memory 265228 kb
Host smart-9e22f8ff-b25a-4526-97e0-6458400034a1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466047981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.2466047981
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.136658749
Short name T41
Test name
Test status
Simulation time 201442897011 ps
CPU time 2797.81 seconds
Started Apr 02 01:00:51 PM PDT 24
Finished Apr 02 01:47:32 PM PDT 24
Peak memory 289396 kb
Host smart-028a064d-a5db-4e73-b846-9a713996d54e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136658749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_hand
ler_stress_all.136658749
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1797807255
Short name T151
Test name
Test status
Simulation time 528473192 ps
CPU time 40.16 seconds
Started Apr 02 12:37:55 PM PDT 24
Finished Apr 02 12:38:36 PM PDT 24
Peak memory 248520 kb
Host smart-a25ee6e5-4007-4041-ba85-8773dd56f64f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1797807255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1797807255
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.4096272825
Short name T16
Test name
Test status
Simulation time 39962417688 ps
CPU time 2489.73 seconds
Started Apr 02 01:01:04 PM PDT 24
Finished Apr 02 01:42:37 PM PDT 24
Peak memory 286216 kb
Host smart-2a7c50d0-67c2-48d7-ad28-02f17ef3c731
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096272825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.4096272825
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.3048606348
Short name T97
Test name
Test status
Simulation time 68719396535 ps
CPU time 6198.31 seconds
Started Apr 02 01:01:20 PM PDT 24
Finished Apr 02 02:44:40 PM PDT 24
Peak memory 371272 kb
Host smart-1e20f4b9-25a8-4c74-9c19-8fc8da7b9696
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048606348 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.3048606348
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.556187462
Short name T114
Test name
Test status
Simulation time 1561625733 ps
CPU time 182.43 seconds
Started Apr 02 12:38:16 PM PDT 24
Finished Apr 02 12:41:18 PM PDT 24
Peak memory 269444 kb
Host smart-78a39e67-0dfa-445c-8826-d6cd21e65ace
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=556187462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_erro
rs.556187462
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1790217340
Short name T296
Test name
Test status
Simulation time 68130262310 ps
CPU time 1925.08 seconds
Started Apr 02 01:01:12 PM PDT 24
Finished Apr 02 01:33:23 PM PDT 24
Peak memory 268372 kb
Host smart-320ebb49-6949-45c6-8697-9569184d1ef6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790217340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1790217340
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.3633701829
Short name T267
Test name
Test status
Simulation time 23634637697 ps
CPU time 1704.72 seconds
Started Apr 02 01:01:36 PM PDT 24
Finished Apr 02 01:30:01 PM PDT 24
Peak memory 289952 kb
Host smart-5431e8bf-b85c-4bab-b748-ba0bb60e4220
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633701829 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.3633701829
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.1112436189
Short name T78
Test name
Test status
Simulation time 29475934552 ps
CPU time 3499.79 seconds
Started Apr 02 01:01:22 PM PDT 24
Finished Apr 02 01:59:42 PM PDT 24
Peak memory 330988 kb
Host smart-49507805-f554-46ae-b807-d68e72c2ce05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112436189 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.1112436189
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1652664511
Short name T133
Test name
Test status
Simulation time 17175804163 ps
CPU time 615.3 seconds
Started Apr 02 12:38:03 PM PDT 24
Finished Apr 02 12:48:19 PM PDT 24
Peak memory 265144 kb
Host smart-975c5f3e-4648-4621-9d51-39896f1d2068
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652664511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.1652664511
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1762958873
Short name T139
Test name
Test status
Simulation time 19636564047 ps
CPU time 346.25 seconds
Started Apr 02 12:38:02 PM PDT 24
Finished Apr 02 12:43:48 PM PDT 24
Peak memory 265148 kb
Host smart-d2323456-b053-4df3-af95-a2d8f86aaafd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1762958873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.1762958873
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.2148278533
Short name T9
Test name
Test status
Simulation time 10557955022 ps
CPU time 485.42 seconds
Started Apr 02 01:01:06 PM PDT 24
Finished Apr 02 01:09:15 PM PDT 24
Peak memory 247924 kb
Host smart-25c6b1a3-118e-456d-9f35-6a253eae7d50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148278533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.2148278533
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.276731182
Short name T299
Test name
Test status
Simulation time 278085905798 ps
CPU time 2438.5 seconds
Started Apr 02 01:01:02 PM PDT 24
Finished Apr 02 01:41:44 PM PDT 24
Peak memory 285252 kb
Host smart-143a5393-eb11-4ea2-b4b0-55d9f391d094
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276731182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.276731182
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3326888149
Short name T129
Test name
Test status
Simulation time 20382009747 ps
CPU time 309.73 seconds
Started Apr 02 12:38:10 PM PDT 24
Finished Apr 02 12:43:20 PM PDT 24
Peak memory 265048 kb
Host smart-cb19efab-68a3-4a7a-bcfe-2d6bafada038
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3326888149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.3326888149
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.918284604
Short name T239
Test name
Test status
Simulation time 14494670 ps
CPU time 1.69 seconds
Started Apr 02 12:38:15 PM PDT 24
Finished Apr 02 12:38:17 PM PDT 24
Peak memory 235792 kb
Host smart-da6dcf82-aba8-4df0-b661-3c2e944eec66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=918284604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.918284604
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.107306510
Short name T57
Test name
Test status
Simulation time 1139829971 ps
CPU time 16.63 seconds
Started Apr 02 01:00:47 PM PDT 24
Finished Apr 02 01:01:04 PM PDT 24
Peak memory 248872 kb
Host smart-ea9253e1-e653-4ed3-a5cf-354122c54fb2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=107306510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.107306510
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.1128613991
Short name T301
Test name
Test status
Simulation time 41659964055 ps
CPU time 2450.48 seconds
Started Apr 02 01:01:07 PM PDT 24
Finished Apr 02 01:42:01 PM PDT 24
Peak memory 281768 kb
Host smart-4b9f7c68-8b5b-4761-8e1f-b6c70dbe6c72
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128613991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.1128613991
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.1326530415
Short name T138
Test name
Test status
Simulation time 50439909828 ps
CPU time 961.45 seconds
Started Apr 02 12:38:01 PM PDT 24
Finished Apr 02 12:54:03 PM PDT 24
Peak memory 265068 kb
Host smart-249ed23f-e563-4f08-9f55-c75ec7d80dad
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326530415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.1326530415
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3599173857
Short name T135
Test name
Test status
Simulation time 12861841991 ps
CPU time 310.17 seconds
Started Apr 02 12:38:10 PM PDT 24
Finished Apr 02 12:43:20 PM PDT 24
Peak memory 265148 kb
Host smart-c9216620-d36d-42a6-b06e-f5e7d0479466
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3599173857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.3599173857
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.1141628878
Short name T244
Test name
Test status
Simulation time 42547630161 ps
CPU time 456.3 seconds
Started Apr 02 01:00:40 PM PDT 24
Finished Apr 02 01:08:17 PM PDT 24
Peak memory 247912 kb
Host smart-610670b9-172f-409d-a401-d7564914f00f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141628878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.1141628878
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.3478701467
Short name T531
Test name
Test status
Simulation time 9754998317 ps
CPU time 403.51 seconds
Started Apr 02 01:01:18 PM PDT 24
Finished Apr 02 01:08:02 PM PDT 24
Peak memory 247928 kb
Host smart-091388dd-1b2f-4a8d-8eb4-6f3e7bf6ba2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478701467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.3478701467
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.3202379125
Short name T90
Test name
Test status
Simulation time 60958274498 ps
CPU time 2326.44 seconds
Started Apr 02 01:01:21 PM PDT 24
Finished Apr 02 01:40:09 PM PDT 24
Peak memory 284636 kb
Host smart-f57fd789-3315-4b63-89a8-c508584ef0ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202379125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.3202379125
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.2788376094
Short name T657
Test name
Test status
Simulation time 439216995032 ps
CPU time 2965.8 seconds
Started Apr 02 01:01:41 PM PDT 24
Finished Apr 02 01:51:07 PM PDT 24
Peak memory 288464 kb
Host smart-92e7d173-c8f1-4526-9f78-115cc738bda9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788376094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.2788376094
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.4261974893
Short name T245
Test name
Test status
Simulation time 12373347556 ps
CPU time 468.74 seconds
Started Apr 02 01:00:56 PM PDT 24
Finished Apr 02 01:08:48 PM PDT 24
Peak memory 247144 kb
Host smart-e402ac29-99a5-478f-b93b-05804c7fb14b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261974893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.4261974893
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3686107746
Short name T124
Test name
Test status
Simulation time 16281486386 ps
CPU time 1138.45 seconds
Started Apr 02 12:38:07 PM PDT 24
Finished Apr 02 12:57:05 PM PDT 24
Peak memory 265228 kb
Host smart-7cc1546a-8003-4314-8953-47cb1e9a9720
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686107746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.3686107746
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.442843759
Short name T63
Test name
Test status
Simulation time 25206714315 ps
CPU time 405.64 seconds
Started Apr 02 01:01:21 PM PDT 24
Finished Apr 02 01:08:08 PM PDT 24
Peak memory 257184 kb
Host smart-3588b65a-859e-4b30-a7c7-ad12a8e888ef
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442843759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_han
dler_stress_all.442843759
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.3393135137
Short name T106
Test name
Test status
Simulation time 278183729381 ps
CPU time 3556.38 seconds
Started Apr 02 01:01:31 PM PDT 24
Finished Apr 02 02:00:48 PM PDT 24
Peak memory 305652 kb
Host smart-a6a3d666-cecb-4a79-8295-6fe910ad1566
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393135137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.3393135137
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.281792751
Short name T122
Test name
Test status
Simulation time 30218106033 ps
CPU time 401.76 seconds
Started Apr 02 12:38:12 PM PDT 24
Finished Apr 02 12:44:54 PM PDT 24
Peak memory 272648 kb
Host smart-057619a9-2c6f-4be9-86fd-00248abf7f64
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=281792751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_erro
rs.281792751
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.2743356579
Short name T341
Test name
Test status
Simulation time 9965404 ps
CPU time 1.54 seconds
Started Apr 02 12:38:18 PM PDT 24
Finished Apr 02 12:38:20 PM PDT 24
Peak memory 236664 kb
Host smart-9ff93b14-0613-45b4-8a29-25c4e47cc386
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2743356579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.2743356579
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.2258818006
Short name T280
Test name
Test status
Simulation time 51307211031 ps
CPU time 313.4 seconds
Started Apr 02 01:00:57 PM PDT 24
Finished Apr 02 01:06:12 PM PDT 24
Peak memory 247912 kb
Host smart-271260eb-ee06-4949-89ae-80623ee41c9b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258818006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.2258818006
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.386869572
Short name T52
Test name
Test status
Simulation time 81011222057 ps
CPU time 7150.06 seconds
Started Apr 02 01:00:42 PM PDT 24
Finished Apr 02 02:59:53 PM PDT 24
Peak memory 354836 kb
Host smart-293b68af-ba03-4ec0-96a4-bf514a334985
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386869572 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.386869572
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.2784089704
Short name T98
Test name
Test status
Simulation time 39799385872 ps
CPU time 490.97 seconds
Started Apr 02 01:01:34 PM PDT 24
Finished Apr 02 01:09:45 PM PDT 24
Peak memory 267816 kb
Host smart-d9cf46b0-ec8d-4df6-b9a6-beb8218c5364
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784089704 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.2784089704
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.1530866011
Short name T557
Test name
Test status
Simulation time 85092787158 ps
CPU time 2333.63 seconds
Started Apr 02 01:01:20 PM PDT 24
Finished Apr 02 01:40:14 PM PDT 24
Peak memory 272564 kb
Host smart-217cfa53-b688-43b2-b560-00ff9c1c35ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530866011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.1530866011
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.4150873428
Short name T150
Test name
Test status
Simulation time 174015220 ps
CPU time 3.78 seconds
Started Apr 02 12:38:07 PM PDT 24
Finished Apr 02 12:38:11 PM PDT 24
Peak memory 236636 kb
Host smart-fbdbb360-db2d-4464-bbc3-2843fc9eee30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4150873428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.4150873428
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2320767426
Short name T145
Test name
Test status
Simulation time 4881483150 ps
CPU time 583.57 seconds
Started Apr 02 12:38:07 PM PDT 24
Finished Apr 02 12:47:51 PM PDT 24
Peak memory 265060 kb
Host smart-e5dbb850-0b0c-44da-9c9c-1741286a135b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320767426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.2320767426
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.399934040
Short name T44
Test name
Test status
Simulation time 18539879739 ps
CPU time 1463.56 seconds
Started Apr 02 01:01:15 PM PDT 24
Finished Apr 02 01:25:42 PM PDT 24
Peak memory 289436 kb
Host smart-ace3b83e-87f6-4b15-8c52-27ffe3aac1fa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399934040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_han
dler_stress_all.399934040
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.3427678176
Short name T251
Test name
Test status
Simulation time 25660596590 ps
CPU time 1112.76 seconds
Started Apr 02 01:00:42 PM PDT 24
Finished Apr 02 01:19:15 PM PDT 24
Peak memory 289088 kb
Host smart-5d37b4f2-0504-434b-9b74-698c8bf94ce5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427678176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.3427678176
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3135691996
Short name T247
Test name
Test status
Simulation time 204459705 ps
CPU time 8.44 seconds
Started Apr 02 12:38:00 PM PDT 24
Finished Apr 02 12:38:08 PM PDT 24
Peak memory 240376 kb
Host smart-2323cbc8-7531-43ef-a8d5-ca20c4c2a990
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135691996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.3135691996
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3577525029
Short name T120
Test name
Test status
Simulation time 84286564268 ps
CPU time 1273.53 seconds
Started Apr 02 12:38:11 PM PDT 24
Finished Apr 02 12:59:25 PM PDT 24
Peak memory 265164 kb
Host smart-89acd226-827f-44c5-a714-efe3af79006a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577525029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.3577525029
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.3281842766
Short name T72
Test name
Test status
Simulation time 1282714583 ps
CPU time 30.61 seconds
Started Apr 02 01:00:55 PM PDT 24
Finished Apr 02 01:01:27 PM PDT 24
Peak memory 248408 kb
Host smart-5e615b07-233d-4966-b288-2d372675ee87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32818
42766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.3281842766
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.307340011
Short name T194
Test name
Test status
Simulation time 18618703761 ps
CPU time 401.12 seconds
Started Apr 02 01:01:13 PM PDT 24
Finished Apr 02 01:07:59 PM PDT 24
Peak memory 248152 kb
Host smart-f9826e39-f3ed-4870-8391-e43b72464417
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307340011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.307340011
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.2485693306
Short name T334
Test name
Test status
Simulation time 45158271386 ps
CPU time 2593.58 seconds
Started Apr 02 01:01:24 PM PDT 24
Finished Apr 02 01:44:39 PM PDT 24
Peak memory 289768 kb
Host smart-50c0d8d4-7a15-45e7-b611-f3aecafa1645
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485693306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.2485693306
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.1029142976
Short name T220
Test name
Test status
Simulation time 159628555 ps
CPU time 3.54 seconds
Started Apr 02 01:00:49 PM PDT 24
Finished Apr 02 01:00:55 PM PDT 24
Peak memory 249024 kb
Host smart-f093165d-b9df-4ca9-8eb9-e67c133ee004
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1029142976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.1029142976
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.4248953698
Short name T217
Test name
Test status
Simulation time 121427804 ps
CPU time 3.51 seconds
Started Apr 02 01:01:11 PM PDT 24
Finished Apr 02 01:01:20 PM PDT 24
Peak memory 249000 kb
Host smart-546740f0-6ccc-496b-9a83-f7a4ed3ce57f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4248953698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.4248953698
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.3278740918
Short name T221
Test name
Test status
Simulation time 38757901 ps
CPU time 3.49 seconds
Started Apr 02 01:01:03 PM PDT 24
Finished Apr 02 01:01:09 PM PDT 24
Peak memory 249140 kb
Host smart-0b8b10bb-c8a0-4482-b55b-491bca7d51a7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3278740918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.3278740918
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.1217619414
Short name T213
Test name
Test status
Simulation time 21281543 ps
CPU time 2.61 seconds
Started Apr 02 01:01:13 PM PDT 24
Finished Apr 02 01:01:20 PM PDT 24
Peak memory 249052 kb
Host smart-d7fb13c4-fdbe-4258-8d1b-1eb19ffbf070
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1217619414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.1217619414
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.593736846
Short name T348
Test name
Test status
Simulation time 10583615 ps
CPU time 1.63 seconds
Started Apr 02 12:37:55 PM PDT 24
Finished Apr 02 12:37:57 PM PDT 24
Peak memory 236620 kb
Host smart-10400159-b3c1-4990-9a5a-6659efc05d12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=593736846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.593736846
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.3886583790
Short name T254
Test name
Test status
Simulation time 93964312 ps
CPU time 8.75 seconds
Started Apr 02 01:00:52 PM PDT 24
Finished Apr 02 01:01:05 PM PDT 24
Peak memory 252520 kb
Host smart-a44ecbda-7166-4386-b430-87c4e6e52811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38865
83790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.3886583790
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.3998236153
Short name T108
Test name
Test status
Simulation time 563850286 ps
CPU time 19.58 seconds
Started Apr 02 01:01:16 PM PDT 24
Finished Apr 02 01:01:38 PM PDT 24
Peak memory 255536 kb
Host smart-d3f0b9f1-6822-4719-a7d1-81d5211e1798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39982
36153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.3998236153
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.609567101
Short name T269
Test name
Test status
Simulation time 74828412148 ps
CPU time 1680.11 seconds
Started Apr 02 01:01:14 PM PDT 24
Finished Apr 02 01:29:19 PM PDT 24
Peak memory 288176 kb
Host smart-4d4e55fd-0816-4c82-a9cc-f792c62dc2b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609567101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.609567101
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.2124905833
Short name T305
Test name
Test status
Simulation time 10158963352 ps
CPU time 396.58 seconds
Started Apr 02 01:01:35 PM PDT 24
Finished Apr 02 01:08:12 PM PDT 24
Peak memory 248052 kb
Host smart-51cecda4-ca7f-4d2f-8aa7-c2156a47ff8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124905833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.2124905833
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.3446618797
Short name T606
Test name
Test status
Simulation time 57238899051 ps
CPU time 5128.97 seconds
Started Apr 02 01:01:36 PM PDT 24
Finished Apr 02 02:27:05 PM PDT 24
Peak memory 322232 kb
Host smart-9ce4c126-1fa0-4761-aec7-f7699524a0c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446618797 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.3446618797
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.3977566851
Short name T639
Test name
Test status
Simulation time 35540648009 ps
CPU time 2077.19 seconds
Started Apr 02 01:01:38 PM PDT 24
Finished Apr 02 01:36:16 PM PDT 24
Peak memory 282188 kb
Host smart-c8964321-fe61-4046-a240-f61c209e1e5d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977566851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.3977566851
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.1470908913
Short name T259
Test name
Test status
Simulation time 138692379127 ps
CPU time 4791.19 seconds
Started Apr 02 01:01:48 PM PDT 24
Finished Apr 02 02:21:39 PM PDT 24
Peak memory 321192 kb
Host smart-1af1e8f7-0a39-4808-b6f9-7267a8dce0f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470908913 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.1470908913
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.3015235319
Short name T15
Test name
Test status
Simulation time 6832958877 ps
CPU time 400.44 seconds
Started Apr 02 01:01:18 PM PDT 24
Finished Apr 02 01:07:59 PM PDT 24
Peak memory 257204 kb
Host smart-5df4fdc0-f936-430d-bece-19a2992c8097
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015235319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.3015235319
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.3863188998
Short name T104
Test name
Test status
Simulation time 1621923615 ps
CPU time 19.9 seconds
Started Apr 02 01:01:55 PM PDT 24
Finished Apr 02 01:02:15 PM PDT 24
Peak memory 248816 kb
Host smart-76736429-93ea-4b71-baaf-b4131923e833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38631
88998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.3863188998
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2775919557
Short name T118
Test name
Test status
Simulation time 69212734957 ps
CPU time 1241.18 seconds
Started Apr 02 12:37:56 PM PDT 24
Finished Apr 02 12:58:37 PM PDT 24
Peak memory 271448 kb
Host smart-9d95735f-bd18-465e-8042-83731523d805
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775919557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.2775919557
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.2835214580
Short name T112
Test name
Test status
Simulation time 17801369957 ps
CPU time 324.21 seconds
Started Apr 02 12:37:57 PM PDT 24
Finished Apr 02 12:43:21 PM PDT 24
Peak memory 266184 kb
Host smart-c4b1e0c5-5d62-4cdf-a215-339498f9dd6c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2835214580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.2835214580
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.194664770
Short name T278
Test name
Test status
Simulation time 221891514 ps
CPU time 8.04 seconds
Started Apr 02 01:01:00 PM PDT 24
Finished Apr 02 01:01:12 PM PDT 24
Peak memory 252844 kb
Host smart-ab2b192f-04d1-448f-8b57-2efb2a79ca1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19466
4770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.194664770
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.3577553355
Short name T285
Test name
Test status
Simulation time 14412836468 ps
CPU time 947.54 seconds
Started Apr 02 01:01:12 PM PDT 24
Finished Apr 02 01:17:05 PM PDT 24
Peak memory 265232 kb
Host smart-e206f9ec-ea7a-42aa-bef0-c37a0a748d2e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577553355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.3577553355
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.729765124
Short name T264
Test name
Test status
Simulation time 157816661185 ps
CPU time 7161.61 seconds
Started Apr 02 01:01:10 PM PDT 24
Finished Apr 02 03:00:39 PM PDT 24
Peak memory 354844 kb
Host smart-4d7d0a32-d817-4eed-964f-8f850aad466a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729765124 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.729765124
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.962495739
Short name T271
Test name
Test status
Simulation time 166803162 ps
CPU time 12.96 seconds
Started Apr 02 01:01:36 PM PDT 24
Finished Apr 02 01:01:49 PM PDT 24
Peak memory 252716 kb
Host smart-de09e332-8a04-4d7c-88d1-96fcedf9b69e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96249
5739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.962495739
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.4093111877
Short name T298
Test name
Test status
Simulation time 160495819561 ps
CPU time 6585.57 seconds
Started Apr 02 01:01:20 PM PDT 24
Finished Apr 02 02:51:07 PM PDT 24
Peak memory 354536 kb
Host smart-9e98e1ac-d21f-4c87-b650-d81b8c817f73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093111877 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.4093111877
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.2763314755
Short name T339
Test name
Test status
Simulation time 40909400586 ps
CPU time 2434 seconds
Started Apr 02 01:01:23 PM PDT 24
Finished Apr 02 01:41:59 PM PDT 24
Peak memory 272712 kb
Host smart-f34960c0-f712-4b37-bf66-508f8fed33ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763314755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.2763314755
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.1005221954
Short name T265
Test name
Test status
Simulation time 57256894972 ps
CPU time 3318.08 seconds
Started Apr 02 01:01:46 PM PDT 24
Finished Apr 02 01:57:05 PM PDT 24
Peak memory 330836 kb
Host smart-c2b1dff5-a8f3-4f63-9a8f-58975803ab8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005221954 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.1005221954
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.282347304
Short name T252
Test name
Test status
Simulation time 700842549 ps
CPU time 15.01 seconds
Started Apr 02 01:01:59 PM PDT 24
Finished Apr 02 01:02:14 PM PDT 24
Peak memory 247412 kb
Host smart-7888a163-155b-4489-8429-4edbaf7fc52b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28234
7304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.282347304
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.1372934596
Short name T102
Test name
Test status
Simulation time 287901980495 ps
CPU time 3441.08 seconds
Started Apr 02 01:02:09 PM PDT 24
Finished Apr 02 01:59:31 PM PDT 24
Peak memory 305724 kb
Host smart-59b0f964-5c31-4f0d-94e4-c863e6b2077a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372934596 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.1372934596
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.1435406409
Short name T270
Test name
Test status
Simulation time 1446854943 ps
CPU time 27.73 seconds
Started Apr 02 01:02:09 PM PDT 24
Finished Apr 02 01:02:37 PM PDT 24
Peak memory 255356 kb
Host smart-a17f703e-90d0-480b-b97a-ad63e5d97553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14354
06409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.1435406409
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.2514456241
Short name T51
Test name
Test status
Simulation time 19263492217 ps
CPU time 1023.59 seconds
Started Apr 02 01:01:03 PM PDT 24
Finished Apr 02 01:18:09 PM PDT 24
Peak memory 273308 kb
Host smart-a06711ce-5d54-4bc0-9bb0-583fe62d7b55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514456241 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.2514456241
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1115320822
Short name T158
Test name
Test status
Simulation time 79948192 ps
CPU time 4.9 seconds
Started Apr 02 12:38:15 PM PDT 24
Finished Apr 02 12:38:20 PM PDT 24
Peak memory 235796 kb
Host smart-ed3a8362-c41c-4948-a14c-f83fee9f9477
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1115320822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.1115320822
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.669165855
Short name T163
Test name
Test status
Simulation time 8259170332 ps
CPU time 86.03 seconds
Started Apr 02 12:38:08 PM PDT 24
Finished Apr 02 12:39:35 PM PDT 24
Peak memory 245144 kb
Host smart-223ed065-76e9-47a6-ab9a-ecbf4b131c2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=669165855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.669165855
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.1747598955
Short name T156
Test name
Test status
Simulation time 996370433 ps
CPU time 72.94 seconds
Started Apr 02 12:38:18 PM PDT 24
Finished Apr 02 12:39:32 PM PDT 24
Peak memory 245252 kb
Host smart-3e15c72a-174b-4e23-8707-08438ffd5bff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1747598955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.1747598955
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1048508071
Short name T134
Test name
Test status
Simulation time 5140023580 ps
CPU time 179.48 seconds
Started Apr 02 12:37:56 PM PDT 24
Finished Apr 02 12:40:55 PM PDT 24
Peak memory 265052 kb
Host smart-000642ac-fe1c-4b76-8c13-28eca3d7d1e0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1048508071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.1048508071
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1766316250
Short name T167
Test name
Test status
Simulation time 33840426 ps
CPU time 2.95 seconds
Started Apr 02 12:37:57 PM PDT 24
Finished Apr 02 12:38:00 PM PDT 24
Peak memory 236640 kb
Host smart-445e993b-caac-49ca-8189-6c328298a0c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1766316250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.1766316250
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1343614487
Short name T157
Test name
Test status
Simulation time 114339273 ps
CPU time 2.95 seconds
Started Apr 02 12:37:55 PM PDT 24
Finished Apr 02 12:37:58 PM PDT 24
Peak memory 237192 kb
Host smart-399b31f3-a651-4d6e-942a-63c0d30dc1fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1343614487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.1343614487
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2554828372
Short name T165
Test name
Test status
Simulation time 58584389 ps
CPU time 3.23 seconds
Started Apr 02 12:38:05 PM PDT 24
Finished Apr 02 12:38:08 PM PDT 24
Peak memory 235788 kb
Host smart-0a16c193-6f67-4736-9c0b-6edf83ac30db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2554828372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.2554828372
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.4168980124
Short name T130
Test name
Test status
Simulation time 6426304594 ps
CPU time 94.62 seconds
Started Apr 02 12:38:18 PM PDT 24
Finished Apr 02 12:39:53 PM PDT 24
Peak memory 256972 kb
Host smart-4d6d5624-7b6f-4583-9e66-0613a7e45e66
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4168980124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.4168980124
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.3720459353
Short name T155
Test name
Test status
Simulation time 114554045 ps
CPU time 3.21 seconds
Started Apr 02 12:38:09 PM PDT 24
Finished Apr 02 12:38:12 PM PDT 24
Peak memory 236648 kb
Host smart-4d8fb4d4-7628-43e7-b993-6295da612f74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3720459353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.3720459353
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1177017509
Short name T166
Test name
Test status
Simulation time 614209901 ps
CPU time 20.93 seconds
Started Apr 02 12:38:07 PM PDT 24
Finished Apr 02 12:38:28 PM PDT 24
Peak memory 240256 kb
Host smart-2d50c9b4-d12a-48f1-8925-037644535e99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1177017509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.1177017509
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.564055452
Short name T160
Test name
Test status
Simulation time 63774479 ps
CPU time 3.37 seconds
Started Apr 02 12:38:02 PM PDT 24
Finished Apr 02 12:38:06 PM PDT 24
Peak memory 236640 kb
Host smart-12ac5f1f-5c16-44e5-a672-507c45922dc5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=564055452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.564055452
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3758365021
Short name T131
Test name
Test status
Simulation time 7569127723 ps
CPU time 285.92 seconds
Started Apr 02 12:38:00 PM PDT 24
Finished Apr 02 12:42:46 PM PDT 24
Peak memory 265148 kb
Host smart-e78ae734-dc43-4874-90f0-bfb13796d15d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3758365021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.3758365021
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2581848451
Short name T168
Test name
Test status
Simulation time 2254409274 ps
CPU time 67 seconds
Started Apr 02 12:38:02 PM PDT 24
Finished Apr 02 12:39:09 PM PDT 24
Peak memory 239600 kb
Host smart-34ba8a59-9d3b-4f6b-a1aa-53d0a6b19ba4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2581848451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.2581848451
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3272347117
Short name T161
Test name
Test status
Simulation time 104674757 ps
CPU time 5.98 seconds
Started Apr 02 12:37:51 PM PDT 24
Finished Apr 02 12:37:57 PM PDT 24
Peak memory 236648 kb
Host smart-2b62c213-162a-4eec-8d9c-166b9076d867
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3272347117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.3272347117
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2489442571
Short name T164
Test name
Test status
Simulation time 4769467361 ps
CPU time 83.33 seconds
Started Apr 02 12:38:16 PM PDT 24
Finished Apr 02 12:39:40 PM PDT 24
Peak memory 240332 kb
Host smart-132e7e16-0e8d-4fa0-98f2-20581f2c7f6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2489442571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.2489442571
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.3168295494
Short name T149
Test name
Test status
Simulation time 37876196 ps
CPU time 3.67 seconds
Started Apr 02 12:38:13 PM PDT 24
Finished Apr 02 12:38:17 PM PDT 24
Peak memory 236672 kb
Host smart-7c004440-bc39-474d-ba68-23b7e656ac96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3168295494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.3168295494
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1082205222
Short name T171
Test name
Test status
Simulation time 59837996 ps
CPU time 2.2 seconds
Started Apr 02 12:38:21 PM PDT 24
Finished Apr 02 12:38:23 PM PDT 24
Peak memory 236948 kb
Host smart-d5160acc-69d1-4b38-8258-f7edb5ec7cde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1082205222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.1082205222
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.1329301447
Short name T173
Test name
Test status
Simulation time 116158858 ps
CPU time 3.45 seconds
Started Apr 02 12:38:08 PM PDT 24
Finished Apr 02 12:38:12 PM PDT 24
Peak memory 236404 kb
Host smart-a6b4573b-3609-4624-8553-e77f630b2a23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1329301447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.1329301447
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3945958901
Short name T162
Test name
Test status
Simulation time 31358971 ps
CPU time 2.62 seconds
Started Apr 02 12:38:42 PM PDT 24
Finished Apr 02 12:38:45 PM PDT 24
Peak memory 235760 kb
Host smart-08de7285-da44-4822-9914-a1c98ee8396b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3945958901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.3945958901
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.4152918365
Short name T21
Test name
Test status
Simulation time 12085350559 ps
CPU time 47.62 seconds
Started Apr 02 01:01:20 PM PDT 24
Finished Apr 02 01:02:08 PM PDT 24
Peak memory 255536 kb
Host smart-5a941abe-f991-475f-afb0-a682f4c963a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41529
18365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.4152918365
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.269812355
Short name T170
Test name
Test status
Simulation time 3459101951 ps
CPU time 254.74 seconds
Started Apr 02 12:37:55 PM PDT 24
Finished Apr 02 12:42:10 PM PDT 24
Peak memory 240264 kb
Host smart-bf23cd12-8036-4684-9277-a696abadbd14
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=269812355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.269812355
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3743263884
Short name T775
Test name
Test status
Simulation time 17862742340 ps
CPU time 252.82 seconds
Started Apr 02 12:37:54 PM PDT 24
Finished Apr 02 12:42:07 PM PDT 24
Peak memory 236632 kb
Host smart-1692ed0b-e19c-42f3-86e4-6fea6efd8470
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3743263884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.3743263884
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2019704107
Short name T800
Test name
Test status
Simulation time 72328464 ps
CPU time 5.79 seconds
Started Apr 02 12:37:50 PM PDT 24
Finished Apr 02 12:37:56 PM PDT 24
Peak memory 240244 kb
Host smart-b3ef04d7-8efc-4ae2-ab64-1cb1531ce7ab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2019704107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2019704107
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.3758004186
Short name T795
Test name
Test status
Simulation time 289459394 ps
CPU time 7.77 seconds
Started Apr 02 12:37:59 PM PDT 24
Finished Apr 02 12:38:07 PM PDT 24
Peak memory 240112 kb
Host smart-f84c2d49-e65c-4aa2-9c80-3f12d2af3862
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758004186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.3758004186
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.3880661386
Short name T731
Test name
Test status
Simulation time 162912140 ps
CPU time 8.76 seconds
Started Apr 02 12:37:57 PM PDT 24
Finished Apr 02 12:38:06 PM PDT 24
Peak memory 236604 kb
Host smart-70f2e539-fd86-4b46-9f66-3d62c234acb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3880661386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.3880661386
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3196403056
Short name T736
Test name
Test status
Simulation time 318395699 ps
CPU time 21.52 seconds
Started Apr 02 12:37:54 PM PDT 24
Finished Apr 02 12:38:15 PM PDT 24
Peak memory 244840 kb
Host smart-c7557240-2877-4439-8c40-57368270d966
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3196403056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.3196403056
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1148096292
Short name T116
Test name
Test status
Simulation time 5431151408 ps
CPU time 197.72 seconds
Started Apr 02 12:37:52 PM PDT 24
Finished Apr 02 12:41:10 PM PDT 24
Peak memory 265160 kb
Host smart-ebd65ec5-d3ce-4134-b064-5c329d5c8858
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1148096292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.1148096292
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1321868809
Short name T136
Test name
Test status
Simulation time 26453046658 ps
CPU time 1003.61 seconds
Started Apr 02 12:37:59 PM PDT 24
Finished Apr 02 12:54:43 PM PDT 24
Peak memory 265132 kb
Host smart-4bf21d9a-afa5-4de1-83ea-49c891c2554e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321868809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.1321868809
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3461892736
Short name T807
Test name
Test status
Simulation time 366241690 ps
CPU time 10.7 seconds
Started Apr 02 12:37:51 PM PDT 24
Finished Apr 02 12:38:01 PM PDT 24
Peak memory 253016 kb
Host smart-7ae3fe1c-690c-490b-b5e4-b5c64ea9f12d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3461892736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3461892736
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.910218296
Short name T733
Test name
Test status
Simulation time 7685960227 ps
CPU time 152.78 seconds
Started Apr 02 12:38:03 PM PDT 24
Finished Apr 02 12:40:36 PM PDT 24
Peak memory 240552 kb
Host smart-39115bb6-67bf-4c39-b162-3302f9bcede2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=910218296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.910218296
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.518242889
Short name T770
Test name
Test status
Simulation time 5918322803 ps
CPU time 191.47 seconds
Started Apr 02 12:38:03 PM PDT 24
Finished Apr 02 12:41:15 PM PDT 24
Peak memory 240288 kb
Host smart-d0d93954-d493-4e79-ae3c-4673f5ec90fc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=518242889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.518242889
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1540741716
Short name T188
Test name
Test status
Simulation time 145874913 ps
CPU time 6.79 seconds
Started Apr 02 12:38:07 PM PDT 24
Finished Apr 02 12:38:14 PM PDT 24
Peak memory 240236 kb
Host smart-836922a7-5df4-4edb-adb9-9787809e7e89
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1540741716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.1540741716
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1794361102
Short name T732
Test name
Test status
Simulation time 472462255 ps
CPU time 8.14 seconds
Started Apr 02 12:38:03 PM PDT 24
Finished Apr 02 12:38:11 PM PDT 24
Peak memory 250964 kb
Host smart-05d4dc49-579a-466e-95b0-92e8be9f6c1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794361102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.1794361102
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.694030806
Short name T189
Test name
Test status
Simulation time 132436262 ps
CPU time 10.12 seconds
Started Apr 02 12:37:56 PM PDT 24
Finished Apr 02 12:38:06 PM PDT 24
Peak memory 240248 kb
Host smart-8796ccd8-7da8-4561-96d6-e46f6fe0d927
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=694030806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.694030806
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2105611798
Short name T765
Test name
Test status
Simulation time 14363191 ps
CPU time 1.76 seconds
Started Apr 02 12:37:59 PM PDT 24
Finished Apr 02 12:38:01 PM PDT 24
Peak memory 236624 kb
Host smart-cc787583-fe18-44d7-a780-6af847bbe6e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2105611798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.2105611798
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1163505532
Short name T798
Test name
Test status
Simulation time 354557411 ps
CPU time 10.85 seconds
Started Apr 02 12:37:56 PM PDT 24
Finished Apr 02 12:38:07 PM PDT 24
Peak memory 243996 kb
Host smart-a4bcb255-6a04-4e9d-bc24-15a7c7a16fdb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1163505532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.1163505532
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.467077964
Short name T119
Test name
Test status
Simulation time 3920793924 ps
CPU time 330.17 seconds
Started Apr 02 12:37:59 PM PDT 24
Finished Apr 02 12:43:30 PM PDT 24
Peak memory 265264 kb
Host smart-01f59692-549e-4599-839c-9dd83385a881
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467077964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.467077964
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.4035007296
Short name T739
Test name
Test status
Simulation time 172955327 ps
CPU time 8.53 seconds
Started Apr 02 12:37:59 PM PDT 24
Finished Apr 02 12:38:08 PM PDT 24
Peak memory 249564 kb
Host smart-65050c89-597b-4c31-a2ab-bd5fc25d6053
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4035007296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.4035007296
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2457237014
Short name T353
Test name
Test status
Simulation time 63093658 ps
CPU time 9.44 seconds
Started Apr 02 12:38:08 PM PDT 24
Finished Apr 02 12:38:18 PM PDT 24
Peak memory 256696 kb
Host smart-4a122cc1-49a0-4fef-ace7-d7672dd03a42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457237014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.2457237014
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.2850100871
Short name T771
Test name
Test status
Simulation time 227601758 ps
CPU time 5.21 seconds
Started Apr 02 12:38:10 PM PDT 24
Finished Apr 02 12:38:15 PM PDT 24
Peak memory 240208 kb
Host smart-b2e7c83d-6cab-466b-b6f6-ad6b4668c96a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2850100871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.2850100871
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3414760385
Short name T751
Test name
Test status
Simulation time 17041788 ps
CPU time 1.34 seconds
Started Apr 02 12:38:09 PM PDT 24
Finished Apr 02 12:38:11 PM PDT 24
Peak memory 236660 kb
Host smart-d61e1b82-f5d3-4450-a7e0-d43f1f2f285c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3414760385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.3414760385
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3551583104
Short name T786
Test name
Test status
Simulation time 248954947 ps
CPU time 17.03 seconds
Started Apr 02 12:38:09 PM PDT 24
Finished Apr 02 12:38:26 PM PDT 24
Peak memory 243972 kb
Host smart-7eaf0f05-0b24-4172-a62b-070b6b3247ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3551583104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.3551583104
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.548614673
Short name T821
Test name
Test status
Simulation time 116571843 ps
CPU time 6.99 seconds
Started Apr 02 12:38:06 PM PDT 24
Finished Apr 02 12:38:13 PM PDT 24
Peak memory 248604 kb
Host smart-69ce55d3-4d6f-4c8f-979e-e3b154b78f4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=548614673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.548614673
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2890950178
Short name T735
Test name
Test status
Simulation time 153955711 ps
CPU time 2.57 seconds
Started Apr 02 12:38:16 PM PDT 24
Finished Apr 02 12:38:19 PM PDT 24
Peak memory 236632 kb
Host smart-8dcc199e-6c46-4df1-9288-05c064aeb017
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2890950178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2890950178
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1675761793
Short name T737
Test name
Test status
Simulation time 101307093 ps
CPU time 8.49 seconds
Started Apr 02 12:38:08 PM PDT 24
Finished Apr 02 12:38:17 PM PDT 24
Peak memory 238776 kb
Host smart-513c865f-49ac-4ea4-bed3-d957d3c3bab4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675761793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.1675761793
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.3289559507
Short name T813
Test name
Test status
Simulation time 383207465 ps
CPU time 7.22 seconds
Started Apr 02 12:38:10 PM PDT 24
Finished Apr 02 12:38:17 PM PDT 24
Peak memory 240204 kb
Host smart-b32f96d3-fb62-4215-8b6e-a4b837320a78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3289559507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.3289559507
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.1073844187
Short name T723
Test name
Test status
Simulation time 8601366 ps
CPU time 1.36 seconds
Started Apr 02 12:38:09 PM PDT 24
Finished Apr 02 12:38:11 PM PDT 24
Peak memory 235820 kb
Host smart-403b8ee8-01a0-4ed1-a86c-82a850514aed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1073844187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.1073844187
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3916737253
Short name T804
Test name
Test status
Simulation time 165377197 ps
CPU time 19.01 seconds
Started Apr 02 12:38:10 PM PDT 24
Finished Apr 02 12:38:29 PM PDT 24
Peak memory 243928 kb
Host smart-cbdac5a5-46d1-4599-9061-ed275e0462e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3916737253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.3916737253
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.1131779728
Short name T830
Test name
Test status
Simulation time 358333593 ps
CPU time 7.84 seconds
Started Apr 02 12:38:10 PM PDT 24
Finished Apr 02 12:38:18 PM PDT 24
Peak memory 252316 kb
Host smart-4ede907a-82c9-4bf2-9940-34c526f4389f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1131779728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.1131779728
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3726150627
Short name T745
Test name
Test status
Simulation time 148416299 ps
CPU time 12.43 seconds
Started Apr 02 12:38:07 PM PDT 24
Finished Apr 02 12:38:20 PM PDT 24
Peak memory 250644 kb
Host smart-6af964fd-cea1-4127-8432-ab69a86ec228
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726150627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.3726150627
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.650070130
Short name T825
Test name
Test status
Simulation time 815624932 ps
CPU time 7.76 seconds
Started Apr 02 12:38:07 PM PDT 24
Finished Apr 02 12:38:15 PM PDT 24
Peak memory 235728 kb
Host smart-61ab6a84-0bd3-4666-b072-3593a3de057f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=650070130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.650070130
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.9915198
Short name T753
Test name
Test status
Simulation time 12778588 ps
CPU time 1.33 seconds
Started Apr 02 12:38:07 PM PDT 24
Finished Apr 02 12:38:09 PM PDT 24
Peak memory 236660 kb
Host smart-1ea7d546-2f9c-4b6d-ba65-931e907fc01f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=9915198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.9915198
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.769915023
Short name T832
Test name
Test status
Simulation time 499476739 ps
CPU time 32.69 seconds
Started Apr 02 12:38:10 PM PDT 24
Finished Apr 02 12:38:43 PM PDT 24
Peak memory 243920 kb
Host smart-5295a34b-a200-4e15-8a2d-96076037a4c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=769915023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_out
standing.769915023
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2876859702
Short name T115
Test name
Test status
Simulation time 2799733952 ps
CPU time 90.46 seconds
Started Apr 02 12:38:05 PM PDT 24
Finished Apr 02 12:39:36 PM PDT 24
Peak memory 256968 kb
Host smart-8f7147b9-3e8c-475f-8751-cf200932ab1a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2876859702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.2876859702
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.4016631202
Short name T749
Test name
Test status
Simulation time 1238984836 ps
CPU time 19.77 seconds
Started Apr 02 12:38:05 PM PDT 24
Finished Apr 02 12:38:24 PM PDT 24
Peak memory 252936 kb
Host smart-d0e9462a-4843-478f-ae7b-6f4937987950
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4016631202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.4016631202
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2923188681
Short name T802
Test name
Test status
Simulation time 41499181 ps
CPU time 5.53 seconds
Started Apr 02 12:38:16 PM PDT 24
Finished Apr 02 12:38:22 PM PDT 24
Peak memory 240564 kb
Host smart-20a12933-4101-49f6-967b-9892cc6d28ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923188681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.2923188681
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.865308772
Short name T191
Test name
Test status
Simulation time 62408821 ps
CPU time 5.69 seconds
Started Apr 02 12:38:16 PM PDT 24
Finished Apr 02 12:38:22 PM PDT 24
Peak memory 240256 kb
Host smart-a79bab42-71ea-4e8f-84e6-61a8e0077515
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=865308772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.865308772
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3089170025
Short name T740
Test name
Test status
Simulation time 16177057 ps
CPU time 1.3 seconds
Started Apr 02 12:38:10 PM PDT 24
Finished Apr 02 12:38:11 PM PDT 24
Peak memory 235756 kb
Host smart-bc7bdce7-f73d-48af-ab5d-9ab244455aab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3089170025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.3089170025
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.3546889601
Short name T791
Test name
Test status
Simulation time 505860629 ps
CPU time 9.91 seconds
Started Apr 02 12:38:15 PM PDT 24
Finished Apr 02 12:38:24 PM PDT 24
Peak memory 240240 kb
Host smart-344dcb9b-f059-4ba9-a297-ea2a284518a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3546889601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.3546889601
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.4197304013
Short name T141
Test name
Test status
Simulation time 8190105109 ps
CPU time 558.7 seconds
Started Apr 02 12:38:08 PM PDT 24
Finished Apr 02 12:47:28 PM PDT 24
Peak memory 265124 kb
Host smart-896db807-3b00-433d-b454-8bb49bf517e8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197304013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.4197304013
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1768065780
Short name T754
Test name
Test status
Simulation time 71687466 ps
CPU time 8.75 seconds
Started Apr 02 12:38:16 PM PDT 24
Finished Apr 02 12:38:25 PM PDT 24
Peak memory 247612 kb
Host smart-74dc29b7-3d59-4d9e-8ec8-d08ef79c77fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1768065780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.1768065780
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2216517099
Short name T354
Test name
Test status
Simulation time 289793700 ps
CPU time 5.35 seconds
Started Apr 02 12:38:13 PM PDT 24
Finished Apr 02 12:38:19 PM PDT 24
Peak memory 240380 kb
Host smart-c7b9e43a-b47d-418b-97fb-27fdae09c2b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216517099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.2216517099
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.2841463393
Short name T816
Test name
Test status
Simulation time 359319561 ps
CPU time 4.84 seconds
Started Apr 02 12:38:13 PM PDT 24
Finished Apr 02 12:38:17 PM PDT 24
Peak memory 235548 kb
Host smart-1971afb0-4ebc-489b-8296-9d3a5818ecca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2841463393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.2841463393
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.3302900563
Short name T801
Test name
Test status
Simulation time 10996614 ps
CPU time 1.37 seconds
Started Apr 02 12:38:11 PM PDT 24
Finished Apr 02 12:38:13 PM PDT 24
Peak memory 236664 kb
Host smart-1ecf65b4-0d60-49ae-855d-cb9403198a61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3302900563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.3302900563
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.1362299865
Short name T820
Test name
Test status
Simulation time 596595465 ps
CPU time 39.3 seconds
Started Apr 02 12:38:16 PM PDT 24
Finished Apr 02 12:38:56 PM PDT 24
Peak memory 243952 kb
Host smart-5f6e756e-be8a-49a5-98a3-b8203fb8847f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1362299865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.1362299865
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3855290755
Short name T123
Test name
Test status
Simulation time 1685260102 ps
CPU time 105.63 seconds
Started Apr 02 12:38:11 PM PDT 24
Finished Apr 02 12:39:57 PM PDT 24
Peak memory 265056 kb
Host smart-9c731747-b7ae-4315-9c11-ddc1ef3e1299
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3855290755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.3855290755
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1158335717
Short name T121
Test name
Test status
Simulation time 5494226369 ps
CPU time 282.14 seconds
Started Apr 02 12:38:18 PM PDT 24
Finished Apr 02 12:43:00 PM PDT 24
Peak memory 268768 kb
Host smart-d3332e12-8d99-44d6-b727-21ddbb9247ac
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158335717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.1158335717
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.709415032
Short name T799
Test name
Test status
Simulation time 17377145 ps
CPU time 2.62 seconds
Started Apr 02 12:38:11 PM PDT 24
Finished Apr 02 12:38:14 PM PDT 24
Peak memory 247628 kb
Host smart-24947260-cb55-4262-a0a5-4da7f8ea2401
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=709415032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.709415032
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1045465252
Short name T350
Test name
Test status
Simulation time 277842143 ps
CPU time 9.59 seconds
Started Apr 02 12:38:12 PM PDT 24
Finished Apr 02 12:38:22 PM PDT 24
Peak memory 240396 kb
Host smart-1d33e244-f742-40e9-a715-75eb90f7e45e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045465252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.1045465252
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3468068068
Short name T810
Test name
Test status
Simulation time 150474930 ps
CPU time 4.71 seconds
Started Apr 02 12:38:13 PM PDT 24
Finished Apr 02 12:38:17 PM PDT 24
Peak memory 236552 kb
Host smart-9e669fcd-e6b6-4484-ae3b-515da11b1c0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3468068068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.3468068068
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.412453462
Short name T726
Test name
Test status
Simulation time 8249602 ps
CPU time 1.36 seconds
Started Apr 02 12:38:11 PM PDT 24
Finished Apr 02 12:38:12 PM PDT 24
Peak memory 235804 kb
Host smart-796323a4-1afb-460b-b9f6-1355744bdbdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=412453462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.412453462
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1492722926
Short name T729
Test name
Test status
Simulation time 253715106 ps
CPU time 17.55 seconds
Started Apr 02 12:38:13 PM PDT 24
Finished Apr 02 12:38:30 PM PDT 24
Peak memory 244824 kb
Host smart-78de361b-e55e-42fe-9f37-2cd1086cf58c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1492722926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.1492722926
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3974935211
Short name T137
Test name
Test status
Simulation time 2412025717 ps
CPU time 162.01 seconds
Started Apr 02 12:38:11 PM PDT 24
Finished Apr 02 12:40:53 PM PDT 24
Peak memory 256980 kb
Host smart-d7356735-e63a-4c7a-8501-f2645dee9166
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3974935211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.3974935211
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.500076585
Short name T357
Test name
Test status
Simulation time 8385079408 ps
CPU time 275.45 seconds
Started Apr 02 12:38:13 PM PDT 24
Finished Apr 02 12:42:49 PM PDT 24
Peak memory 265220 kb
Host smart-4e0bbccd-cedc-415f-b400-01e6a1c63c27
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500076585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.500076585
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.3031129094
Short name T784
Test name
Test status
Simulation time 982848178 ps
CPU time 17.07 seconds
Started Apr 02 12:38:14 PM PDT 24
Finished Apr 02 12:38:32 PM PDT 24
Peak memory 253024 kb
Host smart-e172f655-698a-44b0-b0d8-a4bbd1729043
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3031129094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.3031129094
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.2610986927
Short name T159
Test name
Test status
Simulation time 49701087 ps
CPU time 2.59 seconds
Started Apr 02 12:38:11 PM PDT 24
Finished Apr 02 12:38:13 PM PDT 24
Peak memory 236804 kb
Host smart-1630f91a-491a-45d3-96b1-78818b51e4e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2610986927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.2610986927
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.546841672
Short name T356
Test name
Test status
Simulation time 75582996 ps
CPU time 10.99 seconds
Started Apr 02 12:38:18 PM PDT 24
Finished Apr 02 12:38:29 PM PDT 24
Peak memory 256772 kb
Host smart-49f8d443-5341-47d7-9063-842f794a58b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546841672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.alert_handler_csr_mem_rw_with_rand_reset.546841672
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3996231458
Short name T744
Test name
Test status
Simulation time 171155044 ps
CPU time 3.23 seconds
Started Apr 02 12:38:12 PM PDT 24
Finished Apr 02 12:38:15 PM PDT 24
Peak memory 236560 kb
Host smart-9ebb5060-0322-42d0-b7fc-17b7d9216cea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3996231458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.3996231458
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.3044776467
Short name T345
Test name
Test status
Simulation time 17201663 ps
CPU time 1.38 seconds
Started Apr 02 12:38:11 PM PDT 24
Finished Apr 02 12:38:12 PM PDT 24
Peak memory 234764 kb
Host smart-9dd46397-4526-4bfa-8bb9-d9569a5056a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3044776467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.3044776467
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.861084138
Short name T803
Test name
Test status
Simulation time 1046243752 ps
CPU time 18.48 seconds
Started Apr 02 12:38:18 PM PDT 24
Finished Apr 02 12:38:37 PM PDT 24
Peak memory 243968 kb
Host smart-edbc38a7-746f-4996-a3d0-f6f95b8f01a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=861084138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_out
standing.861084138
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.91536531
Short name T127
Test name
Test status
Simulation time 18183590318 ps
CPU time 658.73 seconds
Started Apr 02 12:38:12 PM PDT 24
Finished Apr 02 12:49:11 PM PDT 24
Peak memory 273352 kb
Host smart-18de35b1-bce0-400b-a11e-1766cfc3460e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91536531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.91536531
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.1044435687
Short name T797
Test name
Test status
Simulation time 1080952367 ps
CPU time 19.86 seconds
Started Apr 02 12:38:16 PM PDT 24
Finished Apr 02 12:38:36 PM PDT 24
Peak memory 248072 kb
Host smart-58dfc43d-8e78-439b-bae8-6ff7aac97a85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1044435687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.1044435687
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1140839282
Short name T730
Test name
Test status
Simulation time 35842072 ps
CPU time 5.95 seconds
Started Apr 02 12:38:18 PM PDT 24
Finished Apr 02 12:38:25 PM PDT 24
Peak memory 240380 kb
Host smart-215bc8ac-7599-47bb-9bd6-89713a70e51d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140839282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.1140839282
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3265187669
Short name T741
Test name
Test status
Simulation time 19535300 ps
CPU time 3.44 seconds
Started Apr 02 12:38:16 PM PDT 24
Finished Apr 02 12:38:20 PM PDT 24
Peak memory 235660 kb
Host smart-9e3e5ab9-a170-4bb9-b087-cdfa6e9bdf40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3265187669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.3265187669
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.2406242238
Short name T812
Test name
Test status
Simulation time 8013828 ps
CPU time 1.43 seconds
Started Apr 02 12:38:29 PM PDT 24
Finished Apr 02 12:38:31 PM PDT 24
Peak memory 235820 kb
Host smart-e88a421f-cf1d-4288-b9d7-d440df44ec4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2406242238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.2406242238
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3659808877
Short name T809
Test name
Test status
Simulation time 1053626773 ps
CPU time 33 seconds
Started Apr 02 12:38:28 PM PDT 24
Finished Apr 02 12:39:01 PM PDT 24
Peak memory 240228 kb
Host smart-b633678c-8b5b-4c78-840b-ea624e47fef7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3659808877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.3659808877
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1272584234
Short name T125
Test name
Test status
Simulation time 2295643587 ps
CPU time 293.72 seconds
Started Apr 02 12:38:12 PM PDT 24
Finished Apr 02 12:43:06 PM PDT 24
Peak memory 265140 kb
Host smart-8ac91fa0-6f30-478b-afc1-0e67206b16ff
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272584234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.1272584234
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.1758777167
Short name T826
Test name
Test status
Simulation time 1431072418 ps
CPU time 13.43 seconds
Started Apr 02 12:38:17 PM PDT 24
Finished Apr 02 12:38:31 PM PDT 24
Peak memory 247512 kb
Host smart-598939e1-e798-414d-8921-abe12ae333ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1758777167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.1758777167
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.315463719
Short name T829
Test name
Test status
Simulation time 231519741 ps
CPU time 7.59 seconds
Started Apr 02 12:38:17 PM PDT 24
Finished Apr 02 12:38:24 PM PDT 24
Peak memory 240548 kb
Host smart-b4087ecf-a3ae-42a0-b37d-3d44d029ecdf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315463719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.alert_handler_csr_mem_rw_with_rand_reset.315463719
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2963432206
Short name T794
Test name
Test status
Simulation time 35546470 ps
CPU time 5.67 seconds
Started Apr 02 12:38:19 PM PDT 24
Finished Apr 02 12:38:25 PM PDT 24
Peak memory 240248 kb
Host smart-8f3b4c93-b394-4a16-a70a-7a76632f1ba8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2963432206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.2963432206
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.1462381216
Short name T773
Test name
Test status
Simulation time 7646767 ps
CPU time 1.48 seconds
Started Apr 02 12:38:17 PM PDT 24
Finished Apr 02 12:38:19 PM PDT 24
Peak memory 235792 kb
Host smart-4857132e-010d-4609-9cb8-61357f80e233
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1462381216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.1462381216
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1144914214
Short name T192
Test name
Test status
Simulation time 1647683345 ps
CPU time 20.78 seconds
Started Apr 02 12:38:14 PM PDT 24
Finished Apr 02 12:38:35 PM PDT 24
Peak memory 248476 kb
Host smart-d0c3bfe1-c5db-4547-a0af-b05a36461854
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1144914214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.1144914214
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.2750260394
Short name T148
Test name
Test status
Simulation time 1751436517 ps
CPU time 120.53 seconds
Started Apr 02 12:38:28 PM PDT 24
Finished Apr 02 12:40:29 PM PDT 24
Peak memory 264372 kb
Host smart-d7fd4d51-ec1e-439a-974a-9e9755e7fbee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2750260394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.2750260394
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1529269144
Short name T824
Test name
Test status
Simulation time 24015113689 ps
CPU time 276.51 seconds
Started Apr 02 12:38:17 PM PDT 24
Finished Apr 02 12:42:54 PM PDT 24
Peak memory 265392 kb
Host smart-624deae9-8999-46f2-b71e-0630c137c605
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529269144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1529269144
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1345148104
Short name T811
Test name
Test status
Simulation time 182483057 ps
CPU time 9.81 seconds
Started Apr 02 12:38:14 PM PDT 24
Finished Apr 02 12:38:24 PM PDT 24
Peak memory 248408 kb
Host smart-5dc60ab1-f6d2-4a07-be88-2b5907b97896
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1345148104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.1345148104
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1751574680
Short name T780
Test name
Test status
Simulation time 506764451 ps
CPU time 10.61 seconds
Started Apr 02 12:38:28 PM PDT 24
Finished Apr 02 12:38:39 PM PDT 24
Peak memory 240392 kb
Host smart-5c3fb3ae-8417-4034-a26a-feb59dedacfb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751574680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.1751574680
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2439398957
Short name T748
Test name
Test status
Simulation time 37778609 ps
CPU time 4.93 seconds
Started Apr 02 12:38:31 PM PDT 24
Finished Apr 02 12:38:37 PM PDT 24
Peak memory 235620 kb
Host smart-7cae8c46-85c1-4cf7-bd29-c7069ba9967a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2439398957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.2439398957
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.468069898
Short name T343
Test name
Test status
Simulation time 14591483 ps
CPU time 1.53 seconds
Started Apr 02 12:38:17 PM PDT 24
Finished Apr 02 12:38:18 PM PDT 24
Peak memory 235788 kb
Host smart-f1c9dc73-0c25-449a-b430-b0ee92adb956
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=468069898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.468069898
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3562194768
Short name T762
Test name
Test status
Simulation time 2810579782 ps
CPU time 43.26 seconds
Started Apr 02 12:38:17 PM PDT 24
Finished Apr 02 12:39:01 PM PDT 24
Peak memory 244912 kb
Host smart-95d15e33-4c2d-4344-b56b-c0f63e9c4e24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3562194768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.3562194768
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3505722562
Short name T143
Test name
Test status
Simulation time 2962764719 ps
CPU time 110.62 seconds
Started Apr 02 12:38:15 PM PDT 24
Finished Apr 02 12:40:05 PM PDT 24
Peak memory 265116 kb
Host smart-972c66c8-41f7-456d-9e9c-1bda688d9f7a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3505722562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.3505722562
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3879493620
Short name T358
Test name
Test status
Simulation time 2268844444 ps
CPU time 294.9 seconds
Started Apr 02 12:38:28 PM PDT 24
Finished Apr 02 12:43:23 PM PDT 24
Peak memory 265196 kb
Host smart-184b82c9-5f21-4751-a574-eb9e8a7993e8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879493620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.3879493620
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.190566096
Short name T759
Test name
Test status
Simulation time 186633231 ps
CPU time 11.87 seconds
Started Apr 02 12:38:20 PM PDT 24
Finished Apr 02 12:38:32 PM PDT 24
Peak memory 252228 kb
Host smart-fd4e6178-d983-4a90-a5f4-72e58c8c1fb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=190566096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.190566096
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.688787475
Short name T790
Test name
Test status
Simulation time 27995069823 ps
CPU time 128.22 seconds
Started Apr 02 12:38:03 PM PDT 24
Finished Apr 02 12:40:11 PM PDT 24
Peak memory 240328 kb
Host smart-052f87ce-6197-4d10-9708-ba6e98074474
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=688787475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.688787475
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1471952421
Short name T728
Test name
Test status
Simulation time 4363909193 ps
CPU time 259.88 seconds
Started Apr 02 12:37:55 PM PDT 24
Finished Apr 02 12:42:15 PM PDT 24
Peak memory 240336 kb
Host smart-8777878f-42e9-421d-b936-d0bc90ff65d7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1471952421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.1471952421
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1600592060
Short name T781
Test name
Test status
Simulation time 26216353 ps
CPU time 3.68 seconds
Started Apr 02 12:38:00 PM PDT 24
Finished Apr 02 12:38:03 PM PDT 24
Peak memory 240136 kb
Host smart-f17fb06d-e72f-4da2-8b0c-3c1060a1d455
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1600592060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.1600592060
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.3765204264
Short name T793
Test name
Test status
Simulation time 30301432 ps
CPU time 3.51 seconds
Started Apr 02 12:37:59 PM PDT 24
Finished Apr 02 12:38:03 PM PDT 24
Peak memory 236544 kb
Host smart-6230ff4a-518e-4b8b-854d-84492594fc85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3765204264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.3765204264
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.3852248528
Short name T349
Test name
Test status
Simulation time 6391476 ps
CPU time 1.42 seconds
Started Apr 02 12:38:03 PM PDT 24
Finished Apr 02 12:38:05 PM PDT 24
Peak memory 236636 kb
Host smart-3cd4793b-d686-4f43-9966-22772fe84964
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3852248528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.3852248528
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.379738752
Short name T789
Test name
Test status
Simulation time 194584330 ps
CPU time 24.41 seconds
Started Apr 02 12:37:57 PM PDT 24
Finished Apr 02 12:38:21 PM PDT 24
Peak memory 244872 kb
Host smart-f6ea894f-6c3d-4224-9b9b-9408ea4e8f96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=379738752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outs
tanding.379738752
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.1126728408
Short name T246
Test name
Test status
Simulation time 280366974 ps
CPU time 11.02 seconds
Started Apr 02 12:38:02 PM PDT 24
Finished Apr 02 12:38:13 PM PDT 24
Peak memory 248732 kb
Host smart-8fb1885e-c8cb-4358-9e82-510ed9853e66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1126728408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.1126728408
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.575067268
Short name T796
Test name
Test status
Simulation time 10868453 ps
CPU time 1.32 seconds
Started Apr 02 12:38:31 PM PDT 24
Finished Apr 02 12:38:34 PM PDT 24
Peak memory 235708 kb
Host smart-e7d516f3-3c91-4f2b-9325-a2072d68d965
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=575067268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.575067268
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1048013268
Short name T819
Test name
Test status
Simulation time 12253419 ps
CPU time 1.28 seconds
Started Apr 02 12:38:14 PM PDT 24
Finished Apr 02 12:38:15 PM PDT 24
Peak memory 236656 kb
Host smart-8f64cc89-7a1f-4f43-b0b1-a3caa2e5a2a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1048013268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.1048013268
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.3613795212
Short name T153
Test name
Test status
Simulation time 7864410 ps
CPU time 1.38 seconds
Started Apr 02 12:38:23 PM PDT 24
Finished Apr 02 12:38:24 PM PDT 24
Peak memory 235800 kb
Host smart-893e4483-f5ee-4c4d-a125-ea7149a5686a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3613795212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.3613795212
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.678785669
Short name T814
Test name
Test status
Simulation time 20770435 ps
CPU time 1.23 seconds
Started Apr 02 12:38:15 PM PDT 24
Finished Apr 02 12:38:16 PM PDT 24
Peak memory 236512 kb
Host smart-03c746d2-1fbd-4043-a6bc-4ae63b9ad06c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=678785669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.678785669
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1584096953
Short name T817
Test name
Test status
Simulation time 46351080 ps
CPU time 1.66 seconds
Started Apr 02 12:38:17 PM PDT 24
Finished Apr 02 12:38:19 PM PDT 24
Peak memory 236668 kb
Host smart-d71acb04-060a-4ba3-ac72-83a021897ef7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1584096953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.1584096953
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3150421090
Short name T783
Test name
Test status
Simulation time 13558413 ps
CPU time 1.38 seconds
Started Apr 02 12:38:17 PM PDT 24
Finished Apr 02 12:38:18 PM PDT 24
Peak memory 235776 kb
Host smart-a63caaab-0fca-4da5-95ed-553099e91350
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3150421090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.3150421090
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3377188769
Short name T776
Test name
Test status
Simulation time 17296939 ps
CPU time 1.36 seconds
Started Apr 02 12:38:31 PM PDT 24
Finished Apr 02 12:38:34 PM PDT 24
Peak memory 236572 kb
Host smart-7522d0de-fb16-408c-9fe5-2f71bfb5151a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3377188769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.3377188769
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.216260093
Short name T344
Test name
Test status
Simulation time 10034590 ps
CPU time 1.65 seconds
Started Apr 02 12:38:18 PM PDT 24
Finished Apr 02 12:38:20 PM PDT 24
Peak memory 236664 kb
Host smart-ce23397b-5e49-4471-a9a2-f999a0713088
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=216260093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.216260093
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.3690787023
Short name T767
Test name
Test status
Simulation time 6613921 ps
CPU time 1.41 seconds
Started Apr 02 12:38:17 PM PDT 24
Finished Apr 02 12:38:18 PM PDT 24
Peak memory 235712 kb
Host smart-29cc6791-afd1-496a-b71e-5b59bc67764c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3690787023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.3690787023
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3018760832
Short name T743
Test name
Test status
Simulation time 7519189334 ps
CPU time 237.58 seconds
Started Apr 02 12:38:02 PM PDT 24
Finished Apr 02 12:41:59 PM PDT 24
Peak memory 240528 kb
Host smart-85130300-fa3e-4424-9027-94769d9d1143
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3018760832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.3018760832
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.2506428578
Short name T764
Test name
Test status
Simulation time 1638138954 ps
CPU time 199.94 seconds
Started Apr 02 12:37:59 PM PDT 24
Finished Apr 02 12:41:19 PM PDT 24
Peak memory 240228 kb
Host smart-e2843497-3d7b-497d-8bc8-7b0e938513ae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2506428578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.2506428578
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.303813980
Short name T193
Test name
Test status
Simulation time 84485337 ps
CPU time 3.66 seconds
Started Apr 02 12:38:02 PM PDT 24
Finished Apr 02 12:38:06 PM PDT 24
Peak memory 240252 kb
Host smart-30a6c3d5-0fc2-446a-a98e-928ae6fdd436
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=303813980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.303813980
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2537659516
Short name T352
Test name
Test status
Simulation time 46097043 ps
CPU time 8 seconds
Started Apr 02 12:38:01 PM PDT 24
Finished Apr 02 12:38:09 PM PDT 24
Peak memory 248588 kb
Host smart-2c6427a5-7fd1-459a-a84b-7d0d90302080
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537659516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.2537659516
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2993856969
Short name T724
Test name
Test status
Simulation time 228611522 ps
CPU time 8.58 seconds
Started Apr 02 12:38:03 PM PDT 24
Finished Apr 02 12:38:12 PM PDT 24
Peak memory 235676 kb
Host smart-da4e9cb7-4d24-44be-b918-ede50c58475d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2993856969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.2993856969
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1260438333
Short name T772
Test name
Test status
Simulation time 29172404 ps
CPU time 1.29 seconds
Started Apr 02 12:38:02 PM PDT 24
Finished Apr 02 12:38:03 PM PDT 24
Peak memory 236660 kb
Host smart-0ee2032b-5d3f-49da-9e5e-462b1a9eb658
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1260438333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.1260438333
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.3795820458
Short name T190
Test name
Test status
Simulation time 335516452 ps
CPU time 22.43 seconds
Started Apr 02 12:38:01 PM PDT 24
Finished Apr 02 12:38:24 PM PDT 24
Peak memory 239736 kb
Host smart-fcd5cc6d-5b97-4c5b-a2ee-e658b9cc5339
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3795820458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.3795820458
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.3279935264
Short name T146
Test name
Test status
Simulation time 4749152990 ps
CPU time 161.72 seconds
Started Apr 02 12:37:54 PM PDT 24
Finished Apr 02 12:40:36 PM PDT 24
Peak memory 256968 kb
Host smart-056976c7-3a33-4992-968b-75318ea380ba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3279935264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.3279935264
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3016009354
Short name T722
Test name
Test status
Simulation time 179665069 ps
CPU time 7.22 seconds
Started Apr 02 12:38:00 PM PDT 24
Finished Apr 02 12:38:07 PM PDT 24
Peak memory 248336 kb
Host smart-392a92a8-f54f-4614-95d7-6058b283c425
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3016009354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.3016009354
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.3250701500
Short name T154
Test name
Test status
Simulation time 12141763 ps
CPU time 1.71 seconds
Started Apr 02 12:38:18 PM PDT 24
Finished Apr 02 12:38:21 PM PDT 24
Peak memory 235712 kb
Host smart-ddf3248a-e7a4-4c4a-86e4-d2e87636e2d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3250701500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.3250701500
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3658603586
Short name T815
Test name
Test status
Simulation time 6715263 ps
CPU time 1.38 seconds
Started Apr 02 12:38:21 PM PDT 24
Finished Apr 02 12:38:23 PM PDT 24
Peak memory 235820 kb
Host smart-d3a80af7-0ce4-447a-9e73-79a0860225fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3658603586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.3658603586
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3007241298
Short name T758
Test name
Test status
Simulation time 6413951 ps
CPU time 1.39 seconds
Started Apr 02 12:38:21 PM PDT 24
Finished Apr 02 12:38:23 PM PDT 24
Peak memory 234720 kb
Host smart-8d8a7436-6d41-4371-952f-324d85d3fe21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3007241298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.3007241298
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.1140364652
Short name T818
Test name
Test status
Simulation time 6746411 ps
CPU time 1.44 seconds
Started Apr 02 12:38:15 PM PDT 24
Finished Apr 02 12:38:16 PM PDT 24
Peak memory 235820 kb
Host smart-bad4ab31-5614-45f1-853a-3e471c9c854e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1140364652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.1140364652
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.3175353618
Short name T761
Test name
Test status
Simulation time 11885943 ps
CPU time 1.31 seconds
Started Apr 02 12:38:14 PM PDT 24
Finished Apr 02 12:38:15 PM PDT 24
Peak memory 236628 kb
Host smart-1c549fa3-8561-4793-b374-5abb90c6b541
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3175353618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.3175353618
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.1136318093
Short name T756
Test name
Test status
Simulation time 10373698 ps
CPU time 1.28 seconds
Started Apr 02 12:38:29 PM PDT 24
Finished Apr 02 12:38:30 PM PDT 24
Peak memory 235788 kb
Host smart-eff88378-de1f-4f91-b0db-3d69e8a56096
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1136318093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.1136318093
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.4084460643
Short name T721
Test name
Test status
Simulation time 22693245 ps
CPU time 1.35 seconds
Started Apr 02 12:38:16 PM PDT 24
Finished Apr 02 12:38:18 PM PDT 24
Peak memory 235712 kb
Host smart-f1a5a036-12ef-4a15-8b8e-1ce532f6c0d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4084460643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.4084460643
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1957194674
Short name T727
Test name
Test status
Simulation time 26203181 ps
CPU time 1.44 seconds
Started Apr 02 12:38:31 PM PDT 24
Finished Apr 02 12:38:34 PM PDT 24
Peak memory 236572 kb
Host smart-4752be10-116b-4f07-a5f6-5213660c2782
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1957194674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.1957194674
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.806132684
Short name T827
Test name
Test status
Simulation time 9096661 ps
CPU time 1.57 seconds
Started Apr 02 12:38:17 PM PDT 24
Finished Apr 02 12:38:19 PM PDT 24
Peak memory 234800 kb
Host smart-dd15258d-d1d5-4588-b7ca-fc2fbedb3a9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=806132684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.806132684
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.1069570514
Short name T778
Test name
Test status
Simulation time 7306840 ps
CPU time 1.43 seconds
Started Apr 02 12:38:14 PM PDT 24
Finished Apr 02 12:38:15 PM PDT 24
Peak memory 234748 kb
Host smart-8e9dba1e-0a8f-4ed3-b6d2-bfe49ef37ae4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1069570514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.1069570514
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.4266621827
Short name T805
Test name
Test status
Simulation time 6852190549 ps
CPU time 252.11 seconds
Started Apr 02 12:37:58 PM PDT 24
Finished Apr 02 12:42:10 PM PDT 24
Peak memory 240324 kb
Host smart-c08bb12c-a65c-4222-ad1e-e5d75ea45fd1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4266621827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.4266621827
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1232736804
Short name T806
Test name
Test status
Simulation time 1724426916 ps
CPU time 201.06 seconds
Started Apr 02 12:38:02 PM PDT 24
Finished Apr 02 12:41:23 PM PDT 24
Peak memory 240252 kb
Host smart-749c1733-a009-4a04-b06f-8b7b9615a367
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1232736804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.1232736804
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.1556402119
Short name T187
Test name
Test status
Simulation time 142789013 ps
CPU time 6.45 seconds
Started Apr 02 12:38:00 PM PDT 24
Finished Apr 02 12:38:07 PM PDT 24
Peak memory 240208 kb
Host smart-86a75f75-6e65-48c1-8a09-4e7a372b215a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1556402119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.1556402119
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.485270853
Short name T351
Test name
Test status
Simulation time 234186203 ps
CPU time 10.6 seconds
Started Apr 02 12:38:02 PM PDT 24
Finished Apr 02 12:38:12 PM PDT 24
Peak memory 256740 kb
Host smart-133deea3-4120-4747-8297-f5352c354bca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485270853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.alert_handler_csr_mem_rw_with_rand_reset.485270853
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1434053190
Short name T763
Test name
Test status
Simulation time 34220534 ps
CPU time 5.68 seconds
Started Apr 02 12:37:58 PM PDT 24
Finished Apr 02 12:38:04 PM PDT 24
Peak memory 236560 kb
Host smart-84f58f8f-9aac-4eab-abe1-5525252c8c53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1434053190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.1434053190
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.4112909642
Short name T755
Test name
Test status
Simulation time 9545795 ps
CPU time 1.63 seconds
Started Apr 02 12:38:01 PM PDT 24
Finished Apr 02 12:38:02 PM PDT 24
Peak memory 235776 kb
Host smart-f8f95659-5073-4640-84c0-9397fa2d3e87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4112909642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.4112909642
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.2982368931
Short name T169
Test name
Test status
Simulation time 364492317 ps
CPU time 25.62 seconds
Started Apr 02 12:37:58 PM PDT 24
Finished Apr 02 12:38:24 PM PDT 24
Peak memory 244836 kb
Host smart-47668f39-e523-4c18-9b5f-b957dac55d90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2982368931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.2982368931
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.682043769
Short name T718
Test name
Test status
Simulation time 165967588 ps
CPU time 5.99 seconds
Started Apr 02 12:38:01 PM PDT 24
Finished Apr 02 12:38:07 PM PDT 24
Peak memory 248560 kb
Host smart-bb7cee9c-75bc-4afe-ab89-744a11ae21d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=682043769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.682043769
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.592284809
Short name T774
Test name
Test status
Simulation time 6443269 ps
CPU time 1.5 seconds
Started Apr 02 12:38:17 PM PDT 24
Finished Apr 02 12:38:18 PM PDT 24
Peak memory 236668 kb
Host smart-1265e912-78c8-491d-b50a-3d2214f9e75c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=592284809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.592284809
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.4033243353
Short name T760
Test name
Test status
Simulation time 31680782 ps
CPU time 1.32 seconds
Started Apr 02 12:38:28 PM PDT 24
Finished Apr 02 12:38:30 PM PDT 24
Peak memory 235772 kb
Host smart-3aaf73f0-85d3-43fa-b9b4-6898a953e582
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4033243353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.4033243353
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1594892781
Short name T747
Test name
Test status
Simulation time 7858735 ps
CPU time 1.47 seconds
Started Apr 02 12:38:29 PM PDT 24
Finished Apr 02 12:38:30 PM PDT 24
Peak memory 235820 kb
Host smart-c9919542-8eb0-40da-829d-ebca75d8f2c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1594892781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.1594892781
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.3287924537
Short name T152
Test name
Test status
Simulation time 18834931 ps
CPU time 1.32 seconds
Started Apr 02 12:38:21 PM PDT 24
Finished Apr 02 12:38:23 PM PDT 24
Peak memory 234720 kb
Host smart-48b5aac6-8bb0-414f-a2e4-27b1b6a0064a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3287924537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.3287924537
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3676046321
Short name T342
Test name
Test status
Simulation time 7268370 ps
CPU time 1.32 seconds
Started Apr 02 12:38:31 PM PDT 24
Finished Apr 02 12:38:33 PM PDT 24
Peak memory 236588 kb
Host smart-7f49fc46-ec8f-4236-88bc-0fbe00620880
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3676046321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.3676046321
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.696996665
Short name T742
Test name
Test status
Simulation time 26031709 ps
CPU time 1.35 seconds
Started Apr 02 12:38:18 PM PDT 24
Finished Apr 02 12:38:20 PM PDT 24
Peak memory 234776 kb
Host smart-07c0793a-973f-4f4e-8af5-686d5d1dde04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=696996665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.696996665
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.3065243984
Short name T757
Test name
Test status
Simulation time 10062686 ps
CPU time 1.34 seconds
Started Apr 02 12:38:17 PM PDT 24
Finished Apr 02 12:38:18 PM PDT 24
Peak memory 235804 kb
Host smart-265a8cac-ffd8-4ac6-b8d5-521b49708242
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3065243984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.3065243984
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.3941533163
Short name T347
Test name
Test status
Simulation time 44253947 ps
CPU time 1.26 seconds
Started Apr 02 12:38:28 PM PDT 24
Finished Apr 02 12:38:29 PM PDT 24
Peak memory 236676 kb
Host smart-293a106a-cd0e-4b30-8652-91db2666c612
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3941533163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.3941533163
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.3586624203
Short name T792
Test name
Test status
Simulation time 15622379 ps
CPU time 1.4 seconds
Started Apr 02 12:38:17 PM PDT 24
Finished Apr 02 12:38:19 PM PDT 24
Peak memory 234964 kb
Host smart-70c8f051-262c-4999-9706-c1b6eb21c4c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3586624203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.3586624203
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.102240249
Short name T734
Test name
Test status
Simulation time 56992500 ps
CPU time 4.35 seconds
Started Apr 02 12:38:03 PM PDT 24
Finished Apr 02 12:38:08 PM PDT 24
Peak memory 240360 kb
Host smart-97f178cf-7050-4f3b-9689-f8702d93fc7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102240249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.alert_handler_csr_mem_rw_with_rand_reset.102240249
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.3895964576
Short name T828
Test name
Test status
Simulation time 401799108 ps
CPU time 5.65 seconds
Started Apr 02 12:37:59 PM PDT 24
Finished Apr 02 12:38:04 PM PDT 24
Peak memory 240228 kb
Host smart-bd5ecd5e-7bf6-4df5-be74-cc435b9cae62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3895964576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.3895964576
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.710390967
Short name T787
Test name
Test status
Simulation time 11772224 ps
CPU time 1.63 seconds
Started Apr 02 12:38:02 PM PDT 24
Finished Apr 02 12:38:04 PM PDT 24
Peak memory 235772 kb
Host smart-3d2a4b37-3ff9-44af-a218-42139887f8d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=710390967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.710390967
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.3612737972
Short name T766
Test name
Test status
Simulation time 1390069610 ps
CPU time 18.82 seconds
Started Apr 02 12:37:57 PM PDT 24
Finished Apr 02 12:38:16 PM PDT 24
Peak memory 244736 kb
Host smart-8263ebd6-1830-4da6-adf1-792c7bd3ba57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3612737972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.3612737972
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1352935979
Short name T147
Test name
Test status
Simulation time 28688321604 ps
CPU time 504.45 seconds
Started Apr 02 12:38:01 PM PDT 24
Finished Apr 02 12:46:25 PM PDT 24
Peak memory 268072 kb
Host smart-4001b107-30ed-418a-93ab-53791060b3a2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352935979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.1352935979
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.1838321872
Short name T831
Test name
Test status
Simulation time 350315837 ps
CPU time 13.4 seconds
Started Apr 02 12:38:01 PM PDT 24
Finished Apr 02 12:38:15 PM PDT 24
Peak memory 251952 kb
Host smart-822b6067-ba72-40d0-8211-4fdc105856d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1838321872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.1838321872
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.4293900835
Short name T782
Test name
Test status
Simulation time 131081844 ps
CPU time 11.67 seconds
Started Apr 02 12:38:11 PM PDT 24
Finished Apr 02 12:38:23 PM PDT 24
Peak memory 242556 kb
Host smart-e831354c-b011-4431-9776-af5f4b0bce4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293900835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.4293900835
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.868350787
Short name T172
Test name
Test status
Simulation time 64594934 ps
CPU time 6.26 seconds
Started Apr 02 12:38:06 PM PDT 24
Finished Apr 02 12:38:13 PM PDT 24
Peak memory 240260 kb
Host smart-dada5ed8-0f49-483b-b0ef-1ed9cc48f993
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=868350787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.868350787
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2831545011
Short name T346
Test name
Test status
Simulation time 14832108 ps
CPU time 1.79 seconds
Started Apr 02 12:38:08 PM PDT 24
Finished Apr 02 12:38:11 PM PDT 24
Peak memory 236684 kb
Host smart-40c3a547-b080-4ed8-a388-5ba8789f0ed7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2831545011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.2831545011
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2631662474
Short name T779
Test name
Test status
Simulation time 1921717583 ps
CPU time 37.1 seconds
Started Apr 02 12:38:02 PM PDT 24
Finished Apr 02 12:38:39 PM PDT 24
Peak memory 248496 kb
Host smart-b87ab608-cdab-4f0f-908f-edf27f43b286
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2631662474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.2631662474
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.2196906996
Short name T144
Test name
Test status
Simulation time 3250187306 ps
CPU time 99.15 seconds
Started Apr 02 12:38:05 PM PDT 24
Finished Apr 02 12:39:44 PM PDT 24
Peak memory 265104 kb
Host smart-0bc13223-eb67-47d6-b56d-f524685523f9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2196906996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.2196906996
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.733183896
Short name T140
Test name
Test status
Simulation time 19396085241 ps
CPU time 329.36 seconds
Started Apr 02 12:38:03 PM PDT 24
Finished Apr 02 12:43:32 PM PDT 24
Peak memory 268772 kb
Host smart-a1757eeb-ae1a-40ac-af8b-83c5c5c2fdb5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733183896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.733183896
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1184276424
Short name T777
Test name
Test status
Simulation time 130858350 ps
CPU time 9.57 seconds
Started Apr 02 12:38:08 PM PDT 24
Finished Apr 02 12:38:18 PM PDT 24
Peak memory 248556 kb
Host smart-403bba7a-c58d-49fa-97bc-448102c6845d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1184276424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.1184276424
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.2616232837
Short name T355
Test name
Test status
Simulation time 672332591 ps
CPU time 5.94 seconds
Started Apr 02 12:38:02 PM PDT 24
Finished Apr 02 12:38:08 PM PDT 24
Peak memory 239524 kb
Host smart-a1bb76f5-9bbb-40f0-8b6d-a72a2321918c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616232837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.2616232837
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.2758831728
Short name T788
Test name
Test status
Simulation time 63885825 ps
CPU time 5.37 seconds
Started Apr 02 12:38:02 PM PDT 24
Finished Apr 02 12:38:08 PM PDT 24
Peak memory 236568 kb
Host smart-d7f612aa-3f73-4c31-9394-c832ba525127
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2758831728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.2758831728
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.2382589248
Short name T785
Test name
Test status
Simulation time 12268097 ps
CPU time 1.23 seconds
Started Apr 02 12:38:00 PM PDT 24
Finished Apr 02 12:38:02 PM PDT 24
Peak memory 235644 kb
Host smart-73ddd926-7b2e-4f11-80a7-3b314a090699
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2382589248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.2382589248
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1287073061
Short name T752
Test name
Test status
Simulation time 196533985 ps
CPU time 21.8 seconds
Started Apr 02 12:38:05 PM PDT 24
Finished Apr 02 12:38:27 PM PDT 24
Peak memory 244804 kb
Host smart-babecdfb-61af-469e-9fe2-58992b7ba9f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1287073061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.1287073061
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3630886390
Short name T132
Test name
Test status
Simulation time 912074107 ps
CPU time 85.6 seconds
Started Apr 02 12:38:03 PM PDT 24
Finished Apr 02 12:39:29 PM PDT 24
Peak memory 256936 kb
Host smart-65b06a63-a93a-464a-a8f7-4de37d325939
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3630886390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.3630886390
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3594776857
Short name T126
Test name
Test status
Simulation time 6373208855 ps
CPU time 506.04 seconds
Started Apr 02 12:38:04 PM PDT 24
Finished Apr 02 12:46:30 PM PDT 24
Peak memory 270440 kb
Host smart-1b30fe0a-a00f-42b4-811f-31471aaf0169
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594776857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.3594776857
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3515921071
Short name T725
Test name
Test status
Simulation time 269924378 ps
CPU time 9.93 seconds
Started Apr 02 12:38:02 PM PDT 24
Finished Apr 02 12:38:12 PM PDT 24
Peak memory 248548 kb
Host smart-6df593fc-b596-4227-8d23-d26098eb705a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3515921071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3515921071
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3435419446
Short name T720
Test name
Test status
Simulation time 140762522 ps
CPU time 5.72 seconds
Started Apr 02 12:38:04 PM PDT 24
Finished Apr 02 12:38:10 PM PDT 24
Peak memory 239168 kb
Host smart-fa1d7737-c008-4707-bb25-4a1970df4de0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435419446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.3435419446
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.4078777016
Short name T808
Test name
Test status
Simulation time 424570945 ps
CPU time 5.54 seconds
Started Apr 02 12:38:07 PM PDT 24
Finished Apr 02 12:38:12 PM PDT 24
Peak memory 240160 kb
Host smart-63ffb9ef-4470-4819-9eee-dbe884d3c288
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4078777016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.4078777016
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1189255748
Short name T750
Test name
Test status
Simulation time 9658147 ps
CPU time 1.31 seconds
Started Apr 02 12:38:03 PM PDT 24
Finished Apr 02 12:38:04 PM PDT 24
Peak memory 235820 kb
Host smart-fd337987-8f29-41f6-8e14-a09d1771ccf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1189255748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.1189255748
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.4173667914
Short name T822
Test name
Test status
Simulation time 5293867801 ps
CPU time 43.67 seconds
Started Apr 02 12:38:02 PM PDT 24
Finished Apr 02 12:38:45 PM PDT 24
Peak memory 248556 kb
Host smart-4642232e-f567-4566-9adc-0975e9d3ac4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4173667914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.4173667914
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.4122256073
Short name T117
Test name
Test status
Simulation time 9083354157 ps
CPU time 317.68 seconds
Started Apr 02 12:38:12 PM PDT 24
Finished Apr 02 12:43:30 PM PDT 24
Peak memory 265144 kb
Host smart-612e9344-3e99-4ddf-9ead-74e6f1d4ef01
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4122256073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.4122256073
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3999055212
Short name T142
Test name
Test status
Simulation time 101527950893 ps
CPU time 475.19 seconds
Started Apr 02 12:38:04 PM PDT 24
Finished Apr 02 12:45:59 PM PDT 24
Peak memory 265164 kb
Host smart-f3c8ab16-6f5a-4bb9-85db-e35354359756
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999055212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.3999055212
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1837936088
Short name T768
Test name
Test status
Simulation time 651953762 ps
CPU time 12.36 seconds
Started Apr 02 12:38:03 PM PDT 24
Finished Apr 02 12:38:15 PM PDT 24
Peak memory 248648 kb
Host smart-7f888969-e35b-4bb4-b5e6-95a046474e52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1837936088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.1837936088
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1771264505
Short name T769
Test name
Test status
Simulation time 156429448 ps
CPU time 10.99 seconds
Started Apr 02 12:38:05 PM PDT 24
Finished Apr 02 12:38:16 PM PDT 24
Peak memory 248580 kb
Host smart-7a606cfe-6491-48f6-aff3-c1cc0389ee6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771264505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.1771264505
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.88542064
Short name T746
Test name
Test status
Simulation time 120192872 ps
CPU time 4.99 seconds
Started Apr 02 12:38:19 PM PDT 24
Finished Apr 02 12:38:24 PM PDT 24
Peak memory 240244 kb
Host smart-c5d6b80f-a060-47c5-9725-e72dc6ff0962
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=88542064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.88542064
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.3617360083
Short name T823
Test name
Test status
Simulation time 13435509 ps
CPU time 1.23 seconds
Started Apr 02 12:38:05 PM PDT 24
Finished Apr 02 12:38:06 PM PDT 24
Peak memory 236628 kb
Host smart-6472baf0-dbe0-4967-a6c2-30953622a552
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3617360083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.3617360083
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.4125363397
Short name T738
Test name
Test status
Simulation time 11756106167 ps
CPU time 57.79 seconds
Started Apr 02 12:38:18 PM PDT 24
Finished Apr 02 12:39:16 PM PDT 24
Peak memory 244928 kb
Host smart-6c3cb5ea-e82a-49e2-80ce-56c17bcd104d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4125363397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.4125363397
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.2906104602
Short name T128
Test name
Test status
Simulation time 6471207825 ps
CPU time 177.91 seconds
Started Apr 02 12:38:05 PM PDT 24
Finished Apr 02 12:41:03 PM PDT 24
Peak memory 265164 kb
Host smart-f0298dc1-28de-47f3-82c4-66cb3e2efb71
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2906104602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.2906104602
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.3786848458
Short name T719
Test name
Test status
Simulation time 47270767 ps
CPU time 6.04 seconds
Started Apr 02 12:38:02 PM PDT 24
Finished Apr 02 12:38:08 PM PDT 24
Peak memory 248556 kb
Host smart-36c296f3-5649-4054-99f9-b9bd7d543baa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3786848458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.3786848458
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.2498667153
Short name T85
Test name
Test status
Simulation time 8735796329 ps
CPU time 1137.06 seconds
Started Apr 02 01:00:44 PM PDT 24
Finished Apr 02 01:19:42 PM PDT 24
Peak memory 289956 kb
Host smart-4cfdab0a-5b38-4e8a-9edc-88bffdacbc69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498667153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.2498667153
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.1375629437
Short name T577
Test name
Test status
Simulation time 881565026 ps
CPU time 21.7 seconds
Started Apr 02 01:01:01 PM PDT 24
Finished Apr 02 01:01:26 PM PDT 24
Peak memory 240624 kb
Host smart-752f0c0e-c072-4dc7-b3b3-27858ec5a624
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1375629437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.1375629437
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.3235483899
Short name T373
Test name
Test status
Simulation time 3514679774 ps
CPU time 198.64 seconds
Started Apr 02 01:00:38 PM PDT 24
Finished Apr 02 01:03:56 PM PDT 24
Peak memory 256896 kb
Host smart-3c5e3bda-33f6-4b3f-b503-48ac87bbcfd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32354
83899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.3235483899
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.4071272912
Short name T560
Test name
Test status
Simulation time 229620535 ps
CPU time 5.68 seconds
Started Apr 02 01:00:42 PM PDT 24
Finished Apr 02 01:00:48 PM PDT 24
Peak memory 248952 kb
Host smart-ea9e12ad-d74a-4be1-bc68-e9b71d7ae6ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40712
72912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.4071272912
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.2822227806
Short name T700
Test name
Test status
Simulation time 154706473245 ps
CPU time 1981.19 seconds
Started Apr 02 01:00:43 PM PDT 24
Finished Apr 02 01:33:44 PM PDT 24
Peak memory 271552 kb
Host smart-0483dbd1-196d-42ba-9363-c9a587d0b49e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822227806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2822227806
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.748763507
Short name T287
Test name
Test status
Simulation time 33130125853 ps
CPU time 1538.35 seconds
Started Apr 02 01:00:37 PM PDT 24
Finished Apr 02 01:26:16 PM PDT 24
Peak memory 289896 kb
Host smart-e2de7620-0003-4736-9bd5-3382dfd7b311
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748763507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.748763507
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.2373982234
Short name T583
Test name
Test status
Simulation time 3692240778 ps
CPU time 128.34 seconds
Started Apr 02 01:00:44 PM PDT 24
Finished Apr 02 01:02:53 PM PDT 24
Peak memory 248900 kb
Host smart-563d999d-395a-4b66-b21a-d04a597c2c45
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373982234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.2373982234
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.1342384361
Short name T277
Test name
Test status
Simulation time 631989990 ps
CPU time 34.52 seconds
Started Apr 02 01:00:52 PM PDT 24
Finished Apr 02 01:01:31 PM PDT 24
Peak memory 255836 kb
Host smart-cb7cc12a-57de-4d8f-88b1-80644a24523f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13423
84361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.1342384361
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.3738987624
Short name T30
Test name
Test status
Simulation time 960171935 ps
CPU time 40.01 seconds
Started Apr 02 01:00:51 PM PDT 24
Finished Apr 02 01:01:34 PM PDT 24
Peak memory 268676 kb
Host smart-e54b0128-63d1-45f7-8c4a-f300651437df
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3738987624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.3738987624
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.4173402147
Short name T689
Test name
Test status
Simulation time 1195258726 ps
CPU time 12.4 seconds
Started Apr 02 01:00:55 PM PDT 24
Finished Apr 02 01:01:11 PM PDT 24
Peak memory 248828 kb
Host smart-9a29d727-5ef3-43b2-bb1c-fffc8bc90c69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41734
02147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.4173402147
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.1944799273
Short name T198
Test name
Test status
Simulation time 7474337314 ps
CPU time 182.91 seconds
Started Apr 02 01:00:43 PM PDT 24
Finished Apr 02 01:03:46 PM PDT 24
Peak memory 257196 kb
Host smart-becc128c-c253-4d44-81b6-cf7404942574
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944799273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.1944799273
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.1604937975
Short name T707
Test name
Test status
Simulation time 14265544997 ps
CPU time 950.17 seconds
Started Apr 02 01:00:46 PM PDT 24
Finished Apr 02 01:16:37 PM PDT 24
Peak memory 265248 kb
Host smart-184e4fae-4d19-4a22-98fb-73a9c7f531aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604937975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.1604937975
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.2432219938
Short name T469
Test name
Test status
Simulation time 1423128404 ps
CPU time 17.32 seconds
Started Apr 02 01:00:47 PM PDT 24
Finished Apr 02 01:01:05 PM PDT 24
Peak memory 248696 kb
Host smart-9b4f854c-33ae-493a-96f9-eca17dce76e0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2432219938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.2432219938
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.2158828569
Short name T619
Test name
Test status
Simulation time 7847284964 ps
CPU time 140.01 seconds
Started Apr 02 01:00:39 PM PDT 24
Finished Apr 02 01:02:59 PM PDT 24
Peak memory 257108 kb
Host smart-62acff0a-df9c-4ba9-b871-233c23845b98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21588
28569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.2158828569
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.3272595672
Short name T95
Test name
Test status
Simulation time 951863737 ps
CPU time 54.41 seconds
Started Apr 02 01:00:37 PM PDT 24
Finished Apr 02 01:01:32 PM PDT 24
Peak memory 248976 kb
Host smart-e4da331d-f591-4f7f-a201-8c25148a2c81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32725
95672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.3272595672
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.986806841
Short name T337
Test name
Test status
Simulation time 48819754319 ps
CPU time 2127.25 seconds
Started Apr 02 01:00:49 PM PDT 24
Finished Apr 02 01:36:19 PM PDT 24
Peak memory 273552 kb
Host smart-4c686b7f-dfce-47fe-9b23-cf5b807645c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986806841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.986806841
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.1270557261
Short name T694
Test name
Test status
Simulation time 47155124922 ps
CPU time 2609.25 seconds
Started Apr 02 01:00:42 PM PDT 24
Finished Apr 02 01:44:12 PM PDT 24
Peak memory 281780 kb
Host smart-5f09923a-f150-4957-b171-e4498b602a65
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270557261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.1270557261
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.667157596
Short name T17
Test name
Test status
Simulation time 439269948 ps
CPU time 9.87 seconds
Started Apr 02 01:00:47 PM PDT 24
Finished Apr 02 01:00:57 PM PDT 24
Peak memory 248872 kb
Host smart-6dab70e9-0501-443e-91dc-12357806cdca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66715
7596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.667157596
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.2285543742
Short name T504
Test name
Test status
Simulation time 253854502 ps
CPU time 15.42 seconds
Started Apr 02 01:00:51 PM PDT 24
Finished Apr 02 01:01:09 PM PDT 24
Peak memory 249188 kb
Host smart-3cf9c34e-c89a-40c4-bc1b-a9034cf5eb8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22855
43742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.2285543742
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.329126517
Short name T11
Test name
Test status
Simulation time 714284304 ps
CPU time 28.36 seconds
Started Apr 02 01:00:38 PM PDT 24
Finished Apr 02 01:01:07 PM PDT 24
Peak memory 269880 kb
Host smart-774d891b-2c24-41eb-8705-a84cdbfdbe49
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=329126517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.329126517
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.1041256514
Short name T498
Test name
Test status
Simulation time 1170479220 ps
CPU time 71.27 seconds
Started Apr 02 01:00:59 PM PDT 24
Finished Apr 02 01:02:12 PM PDT 24
Peak memory 248768 kb
Host smart-472e095c-e852-404e-b4c6-e26aff278866
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10412
56514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.1041256514
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.3178276604
Short name T260
Test name
Test status
Simulation time 126432528950 ps
CPU time 3726.92 seconds
Started Apr 02 01:00:36 PM PDT 24
Finished Apr 02 02:02:43 PM PDT 24
Peak memory 304320 kb
Host smart-9c69fc06-3507-4ea6-83e4-3e3ee59acb54
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178276604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.3178276604
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.209398504
Short name T206
Test name
Test status
Simulation time 164427450 ps
CPU time 3.82 seconds
Started Apr 02 01:01:15 PM PDT 24
Finished Apr 02 01:01:22 PM PDT 24
Peak memory 249040 kb
Host smart-0bd337bc-eac2-444d-9db3-df0c316a1fc9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=209398504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.209398504
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.698341337
Short name T93
Test name
Test status
Simulation time 34713764871 ps
CPU time 2163.38 seconds
Started Apr 02 01:01:02 PM PDT 24
Finished Apr 02 01:37:09 PM PDT 24
Peak memory 288528 kb
Host smart-2e9d7d29-af59-4092-802a-f06706a1999c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698341337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.698341337
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.2068866912
Short name T387
Test name
Test status
Simulation time 183130251 ps
CPU time 10.16 seconds
Started Apr 02 01:00:57 PM PDT 24
Finished Apr 02 01:01:09 PM PDT 24
Peak memory 240688 kb
Host smart-a2d3989e-cc76-490c-9fbe-c363b8160bac
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2068866912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.2068866912
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.2528408888
Short name T569
Test name
Test status
Simulation time 9327555388 ps
CPU time 266.3 seconds
Started Apr 02 01:00:52 PM PDT 24
Finished Apr 02 01:05:22 PM PDT 24
Peak memory 251072 kb
Host smart-a4356ef9-a42d-4975-a139-0a47ca36a0c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25284
08888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2528408888
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.2334785228
Short name T618
Test name
Test status
Simulation time 92203072 ps
CPU time 9.95 seconds
Started Apr 02 01:01:01 PM PDT 24
Finished Apr 02 01:01:14 PM PDT 24
Peak memory 254624 kb
Host smart-2cb863de-4ce9-4c1f-9e14-85191d99f120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23347
85228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.2334785228
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.1404035977
Short name T290
Test name
Test status
Simulation time 121518778119 ps
CPU time 2039.25 seconds
Started Apr 02 01:01:23 PM PDT 24
Finished Apr 02 01:35:24 PM PDT 24
Peak memory 285940 kb
Host smart-b62c676d-67c2-4e6e-9d32-f370a3ea3af3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404035977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1404035977
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.1872637208
Short name T318
Test name
Test status
Simulation time 12813853075 ps
CPU time 546.12 seconds
Started Apr 02 01:01:06 PM PDT 24
Finished Apr 02 01:10:16 PM PDT 24
Peak memory 248020 kb
Host smart-b7e279e7-c1ea-43d4-8230-01955b7f7c15
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872637208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.1872637208
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.21356936
Short name T651
Test name
Test status
Simulation time 405746842 ps
CPU time 14.49 seconds
Started Apr 02 01:01:08 PM PDT 24
Finished Apr 02 01:01:29 PM PDT 24
Peak memory 248900 kb
Host smart-8a4a66b9-87f4-4719-b5d9-d14542932577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21356
936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.21356936
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.2808265614
Short name T404
Test name
Test status
Simulation time 2221563432 ps
CPU time 69.03 seconds
Started Apr 02 01:00:51 PM PDT 24
Finished Apr 02 01:02:03 PM PDT 24
Peak memory 255016 kb
Host smart-9b902c4e-a74e-4476-a0a5-50083ac8b9fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28082
65614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.2808265614
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.3209105156
Short name T681
Test name
Test status
Simulation time 1619981286 ps
CPU time 38.73 seconds
Started Apr 02 01:01:12 PM PDT 24
Finished Apr 02 01:01:57 PM PDT 24
Peak memory 248244 kb
Host smart-004c97a1-9556-4185-a79c-5e34c9833954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32091
05156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.3209105156
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.1300820610
Short name T243
Test name
Test status
Simulation time 362502126 ps
CPU time 7.35 seconds
Started Apr 02 01:00:56 PM PDT 24
Finished Apr 02 01:01:04 PM PDT 24
Peak memory 240732 kb
Host smart-eb7a6554-bafe-4667-b0e6-4b68bee096a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13008
20610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.1300820610
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.4138763164
Short name T87
Test name
Test status
Simulation time 79121966913 ps
CPU time 2991.24 seconds
Started Apr 02 01:00:58 PM PDT 24
Finished Apr 02 01:50:51 PM PDT 24
Peak memory 289148 kb
Host smart-9addba6c-20ab-4227-965a-1cdd79771b6c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138763164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.4138763164
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.2282752505
Short name T211
Test name
Test status
Simulation time 44625599 ps
CPU time 2.62 seconds
Started Apr 02 01:00:56 PM PDT 24
Finished Apr 02 01:01:02 PM PDT 24
Peak memory 249080 kb
Host smart-fc0c6f65-fcee-4f09-8171-5ae90600af97
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2282752505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.2282752505
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.3823062282
Short name T47
Test name
Test status
Simulation time 200122103668 ps
CPU time 3038.22 seconds
Started Apr 02 01:01:01 PM PDT 24
Finished Apr 02 01:51:42 PM PDT 24
Peak memory 289944 kb
Host smart-7d8ca579-869f-48e5-8788-6eb31ea42a52
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823062282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.3823062282
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.4264006649
Short name T471
Test name
Test status
Simulation time 139534603 ps
CPU time 8.68 seconds
Started Apr 02 01:00:59 PM PDT 24
Finished Apr 02 01:01:08 PM PDT 24
Peak memory 240704 kb
Host smart-6e1d785c-4f50-4cdc-8620-2f693682fc84
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4264006649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.4264006649
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.2535574343
Short name T392
Test name
Test status
Simulation time 12620483629 ps
CPU time 190.54 seconds
Started Apr 02 01:01:08 PM PDT 24
Finished Apr 02 01:04:25 PM PDT 24
Peak memory 256748 kb
Host smart-3396f64d-88c3-4076-8e08-41a0c59072c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25355
74343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.2535574343
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.1175807035
Short name T467
Test name
Test status
Simulation time 1191492048 ps
CPU time 71 seconds
Started Apr 02 01:01:15 PM PDT 24
Finished Apr 02 01:02:30 PM PDT 24
Peak memory 254776 kb
Host smart-03448dc1-522b-4b6c-be3d-161ef9ab11fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11758
07035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.1175807035
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.3930179813
Short name T395
Test name
Test status
Simulation time 33431494409 ps
CPU time 1532.3 seconds
Started Apr 02 01:00:55 PM PDT 24
Finished Apr 02 01:26:29 PM PDT 24
Peak memory 289508 kb
Host smart-2b2e62e9-ff7f-4341-a38e-6c9942ea5456
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930179813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.3930179813
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.4003109232
Short name T320
Test name
Test status
Simulation time 2667506280 ps
CPU time 115.45 seconds
Started Apr 02 01:01:01 PM PDT 24
Finished Apr 02 01:02:59 PM PDT 24
Peak memory 248080 kb
Host smart-bcd78f53-2a9c-4991-b622-055b265259de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003109232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.4003109232
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.3773035198
Short name T573
Test name
Test status
Simulation time 1227694790 ps
CPU time 56 seconds
Started Apr 02 01:01:11 PM PDT 24
Finished Apr 02 01:02:13 PM PDT 24
Peak memory 255828 kb
Host smart-5be76fb7-e115-447b-8dae-6ce5569e2077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37730
35198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.3773035198
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.2173135679
Short name T378
Test name
Test status
Simulation time 2978624267 ps
CPU time 45.05 seconds
Started Apr 02 01:01:01 PM PDT 24
Finished Apr 02 01:01:50 PM PDT 24
Peak memory 248004 kb
Host smart-5b8be2dc-2f59-4352-83f7-7a62ceb4023a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21731
35679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2173135679
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.1171087955
Short name T540
Test name
Test status
Simulation time 266656259 ps
CPU time 25.26 seconds
Started Apr 02 01:01:05 PM PDT 24
Finished Apr 02 01:01:33 PM PDT 24
Peak memory 256308 kb
Host smart-f85e9422-b155-47f9-8986-9eff07863451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11710
87955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.1171087955
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.731626161
Short name T482
Test name
Test status
Simulation time 971190038 ps
CPU time 45.57 seconds
Started Apr 02 01:00:52 PM PDT 24
Finished Apr 02 01:01:42 PM PDT 24
Peak memory 248900 kb
Host smart-daaf1ca8-62b4-49b1-9468-198a7a44b1e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73162
6161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.731626161
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.1603152942
Short name T552
Test name
Test status
Simulation time 10586763928 ps
CPU time 984.22 seconds
Started Apr 02 01:00:59 PM PDT 24
Finished Apr 02 01:17:23 PM PDT 24
Peak memory 286256 kb
Host smart-ac9e9cf2-9f64-4398-90e1-7bd256c634f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603152942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.1603152942
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.1346136801
Short name T410
Test name
Test status
Simulation time 4094216393 ps
CPU time 45.58 seconds
Started Apr 02 01:01:04 PM PDT 24
Finished Apr 02 01:01:53 PM PDT 24
Peak memory 240724 kb
Host smart-d8584eab-ceae-407b-a893-cfffb7b7dc1e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1346136801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.1346136801
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.2557813288
Short name T627
Test name
Test status
Simulation time 3410199331 ps
CPU time 184.85 seconds
Started Apr 02 01:01:10 PM PDT 24
Finished Apr 02 01:04:21 PM PDT 24
Peak memory 256896 kb
Host smart-08140bbd-d1fd-43a5-b6e7-a49f5fdced8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25578
13288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.2557813288
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.4082729711
Short name T96
Test name
Test status
Simulation time 4032011524 ps
CPU time 61.22 seconds
Started Apr 02 01:01:02 PM PDT 24
Finished Apr 02 01:02:06 PM PDT 24
Peak memory 255312 kb
Host smart-e6eee5b5-a078-43cb-beb8-969c4cadfb30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40827
29711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.4082729711
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.3226861335
Short name T600
Test name
Test status
Simulation time 31027512727 ps
CPU time 1439.01 seconds
Started Apr 02 01:01:20 PM PDT 24
Finished Apr 02 01:25:20 PM PDT 24
Peak memory 289164 kb
Host smart-47a7a292-7531-4ff0-997e-576952dec67a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226861335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.3226861335
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.1227416050
Short name T389
Test name
Test status
Simulation time 9622444689 ps
CPU time 1420.98 seconds
Started Apr 02 01:00:59 PM PDT 24
Finished Apr 02 01:24:42 PM PDT 24
Peak memory 289912 kb
Host smart-636c6edc-3f1e-4a72-91e1-30cf460fb8d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227416050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.1227416050
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.328504425
Short name T204
Test name
Test status
Simulation time 8240415020 ps
CPU time 364.48 seconds
Started Apr 02 01:00:58 PM PDT 24
Finished Apr 02 01:07:04 PM PDT 24
Peak memory 248316 kb
Host smart-864c8551-1be2-4b0d-ad8f-92e8bb2b2a9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328504425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.328504425
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.885165027
Short name T695
Test name
Test status
Simulation time 809003119 ps
CPU time 50.22 seconds
Started Apr 02 01:00:53 PM PDT 24
Finished Apr 02 01:01:46 PM PDT 24
Peak memory 248892 kb
Host smart-c247a967-0385-498d-b0ba-7a9419edd076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88516
5027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.885165027
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.636306249
Short name T642
Test name
Test status
Simulation time 2485509351 ps
CPU time 36.57 seconds
Started Apr 02 01:01:09 PM PDT 24
Finished Apr 02 01:01:53 PM PDT 24
Peak memory 248968 kb
Host smart-34927f53-e0cc-4352-a02b-34f2df7fdeef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63630
6249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.636306249
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.528527337
Short name T597
Test name
Test status
Simulation time 1187029278 ps
CPU time 68.88 seconds
Started Apr 02 01:01:01 PM PDT 24
Finished Apr 02 01:02:13 PM PDT 24
Peak memory 249028 kb
Host smart-0c558fa0-10c3-421b-b693-37a884b6164d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52852
7337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.528527337
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.2660029948
Short name T216
Test name
Test status
Simulation time 17439305 ps
CPU time 2.83 seconds
Started Apr 02 01:01:03 PM PDT 24
Finished Apr 02 01:01:08 PM PDT 24
Peak memory 249044 kb
Host smart-f3c297bf-5de9-4353-95e5-2ec720999b06
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2660029948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.2660029948
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.3487462823
Short name T423
Test name
Test status
Simulation time 51794668445 ps
CPU time 2984.36 seconds
Started Apr 02 01:01:27 PM PDT 24
Finished Apr 02 01:51:12 PM PDT 24
Peak memory 289708 kb
Host smart-e5a42daf-5461-4b27-acb5-dea6fe118a87
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487462823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.3487462823
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.1006501643
Short name T584
Test name
Test status
Simulation time 98475138 ps
CPU time 7.05 seconds
Started Apr 02 01:01:12 PM PDT 24
Finished Apr 02 01:01:25 PM PDT 24
Peak memory 240652 kb
Host smart-6bc83435-e0a2-4568-9e1e-6d9b763f2fcd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1006501643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.1006501643
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.3939203499
Short name T196
Test name
Test status
Simulation time 50322679368 ps
CPU time 163 seconds
Started Apr 02 01:01:06 PM PDT 24
Finished Apr 02 01:03:53 PM PDT 24
Peak memory 250064 kb
Host smart-99face88-2ccf-476d-bcec-ed11f5743f45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39392
03499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.3939203499
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.630746468
Short name T399
Test name
Test status
Simulation time 285608125 ps
CPU time 28.33 seconds
Started Apr 02 01:01:01 PM PDT 24
Finished Apr 02 01:01:32 PM PDT 24
Peak memory 255608 kb
Host smart-42a0c735-b599-4a44-b7a2-04327bed3457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63074
6468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.630746468
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.3798610268
Short name T336
Test name
Test status
Simulation time 47485163860 ps
CPU time 1303.74 seconds
Started Apr 02 01:01:06 PM PDT 24
Finished Apr 02 01:22:54 PM PDT 24
Peak memory 285908 kb
Host smart-b17786f9-eee3-44db-b5aa-3d5bb9786fe3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798610268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.3798610268
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.1613100419
Short name T645
Test name
Test status
Simulation time 32402456890 ps
CPU time 1304.49 seconds
Started Apr 02 01:01:01 PM PDT 24
Finished Apr 02 01:22:48 PM PDT 24
Peak memory 281804 kb
Host smart-610764b5-c5b3-4197-ac08-c5b0dd98c046
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613100419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.1613100419
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.674191033
Short name T303
Test name
Test status
Simulation time 6430150168 ps
CPU time 281.74 seconds
Started Apr 02 01:01:28 PM PDT 24
Finished Apr 02 01:06:10 PM PDT 24
Peak memory 247984 kb
Host smart-695e9ebe-9522-40b3-972b-9b0b1a08dd44
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674191033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.674191033
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.1489002777
Short name T479
Test name
Test status
Simulation time 336048033 ps
CPU time 29.2 seconds
Started Apr 02 01:01:06 PM PDT 24
Finished Apr 02 01:01:39 PM PDT 24
Peak memory 256136 kb
Host smart-58f6fc05-12f1-4700-91f7-f23d7dd5d4bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14890
02777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.1489002777
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.179332699
Short name T294
Test name
Test status
Simulation time 1249882597 ps
CPU time 27.59 seconds
Started Apr 02 01:01:10 PM PDT 24
Finished Apr 02 01:01:42 PM PDT 24
Peak memory 249204 kb
Host smart-bd21b059-c1c3-4808-a7b6-4b55d04088f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17933
2699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.179332699
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.3962286490
Short name T179
Test name
Test status
Simulation time 71893816 ps
CPU time 5.15 seconds
Started Apr 02 01:01:19 PM PDT 24
Finished Apr 02 01:01:24 PM PDT 24
Peak memory 240604 kb
Host smart-3500aebf-20a0-42b5-b199-720dc2243c32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39622
86490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.3962286490
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.1590518170
Short name T673
Test name
Test status
Simulation time 299252012 ps
CPU time 27.95 seconds
Started Apr 02 01:01:01 PM PDT 24
Finished Apr 02 01:01:32 PM PDT 24
Peak memory 248900 kb
Host smart-b43e897d-20c6-4f06-92bf-b5e86d9fe791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15905
18170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.1590518170
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.4194603935
Short name T291
Test name
Test status
Simulation time 150079477391 ps
CPU time 1265.96 seconds
Started Apr 02 01:01:11 PM PDT 24
Finished Apr 02 01:22:24 PM PDT 24
Peak memory 289196 kb
Host smart-a6bfdf82-91a4-4788-a4ec-2714e08588ff
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194603935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.4194603935
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.402052274
Short name T109
Test name
Test status
Simulation time 122131626510 ps
CPU time 3481.29 seconds
Started Apr 02 01:01:18 PM PDT 24
Finished Apr 02 01:59:21 PM PDT 24
Peak memory 278984 kb
Host smart-c8cc3f47-1084-4878-bca4-f8cc0d7e00e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402052274 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.402052274
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.2458062423
Short name T210
Test name
Test status
Simulation time 26715990 ps
CPU time 2.64 seconds
Started Apr 02 01:01:04 PM PDT 24
Finished Apr 02 01:01:08 PM PDT 24
Peak memory 249040 kb
Host smart-7174bc98-89ac-4426-b893-f034f3b66bdb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2458062423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.2458062423
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.1477022811
Short name T511
Test name
Test status
Simulation time 94687438752 ps
CPU time 1437.42 seconds
Started Apr 02 01:01:21 PM PDT 24
Finished Apr 02 01:25:20 PM PDT 24
Peak memory 287736 kb
Host smart-100e242a-1f11-4f02-b4dc-f53aa2cccbcf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477022811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.1477022811
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.3861391801
Short name T203
Test name
Test status
Simulation time 2520878424 ps
CPU time 54.5 seconds
Started Apr 02 01:01:07 PM PDT 24
Finished Apr 02 01:02:05 PM PDT 24
Peak memory 240756 kb
Host smart-1d4a8300-2701-40c1-a06a-d5d36d426c5b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3861391801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.3861391801
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.3973271070
Short name T182
Test name
Test status
Simulation time 2789878759 ps
CPU time 170.67 seconds
Started Apr 02 01:01:19 PM PDT 24
Finished Apr 02 01:04:11 PM PDT 24
Peak memory 256448 kb
Host smart-0aa7d857-9d0d-4326-9cb8-aba2ff056ead
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39732
71070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.3973271070
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.3169414005
Short name T539
Test name
Test status
Simulation time 1420604942 ps
CPU time 12.63 seconds
Started Apr 02 01:01:02 PM PDT 24
Finished Apr 02 01:01:17 PM PDT 24
Peak memory 253160 kb
Host smart-e6fc3950-dbd7-482c-a86c-0572f787d876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31694
14005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3169414005
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.2171814811
Short name T544
Test name
Test status
Simulation time 76215003962 ps
CPU time 1218.09 seconds
Started Apr 02 01:01:02 PM PDT 24
Finished Apr 02 01:21:23 PM PDT 24
Peak memory 281692 kb
Host smart-d3cc8ad6-cf71-4894-b874-63448f5d679e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171814811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.2171814811
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.44074287
Short name T665
Test name
Test status
Simulation time 9154161214 ps
CPU time 105.25 seconds
Started Apr 02 01:01:01 PM PDT 24
Finished Apr 02 01:02:49 PM PDT 24
Peak memory 247184 kb
Host smart-30990cce-64b5-4ca8-998f-20061e06fe51
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44074287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.44074287
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.4197916833
Short name T415
Test name
Test status
Simulation time 1438444797 ps
CPU time 23.55 seconds
Started Apr 02 01:01:19 PM PDT 24
Finished Apr 02 01:01:43 PM PDT 24
Peak memory 255692 kb
Host smart-c11d8897-43d9-4fb3-a740-71070a88eeb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41979
16833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.4197916833
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.3400664739
Short name T579
Test name
Test status
Simulation time 6893212283 ps
CPU time 60.77 seconds
Started Apr 02 01:00:58 PM PDT 24
Finished Apr 02 01:02:00 PM PDT 24
Peak memory 255732 kb
Host smart-d7d8255a-71f7-4459-9722-840875e628a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34006
64739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.3400664739
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.2626356910
Short name T54
Test name
Test status
Simulation time 91862289 ps
CPU time 10.98 seconds
Started Apr 02 01:01:17 PM PDT 24
Finished Apr 02 01:01:30 PM PDT 24
Peak memory 255996 kb
Host smart-4ed8cb26-a392-47f2-9d04-cc007011d361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26263
56910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.2626356910
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.4292068057
Short name T393
Test name
Test status
Simulation time 1522796036 ps
CPU time 46.74 seconds
Started Apr 02 01:01:12 PM PDT 24
Finished Apr 02 01:02:04 PM PDT 24
Peak memory 256040 kb
Host smart-d2dd5eb7-f759-491b-885f-1d169e503b70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42920
68057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.4292068057
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.1091506609
Short name T82
Test name
Test status
Simulation time 72781545887 ps
CPU time 2165.95 seconds
Started Apr 02 01:01:04 PM PDT 24
Finished Apr 02 01:37:13 PM PDT 24
Peak memory 273496 kb
Host smart-f732c884-5a07-4b58-b00c-5fa8e7decde4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091506609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.1091506609
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.941601131
Short name T174
Test name
Test status
Simulation time 133984500470 ps
CPU time 4414.12 seconds
Started Apr 02 01:01:05 PM PDT 24
Finished Apr 02 02:14:43 PM PDT 24
Peak memory 322168 kb
Host smart-365964ae-0a77-41e9-89f1-1b8b2a81a73b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941601131 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.941601131
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.1339407197
Short name T222
Test name
Test status
Simulation time 47049870 ps
CPU time 2.43 seconds
Started Apr 02 01:01:31 PM PDT 24
Finished Apr 02 01:01:33 PM PDT 24
Peak memory 249088 kb
Host smart-8ad47d28-8969-41fa-a585-c8a6c108a312
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1339407197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.1339407197
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.1513794124
Short name T702
Test name
Test status
Simulation time 53988849839 ps
CPU time 3040.25 seconds
Started Apr 02 01:01:33 PM PDT 24
Finished Apr 02 01:52:13 PM PDT 24
Peak memory 289168 kb
Host smart-17a6785a-ce50-4fee-af17-e08e4a40c3db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513794124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.1513794124
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.2514573710
Short name T92
Test name
Test status
Simulation time 21355607387 ps
CPU time 108.31 seconds
Started Apr 02 01:01:15 PM PDT 24
Finished Apr 02 01:03:07 PM PDT 24
Peak memory 249016 kb
Host smart-ee3c0aaa-b02f-42c0-9fc6-769c6cfec251
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2514573710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.2514573710
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.564658949
Short name T663
Test name
Test status
Simulation time 1452673832 ps
CPU time 79.69 seconds
Started Apr 02 01:01:19 PM PDT 24
Finished Apr 02 01:02:40 PM PDT 24
Peak memory 255304 kb
Host smart-ef1e4644-d1fe-490e-8ceb-2c76e2c6a859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56465
8949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.564658949
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.778549766
Short name T69
Test name
Test status
Simulation time 2187814736 ps
CPU time 33.22 seconds
Started Apr 02 01:01:14 PM PDT 24
Finished Apr 02 01:01:52 PM PDT 24
Peak memory 255524 kb
Host smart-f6ce346b-85a2-4793-beb6-6698a1ecc9e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77854
9766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.778549766
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.3923972194
Short name T327
Test name
Test status
Simulation time 88220579753 ps
CPU time 2715.28 seconds
Started Apr 02 01:01:20 PM PDT 24
Finished Apr 02 01:46:36 PM PDT 24
Peak memory 289192 kb
Host smart-4715993e-cb89-428d-b6a7-e95f531744ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923972194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.3923972194
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.3104793055
Short name T26
Test name
Test status
Simulation time 199425987904 ps
CPU time 2678.52 seconds
Started Apr 02 01:01:06 PM PDT 24
Finished Apr 02 01:45:48 PM PDT 24
Peak memory 288244 kb
Host smart-d7e419c1-05c5-4d7c-b6cd-ca51dccfc0ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104793055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.3104793055
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.3249598865
Short name T641
Test name
Test status
Simulation time 133619111 ps
CPU time 5.84 seconds
Started Apr 02 01:01:03 PM PDT 24
Finished Apr 02 01:01:11 PM PDT 24
Peak memory 248812 kb
Host smart-eaf50131-6f56-457d-925d-048e5f972436
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32495
98865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.3249598865
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.2581692904
Short name T494
Test name
Test status
Simulation time 492327591 ps
CPU time 33.7 seconds
Started Apr 02 01:01:06 PM PDT 24
Finished Apr 02 01:01:43 PM PDT 24
Peak memory 248708 kb
Host smart-7782d481-bb47-4f6a-a891-b8166fafdac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25816
92904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.2581692904
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.3417910505
Short name T408
Test name
Test status
Simulation time 343559395 ps
CPU time 30.42 seconds
Started Apr 02 01:01:13 PM PDT 24
Finished Apr 02 01:01:48 PM PDT 24
Peak memory 248880 kb
Host smart-13974a43-a93e-49d9-b198-9f96e8f9c778
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34179
10505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.3417910505
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.3499425304
Short name T709
Test name
Test status
Simulation time 958297284 ps
CPU time 21.05 seconds
Started Apr 02 01:01:01 PM PDT 24
Finished Apr 02 01:01:25 PM PDT 24
Peak memory 248796 kb
Host smart-7c988b89-1fc6-43ce-ae2f-88105a5eda40
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499425304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.3499425304
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.2824020436
Short name T202
Test name
Test status
Simulation time 59983997393 ps
CPU time 5724.86 seconds
Started Apr 02 01:01:22 PM PDT 24
Finished Apr 02 02:36:48 PM PDT 24
Peak memory 355540 kb
Host smart-c6669d66-c7f6-40df-8710-1f2b83ba62ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824020436 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.2824020436
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.1618660651
Short name T218
Test name
Test status
Simulation time 203654400 ps
CPU time 4.01 seconds
Started Apr 02 01:01:25 PM PDT 24
Finished Apr 02 01:01:30 PM PDT 24
Peak memory 249048 kb
Host smart-2802d6fa-1d91-47ef-9ca4-d7dfe2c159fd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1618660651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.1618660651
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.3286114150
Short name T662
Test name
Test status
Simulation time 148776703975 ps
CPU time 2323.56 seconds
Started Apr 02 01:01:09 PM PDT 24
Finished Apr 02 01:40:00 PM PDT 24
Peak memory 281764 kb
Host smart-0d00ccd6-0153-4866-8810-67b17f5da3a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286114150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.3286114150
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.1391595431
Short name T362
Test name
Test status
Simulation time 2637887579 ps
CPU time 13.63 seconds
Started Apr 02 01:01:07 PM PDT 24
Finished Apr 02 01:01:24 PM PDT 24
Peak memory 240624 kb
Host smart-50920edb-61ac-4aa7-a9b4-d64800f171ec
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1391595431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1391595431
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.2114996359
Short name T420
Test name
Test status
Simulation time 5560059429 ps
CPU time 180.07 seconds
Started Apr 02 01:01:32 PM PDT 24
Finished Apr 02 01:04:32 PM PDT 24
Peak memory 250028 kb
Host smart-c1f0dcfc-55a4-415b-bc53-10d8dc67dc9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21149
96359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.2114996359
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.530782531
Short name T183
Test name
Test status
Simulation time 878594436 ps
CPU time 24.69 seconds
Started Apr 02 01:01:05 PM PDT 24
Finished Apr 02 01:01:34 PM PDT 24
Peak memory 253892 kb
Host smart-bb341b4e-fd10-4f26-9af5-1ede75e0947a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53078
2531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.530782531
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.4257236959
Short name T595
Test name
Test status
Simulation time 40380757404 ps
CPU time 2062.35 seconds
Started Apr 02 01:01:21 PM PDT 24
Finished Apr 02 01:35:45 PM PDT 24
Peak memory 287156 kb
Host smart-cdff3381-15bd-4958-8451-8c2853b5d703
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257236959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.4257236959
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.3378077394
Short name T326
Test name
Test status
Simulation time 5627692163 ps
CPU time 227.08 seconds
Started Apr 02 01:01:21 PM PDT 24
Finished Apr 02 01:05:09 PM PDT 24
Peak memory 247176 kb
Host smart-bafd55a2-455f-458a-8191-6c8d6461b479
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378077394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3378077394
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.3494247006
Short name T510
Test name
Test status
Simulation time 1208100316 ps
CPU time 37.64 seconds
Started Apr 02 01:01:22 PM PDT 24
Finished Apr 02 01:02:02 PM PDT 24
Peak memory 256056 kb
Host smart-4be600b3-0b04-47fc-9063-ced6b10fec75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34942
47006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.3494247006
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.332966444
Short name T18
Test name
Test status
Simulation time 421607765 ps
CPU time 9.42 seconds
Started Apr 02 01:01:02 PM PDT 24
Finished Apr 02 01:01:14 PM PDT 24
Peak memory 248932 kb
Host smart-ec5196e8-4911-4dda-97dd-57c4b6bbdc90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33296
6444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.332966444
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.2850171679
Short name T431
Test name
Test status
Simulation time 841341097 ps
CPU time 60.23 seconds
Started Apr 02 01:01:30 PM PDT 24
Finished Apr 02 01:02:30 PM PDT 24
Peak memory 255344 kb
Host smart-d910baf1-d849-4572-bf08-379619b9be66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28501
71679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.2850171679
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.3040100696
Short name T678
Test name
Test status
Simulation time 179039562 ps
CPU time 15.52 seconds
Started Apr 02 01:01:12 PM PDT 24
Finished Apr 02 01:01:33 PM PDT 24
Peak memory 249092 kb
Host smart-fe2db2f5-5fec-4c0f-b0de-f39c9098fdeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30401
00696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.3040100696
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.1439855293
Short name T103
Test name
Test status
Simulation time 58006989037 ps
CPU time 4746.98 seconds
Started Apr 02 01:01:05 PM PDT 24
Finished Apr 02 02:20:15 PM PDT 24
Peak memory 306396 kb
Host smart-c5b71ea4-884a-460f-aa12-fe75329df9e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439855293 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.1439855293
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.1406390116
Short name T223
Test name
Test status
Simulation time 95626811 ps
CPU time 3.12 seconds
Started Apr 02 01:01:22 PM PDT 24
Finished Apr 02 01:01:25 PM PDT 24
Peak memory 249100 kb
Host smart-a7400c7f-8a7c-4449-b993-14c2a2744ef2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1406390116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.1406390116
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.4060247072
Short name T670
Test name
Test status
Simulation time 108177931016 ps
CPU time 1910.19 seconds
Started Apr 02 01:01:06 PM PDT 24
Finished Apr 02 01:33:00 PM PDT 24
Peak memory 284076 kb
Host smart-0a44d368-7a66-4341-adf5-7d8be60e3465
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060247072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.4060247072
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.919064153
Short name T391
Test name
Test status
Simulation time 662730245 ps
CPU time 10.53 seconds
Started Apr 02 01:01:19 PM PDT 24
Finished Apr 02 01:01:31 PM PDT 24
Peak memory 251800 kb
Host smart-5f17a073-9185-4e24-b884-11dc44133063
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=919064153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.919064153
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.1012860501
Short name T683
Test name
Test status
Simulation time 436149803 ps
CPU time 35.58 seconds
Started Apr 02 01:01:05 PM PDT 24
Finished Apr 02 01:01:43 PM PDT 24
Peak memory 248764 kb
Host smart-dd6d5cf1-3e02-4322-af59-157670804bfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10128
60501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.1012860501
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.3401609681
Short name T459
Test name
Test status
Simulation time 827727400 ps
CPU time 21.37 seconds
Started Apr 02 01:01:34 PM PDT 24
Finished Apr 02 01:01:56 PM PDT 24
Peak memory 248844 kb
Host smart-c49c5332-4722-42da-84ee-758741cc6804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34016
09681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.3401609681
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.2206460008
Short name T289
Test name
Test status
Simulation time 151980227857 ps
CPU time 2561.55 seconds
Started Apr 02 01:01:08 PM PDT 24
Finished Apr 02 01:43:55 PM PDT 24
Peak memory 288716 kb
Host smart-bce52ae6-bde9-4130-b3ba-8e87423acf56
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206460008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.2206460008
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.287957117
Short name T499
Test name
Test status
Simulation time 372098038 ps
CPU time 25.22 seconds
Started Apr 02 01:01:05 PM PDT 24
Finished Apr 02 01:01:33 PM PDT 24
Peak memory 248892 kb
Host smart-92559a92-6acc-4563-9923-6efdd6ed81fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28795
7117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.287957117
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.3838621153
Short name T425
Test name
Test status
Simulation time 1651009692 ps
CPU time 23.21 seconds
Started Apr 02 01:01:37 PM PDT 24
Finished Apr 02 01:02:00 PM PDT 24
Peak memory 248836 kb
Host smart-fdaa97a0-eb05-4bc1-a631-3f9b6e7e2c03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38386
21153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3838621153
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.3825813100
Short name T367
Test name
Test status
Simulation time 155138125 ps
CPU time 19.98 seconds
Started Apr 02 01:01:06 PM PDT 24
Finished Apr 02 01:01:30 PM PDT 24
Peak memory 254776 kb
Host smart-aae07968-76f5-462e-bd1f-32167875f171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38258
13100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.3825813100
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.3736582602
Short name T374
Test name
Test status
Simulation time 478711952 ps
CPU time 36 seconds
Started Apr 02 01:01:05 PM PDT 24
Finished Apr 02 01:01:43 PM PDT 24
Peak memory 255976 kb
Host smart-cbcb769a-8ad8-48ba-86d6-b091bf01425c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37365
82602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.3736582602
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.4147149743
Short name T620
Test name
Test status
Simulation time 121860882097 ps
CPU time 1925.57 seconds
Started Apr 02 01:01:15 PM PDT 24
Finished Apr 02 01:33:24 PM PDT 24
Peak memory 285276 kb
Host smart-c0a5cf20-9e21-4989-88fa-d81865118cdf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147149743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.4147149743
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.1260077807
Short name T207
Test name
Test status
Simulation time 57611952 ps
CPU time 2.3 seconds
Started Apr 02 01:01:22 PM PDT 24
Finished Apr 02 01:01:26 PM PDT 24
Peak memory 257212 kb
Host smart-f7f2b869-60ce-4f41-a820-321de0bf6fb5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1260077807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.1260077807
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.3244500552
Short name T638
Test name
Test status
Simulation time 16562524095 ps
CPU time 929.18 seconds
Started Apr 02 01:01:33 PM PDT 24
Finished Apr 02 01:17:02 PM PDT 24
Peak memory 265264 kb
Host smart-385a4548-1be1-457f-9326-a07ae3cebd36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244500552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.3244500552
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.593665103
Short name T8
Test name
Test status
Simulation time 311635595 ps
CPU time 9.84 seconds
Started Apr 02 01:01:35 PM PDT 24
Finished Apr 02 01:01:45 PM PDT 24
Peak memory 248736 kb
Host smart-dab85a82-3bc7-49e8-9a0d-7988853d4096
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=593665103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.593665103
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.2155497259
Short name T370
Test name
Test status
Simulation time 97285932 ps
CPU time 7.92 seconds
Started Apr 02 01:01:34 PM PDT 24
Finished Apr 02 01:01:42 PM PDT 24
Peak memory 254104 kb
Host smart-a5b7f930-05bb-4fc6-a175-5c820f5fa707
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21554
97259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.2155497259
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.2316365065
Short name T533
Test name
Test status
Simulation time 1369393173 ps
CPU time 42.89 seconds
Started Apr 02 01:01:29 PM PDT 24
Finished Apr 02 01:02:12 PM PDT 24
Peak memory 256920 kb
Host smart-a53b3491-9908-40d8-84c8-58aff6e60999
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23163
65065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.2316365065
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.1232471438
Short name T332
Test name
Test status
Simulation time 10262752158 ps
CPU time 799.99 seconds
Started Apr 02 01:01:38 PM PDT 24
Finished Apr 02 01:14:58 PM PDT 24
Peak memory 265396 kb
Host smart-8a2dcbee-df23-4b0b-9055-c2aba376e619
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232471438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.1232471438
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.1637130681
Short name T7
Test name
Test status
Simulation time 17611937863 ps
CPU time 1005.5 seconds
Started Apr 02 01:01:30 PM PDT 24
Finished Apr 02 01:18:16 PM PDT 24
Peak memory 281128 kb
Host smart-69fd1113-bed9-443c-a1db-b092068a7a8a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637130681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.1637130681
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.3817804902
Short name T1
Test name
Test status
Simulation time 12348254720 ps
CPU time 263.03 seconds
Started Apr 02 01:01:12 PM PDT 24
Finished Apr 02 01:05:41 PM PDT 24
Peak memory 248032 kb
Host smart-b0ae0217-6a24-46aa-921a-071747d2ab22
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817804902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.3817804902
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.2578886327
Short name T486
Test name
Test status
Simulation time 3013441054 ps
CPU time 53.75 seconds
Started Apr 02 01:01:26 PM PDT 24
Finished Apr 02 01:02:20 PM PDT 24
Peak memory 249292 kb
Host smart-160fcb8e-3dfd-4d88-949c-340e38d19825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25788
86327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.2578886327
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.2304408687
Short name T559
Test name
Test status
Simulation time 458638614 ps
CPU time 31.34 seconds
Started Apr 02 01:01:32 PM PDT 24
Finished Apr 02 01:02:03 PM PDT 24
Peak memory 256224 kb
Host smart-3200212d-d3f6-466a-96f7-9c468a0cf965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23044
08687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.2304408687
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.192954118
Short name T592
Test name
Test status
Simulation time 3591626853 ps
CPU time 59.48 seconds
Started Apr 02 01:01:11 PM PDT 24
Finished Apr 02 01:02:16 PM PDT 24
Peak memory 248964 kb
Host smart-b0a06eb4-5660-4540-a249-f43b5aa4237d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19295
4118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.192954118
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.92668651
Short name T489
Test name
Test status
Simulation time 34200787 ps
CPU time 3.41 seconds
Started Apr 02 01:01:26 PM PDT 24
Finished Apr 02 01:01:30 PM PDT 24
Peak memory 240676 kb
Host smart-6509e45d-9648-481e-aa9a-d0b6af4d4ef3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92668
651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.92668651
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.1730295838
Short name T43
Test name
Test status
Simulation time 96502157836 ps
CPU time 1872.68 seconds
Started Apr 02 01:01:13 PM PDT 24
Finished Apr 02 01:32:31 PM PDT 24
Peak memory 303492 kb
Host smart-5b449766-0611-44c4-be76-eb1c9d67f364
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730295838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.1730295838
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.2038856864
Short name T613
Test name
Test status
Simulation time 23873725065 ps
CPU time 876.49 seconds
Started Apr 02 01:01:35 PM PDT 24
Finished Apr 02 01:16:11 PM PDT 24
Peak memory 288720 kb
Host smart-8b03ab12-94c9-4ce4-9281-b777fc1ac20d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038856864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.2038856864
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.786986233
Short name T400
Test name
Test status
Simulation time 956611264 ps
CPU time 14.14 seconds
Started Apr 02 01:01:18 PM PDT 24
Finished Apr 02 01:01:33 PM PDT 24
Peak memory 240668 kb
Host smart-2ade1b82-7c3c-4a8f-83da-d7d5a28d1295
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=786986233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.786986233
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.4105626764
Short name T488
Test name
Test status
Simulation time 48395222260 ps
CPU time 276.3 seconds
Started Apr 02 01:01:12 PM PDT 24
Finished Apr 02 01:05:54 PM PDT 24
Peak memory 256752 kb
Host smart-5e56dfb9-9ae3-4b74-b961-1be0746b5400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41056
26764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.4105626764
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.3750893744
Short name T591
Test name
Test status
Simulation time 1429189079 ps
CPU time 42.6 seconds
Started Apr 02 01:01:08 PM PDT 24
Finished Apr 02 01:01:56 PM PDT 24
Peak memory 249236 kb
Host smart-50b25e61-25dc-488e-b435-3fbddcc2c58d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37508
93744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.3750893744
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.1895166025
Short name T660
Test name
Test status
Simulation time 275501098 ps
CPU time 22.53 seconds
Started Apr 02 01:01:25 PM PDT 24
Finished Apr 02 01:01:49 PM PDT 24
Peak memory 256080 kb
Host smart-a298145f-f40a-45ad-adc1-134080c84c3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18951
66025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.1895166025
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.3351417286
Short name T440
Test name
Test status
Simulation time 111531340 ps
CPU time 3.04 seconds
Started Apr 02 01:01:10 PM PDT 24
Finished Apr 02 01:01:19 PM PDT 24
Peak memory 239208 kb
Host smart-b6e1bec4-6779-44a6-8da2-34ff86d747a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33514
17286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.3351417286
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.3013575112
Short name T248
Test name
Test status
Simulation time 3021012349 ps
CPU time 17.23 seconds
Started Apr 02 01:01:17 PM PDT 24
Finished Apr 02 01:01:36 PM PDT 24
Peak memory 248948 kb
Host smart-bb291319-caea-42f1-81a2-e0da3880e2f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30135
75112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.3013575112
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.1504518339
Short name T382
Test name
Test status
Simulation time 69277454 ps
CPU time 2.89 seconds
Started Apr 02 01:01:17 PM PDT 24
Finished Apr 02 01:01:22 PM PDT 24
Peak memory 240684 kb
Host smart-ea546b2c-496f-4a49-a121-c13a42ada14c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15045
18339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.1504518339
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.3497079891
Short name T200
Test name
Test status
Simulation time 9517108536 ps
CPU time 166.67 seconds
Started Apr 02 01:01:27 PM PDT 24
Finished Apr 02 01:04:14 PM PDT 24
Peak memory 250188 kb
Host smart-75e25e3a-0d0d-43ac-9f28-ac8dc47a537f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497079891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.3497079891
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.3385609379
Short name T22
Test name
Test status
Simulation time 249029428 ps
CPU time 3.1 seconds
Started Apr 02 01:00:37 PM PDT 24
Finished Apr 02 01:00:41 PM PDT 24
Peak memory 249100 kb
Host smart-b2c2ed2f-46f0-404d-9380-1f5a2cc6cc4a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3385609379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.3385609379
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.727492754
Short name T593
Test name
Test status
Simulation time 1066148684 ps
CPU time 44.61 seconds
Started Apr 02 01:00:32 PM PDT 24
Finished Apr 02 01:01:17 PM PDT 24
Peak memory 240616 kb
Host smart-b6502494-18df-4c41-81a7-b780f1ac85a8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=727492754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.727492754
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.1378386659
Short name T674
Test name
Test status
Simulation time 21311289208 ps
CPU time 262.96 seconds
Started Apr 02 01:00:41 PM PDT 24
Finished Apr 02 01:05:04 PM PDT 24
Peak memory 255720 kb
Host smart-38d4c722-b713-4119-87ec-3188d5978018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13783
86659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.1378386659
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.1762336600
Short name T401
Test name
Test status
Simulation time 255699778 ps
CPU time 13.96 seconds
Started Apr 02 01:00:48 PM PDT 24
Finished Apr 02 01:01:02 PM PDT 24
Peak memory 254800 kb
Host smart-4d6166fe-46a5-4a0f-8cea-31334b32adc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17623
36600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.1762336600
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.3943248364
Short name T711
Test name
Test status
Simulation time 175468429944 ps
CPU time 2462.01 seconds
Started Apr 02 01:01:10 PM PDT 24
Finished Apr 02 01:42:19 PM PDT 24
Peak memory 288844 kb
Host smart-847d8053-4ce9-425d-9d03-a27e873fbd70
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943248364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.3943248364
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.891622679
Short name T623
Test name
Test status
Simulation time 110088425487 ps
CPU time 1582.11 seconds
Started Apr 02 01:00:46 PM PDT 24
Finished Apr 02 01:27:09 PM PDT 24
Peak memory 273328 kb
Host smart-2d7e5b71-5c7a-4e03-807a-9c6397c20fa6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891622679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.891622679
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.2378025546
Short name T313
Test name
Test status
Simulation time 11144982312 ps
CPU time 339 seconds
Started Apr 02 01:00:47 PM PDT 24
Finished Apr 02 01:06:33 PM PDT 24
Peak memory 247916 kb
Host smart-82a3a798-9fd9-4b50-b899-fdd2f67b1b6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378025546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.2378025546
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.3533143624
Short name T2
Test name
Test status
Simulation time 263498860 ps
CPU time 29.25 seconds
Started Apr 02 01:01:06 PM PDT 24
Finished Apr 02 01:01:39 PM PDT 24
Peak memory 248924 kb
Host smart-e67663be-995e-4bf0-a578-421fe98c8c9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35331
43624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.3533143624
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.125186137
Short name T588
Test name
Test status
Simulation time 465411752 ps
CPU time 28.15 seconds
Started Apr 02 01:00:51 PM PDT 24
Finished Apr 02 01:01:22 PM PDT 24
Peak memory 248884 kb
Host smart-03fe5258-753e-4413-9b30-3f0d21941fe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12518
6137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.125186137
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.4091838681
Short name T12
Test name
Test status
Simulation time 479807784 ps
CPU time 25.87 seconds
Started Apr 02 01:00:53 PM PDT 24
Finished Apr 02 01:01:22 PM PDT 24
Peak memory 271016 kb
Host smart-8b1263a0-b8ae-4883-9a76-92df5e81e7ff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4091838681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.4091838681
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.2649848230
Short name T666
Test name
Test status
Simulation time 61945513 ps
CPU time 4.3 seconds
Started Apr 02 01:00:47 PM PDT 24
Finished Apr 02 01:00:52 PM PDT 24
Peak memory 238904 kb
Host smart-9b6dee61-80bf-4951-89c0-a2d77e866cf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26498
48230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.2649848230
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.843960923
Short name T229
Test name
Test status
Simulation time 1523651332 ps
CPU time 19.41 seconds
Started Apr 02 01:01:01 PM PDT 24
Finished Apr 02 01:01:23 PM PDT 24
Peak memory 253532 kb
Host smart-949e482d-bce2-4f6a-bfab-c199672abd5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84396
0923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.843960923
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.120076770
Short name T77
Test name
Test status
Simulation time 16613109690 ps
CPU time 1253.51 seconds
Started Apr 02 01:00:45 PM PDT 24
Finished Apr 02 01:21:39 PM PDT 24
Peak memory 289384 kb
Host smart-3691fc29-92f6-4bb7-9827-7a053e6eb1e9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120076770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_hand
ler_stress_all.120076770
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.607416618
Short name T28
Test name
Test status
Simulation time 12356798802 ps
CPU time 1497.66 seconds
Started Apr 02 01:01:28 PM PDT 24
Finished Apr 02 01:26:26 PM PDT 24
Peak memory 289916 kb
Host smart-1f9db33d-d7c5-4c39-b348-d56128266e69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607416618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.607416618
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.223257571
Short name T698
Test name
Test status
Simulation time 6612367586 ps
CPU time 135.81 seconds
Started Apr 02 01:01:18 PM PDT 24
Finished Apr 02 01:03:35 PM PDT 24
Peak memory 257116 kb
Host smart-740e27e4-149c-43db-bf10-28596ab65b65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22325
7571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.223257571
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.1858847354
Short name T37
Test name
Test status
Simulation time 31041878260 ps
CPU time 1904.7 seconds
Started Apr 02 01:01:13 PM PDT 24
Finished Apr 02 01:33:03 PM PDT 24
Peak memory 272520 kb
Host smart-8c04618f-df31-4ab5-8602-242238cd91bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858847354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1858847354
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.858590139
Short name T111
Test name
Test status
Simulation time 23215137626 ps
CPU time 1365.62 seconds
Started Apr 02 01:01:14 PM PDT 24
Finished Apr 02 01:24:04 PM PDT 24
Peak memory 288096 kb
Host smart-0fb6f209-0f4d-42d6-a2c5-46858a22bf63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858590139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.858590139
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.74020449
Short name T528
Test name
Test status
Simulation time 40764345211 ps
CPU time 457.01 seconds
Started Apr 02 01:01:13 PM PDT 24
Finished Apr 02 01:08:55 PM PDT 24
Peak memory 248184 kb
Host smart-96a8bd4e-f2ef-4aa9-9ae6-cd35ec508a2f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74020449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.74020449
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.1589732057
Short name T497
Test name
Test status
Simulation time 283399157 ps
CPU time 21.7 seconds
Started Apr 02 01:01:23 PM PDT 24
Finished Apr 02 01:01:46 PM PDT 24
Peak memory 248732 kb
Host smart-3bcf2c66-2e32-4a37-aeb1-8134a2089e41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15897
32057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.1589732057
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.1845702124
Short name T232
Test name
Test status
Simulation time 780344067 ps
CPU time 35.78 seconds
Started Apr 02 01:01:27 PM PDT 24
Finished Apr 02 01:02:03 PM PDT 24
Peak memory 255852 kb
Host smart-b8e1db52-4d75-4d1f-9423-4b80b9a1961c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18457
02124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.1845702124
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.3307162727
Short name T258
Test name
Test status
Simulation time 364729093 ps
CPU time 10.39 seconds
Started Apr 02 01:01:24 PM PDT 24
Finished Apr 02 01:01:36 PM PDT 24
Peak memory 254428 kb
Host smart-ee3d868c-bfa0-4c12-b1c1-e9af627f89a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33071
62727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.3307162727
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.3247378727
Short name T586
Test name
Test status
Simulation time 8550479050 ps
CPU time 51.87 seconds
Started Apr 02 01:01:08 PM PDT 24
Finished Apr 02 01:02:05 PM PDT 24
Peak memory 249020 kb
Host smart-fd4c8e10-229b-4e06-8c22-abaac943396c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32473
78727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.3247378727
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.252925593
Short name T45
Test name
Test status
Simulation time 26577976475 ps
CPU time 1529.69 seconds
Started Apr 02 01:01:27 PM PDT 24
Finished Apr 02 01:26:57 PM PDT 24
Peak memory 289856 kb
Host smart-de699fca-949f-44e3-a743-9cb10a7ab0cf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252925593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_han
dler_stress_all.252925593
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.3785466697
Short name T42
Test name
Test status
Simulation time 61212072661 ps
CPU time 900.7 seconds
Started Apr 02 01:01:13 PM PDT 24
Finished Apr 02 01:16:19 PM PDT 24
Peak memory 272864 kb
Host smart-a2e6b978-0e94-4575-8948-5becce6fe38d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785466697 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.3785466697
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.2410843664
Short name T608
Test name
Test status
Simulation time 166978954995 ps
CPU time 2943.02 seconds
Started Apr 02 01:01:16 PM PDT 24
Finished Apr 02 01:50:22 PM PDT 24
Peak memory 289560 kb
Host smart-56df85bc-5b9d-407a-b6e7-ed24b8dff85e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410843664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.2410843664
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.2099774606
Short name T451
Test name
Test status
Simulation time 1263490381 ps
CPU time 81.93 seconds
Started Apr 02 01:01:26 PM PDT 24
Finished Apr 02 01:02:48 PM PDT 24
Peak memory 248928 kb
Host smart-5a098e29-8e2a-4def-b2a4-1587dccabfa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20997
74606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.2099774606
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.3898726478
Short name T548
Test name
Test status
Simulation time 100414597 ps
CPU time 3.41 seconds
Started Apr 02 01:01:47 PM PDT 24
Finished Apr 02 01:01:51 PM PDT 24
Peak memory 240700 kb
Host smart-ccfa1387-106b-4034-8361-aec03f1225b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38987
26478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.3898726478
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.2824269612
Short name T648
Test name
Test status
Simulation time 40714242917 ps
CPU time 1216.92 seconds
Started Apr 02 01:01:21 PM PDT 24
Finished Apr 02 01:21:39 PM PDT 24
Peak memory 265328 kb
Host smart-40cc67f8-9322-47ed-9c90-9ac54386ade6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824269612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.2824269612
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.442649636
Short name T428
Test name
Test status
Simulation time 12167478722 ps
CPU time 1705.63 seconds
Started Apr 02 01:01:32 PM PDT 24
Finished Apr 02 01:29:58 PM PDT 24
Peak memory 288708 kb
Host smart-20c2b815-1485-4fe6-87ed-2f18536a817b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442649636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.442649636
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.1548381034
Short name T315
Test name
Test status
Simulation time 9866658263 ps
CPU time 92.88 seconds
Started Apr 02 01:01:16 PM PDT 24
Finished Apr 02 01:02:52 PM PDT 24
Peak memory 247084 kb
Host smart-b7495edd-540c-471c-b7a0-2480b5aaacce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548381034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.1548381034
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.543036903
Short name T633
Test name
Test status
Simulation time 1056956119 ps
CPU time 16.82 seconds
Started Apr 02 01:01:37 PM PDT 24
Finished Apr 02 01:01:54 PM PDT 24
Peak memory 255200 kb
Host smart-9ca73a75-e9f7-445f-ac9a-3c44bb0e6167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54303
6903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.543036903
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.615510262
Short name T449
Test name
Test status
Simulation time 4073866404 ps
CPU time 63.43 seconds
Started Apr 02 01:01:15 PM PDT 24
Finished Apr 02 01:02:22 PM PDT 24
Peak memory 256196 kb
Host smart-97c7a548-b6e2-4326-973e-34a91d2e92c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61551
0262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.615510262
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.425945161
Short name T679
Test name
Test status
Simulation time 217496726 ps
CPU time 23.63 seconds
Started Apr 02 01:01:14 PM PDT 24
Finished Apr 02 01:01:42 PM PDT 24
Peak memory 254684 kb
Host smart-679488d0-84c4-421d-b3b4-b489591d8b7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42594
5161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.425945161
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.898028130
Short name T475
Test name
Test status
Simulation time 1001542569 ps
CPU time 30.02 seconds
Started Apr 02 01:01:13 PM PDT 24
Finished Apr 02 01:01:48 PM PDT 24
Peak memory 248876 kb
Host smart-78c451a7-cb52-46c0-9e85-971ff3e741e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89802
8130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.898028130
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.1579569689
Short name T551
Test name
Test status
Simulation time 10319615228 ps
CPU time 670.47 seconds
Started Apr 02 01:01:19 PM PDT 24
Finished Apr 02 01:12:30 PM PDT 24
Peak memory 273544 kb
Host smart-552a4d0e-9fe1-40fa-834b-f066538fe14c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579569689 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.1579569689
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.1442058231
Short name T693
Test name
Test status
Simulation time 7994037544 ps
CPU time 871.69 seconds
Started Apr 02 01:01:24 PM PDT 24
Finished Apr 02 01:15:58 PM PDT 24
Peak memory 272912 kb
Host smart-03c8c8e1-5e80-4ab3-8f3a-5ea5978ede1f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442058231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.1442058231
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.2217266104
Short name T383
Test name
Test status
Simulation time 3967771403 ps
CPU time 31.94 seconds
Started Apr 02 01:01:17 PM PDT 24
Finished Apr 02 01:01:51 PM PDT 24
Peak memory 254784 kb
Host smart-7a03310b-67c0-490b-a267-189990277748
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22172
66104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.2217266104
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.1298489989
Short name T446
Test name
Test status
Simulation time 1653401974 ps
CPU time 29.39 seconds
Started Apr 02 01:01:15 PM PDT 24
Finished Apr 02 01:01:48 PM PDT 24
Peak memory 254872 kb
Host smart-e663df2d-4e61-4fbe-aa24-c4f54fdf8741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12984
89989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.1298489989
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.546590324
Short name T684
Test name
Test status
Simulation time 72582536319 ps
CPU time 2233.15 seconds
Started Apr 02 01:01:15 PM PDT 24
Finished Apr 02 01:38:32 PM PDT 24
Peak memory 286268 kb
Host smart-713ce1f4-8809-46ba-8e5a-7b29e2af9be9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546590324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.546590324
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.1360476442
Short name T376
Test name
Test status
Simulation time 207449736959 ps
CPU time 2888.35 seconds
Started Apr 02 01:01:17 PM PDT 24
Finished Apr 02 01:49:27 PM PDT 24
Peak memory 287116 kb
Host smart-234f3e64-1352-4759-9204-8cbcd9eccef7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360476442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.1360476442
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.3047588007
Short name T325
Test name
Test status
Simulation time 30293903478 ps
CPU time 598.65 seconds
Started Apr 02 01:01:16 PM PDT 24
Finished Apr 02 01:11:17 PM PDT 24
Peak memory 247088 kb
Host smart-3135c886-c6df-4485-a104-78ddbb5d335c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047588007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.3047588007
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.3530337416
Short name T241
Test name
Test status
Simulation time 4260411736 ps
CPU time 65.53 seconds
Started Apr 02 01:01:17 PM PDT 24
Finished Apr 02 01:02:24 PM PDT 24
Peak memory 248912 kb
Host smart-e880b86a-2364-4cd4-bf8f-1e081780ceb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35303
37416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.3530337416
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.487055511
Short name T411
Test name
Test status
Simulation time 752043221 ps
CPU time 27.39 seconds
Started Apr 02 01:01:19 PM PDT 24
Finished Apr 02 01:01:46 PM PDT 24
Peak memory 248380 kb
Host smart-c9b16432-2bdd-4096-8f30-c3678aa49691
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48705
5511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.487055511
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.1606301922
Short name T68
Test name
Test status
Simulation time 3546174921 ps
CPU time 60.54 seconds
Started Apr 02 01:01:27 PM PDT 24
Finished Apr 02 01:02:27 PM PDT 24
Peak memory 256340 kb
Host smart-acaa2319-2319-4ee8-b694-5ef243ca4d5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16063
01922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.1606301922
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.2480261306
Short name T502
Test name
Test status
Simulation time 136816273 ps
CPU time 11.19 seconds
Started Apr 02 01:01:23 PM PDT 24
Finished Apr 02 01:01:36 PM PDT 24
Peak memory 248832 kb
Host smart-2cbe3d26-4b96-4338-b81d-6757d9240fa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24802
61306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.2480261306
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.164698555
Short name T288
Test name
Test status
Simulation time 8928718399 ps
CPU time 830.38 seconds
Started Apr 02 01:01:20 PM PDT 24
Finished Apr 02 01:15:11 PM PDT 24
Peak memory 273536 kb
Host smart-8132f462-8a73-48d8-a424-cd050d0c0232
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164698555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_han
dler_stress_all.164698555
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.4196814952
Short name T75
Test name
Test status
Simulation time 258691678861 ps
CPU time 4225.43 seconds
Started Apr 02 01:01:22 PM PDT 24
Finished Apr 02 02:11:49 PM PDT 24
Peak memory 288008 kb
Host smart-968e51d7-3675-45b0-aa16-73fa15c7b4ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196814952 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.4196814952
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.440631101
Short name T582
Test name
Test status
Simulation time 41345078698 ps
CPU time 2449.6 seconds
Started Apr 02 01:01:32 PM PDT 24
Finished Apr 02 01:42:22 PM PDT 24
Peak memory 289472 kb
Host smart-091cea58-6940-4cc3-851f-5a538a192d78
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440631101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.440631101
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.44334735
Short name T89
Test name
Test status
Simulation time 2030309316 ps
CPU time 80.5 seconds
Started Apr 02 01:01:21 PM PDT 24
Finished Apr 02 01:02:43 PM PDT 24
Peak memory 256676 kb
Host smart-fec8b39e-3c5d-4d69-bc8e-bcd2997ae413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44334
735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.44334735
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.4020500031
Short name T185
Test name
Test status
Simulation time 63567310 ps
CPU time 8.25 seconds
Started Apr 02 01:01:35 PM PDT 24
Finished Apr 02 01:01:43 PM PDT 24
Peak memory 251880 kb
Host smart-9b4dcb9a-6b4c-403e-9520-90fb1d38c5fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40205
00031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.4020500031
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.2590124254
Short name T300
Test name
Test status
Simulation time 26781673295 ps
CPU time 665.3 seconds
Started Apr 02 01:01:21 PM PDT 24
Finished Apr 02 01:12:29 PM PDT 24
Peak memory 265456 kb
Host smart-86eb19f9-4090-435a-a5ba-9f4e3e5db962
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590124254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.2590124254
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.1505521189
Short name T293
Test name
Test status
Simulation time 17038520315 ps
CPU time 1273.37 seconds
Started Apr 02 01:01:28 PM PDT 24
Finished Apr 02 01:22:42 PM PDT 24
Peak memory 281680 kb
Host smart-ae55433e-e267-4d7f-a2b1-3731043e516c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505521189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.1505521189
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.302893585
Short name T314
Test name
Test status
Simulation time 3150083093 ps
CPU time 141.84 seconds
Started Apr 02 01:01:27 PM PDT 24
Finished Apr 02 01:03:49 PM PDT 24
Peak memory 247944 kb
Host smart-b8111ef4-1410-4408-b996-ca6a2b3a1c10
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302893585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.302893585
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.465240366
Short name T523
Test name
Test status
Simulation time 871167717 ps
CPU time 59 seconds
Started Apr 02 01:01:21 PM PDT 24
Finished Apr 02 01:02:21 PM PDT 24
Peak memory 256032 kb
Host smart-90d194b5-de8e-4764-a216-98476a4c3749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46524
0366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.465240366
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.3126531381
Short name T563
Test name
Test status
Simulation time 1725589574 ps
CPU time 18.08 seconds
Started Apr 02 01:01:22 PM PDT 24
Finished Apr 02 01:01:42 PM PDT 24
Peak memory 255424 kb
Host smart-a336c35a-2934-49ee-b1c0-1484e686859b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31265
31381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.3126531381
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.260635408
Short name T201
Test name
Test status
Simulation time 182848410 ps
CPU time 27.03 seconds
Started Apr 02 01:01:27 PM PDT 24
Finished Apr 02 01:01:54 PM PDT 24
Peak memory 247816 kb
Host smart-f9ddd859-29f1-46fd-b5ed-78f93b2456d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26063
5408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.260635408
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.3577218189
Short name T468
Test name
Test status
Simulation time 509542844 ps
CPU time 28.06 seconds
Started Apr 02 01:01:17 PM PDT 24
Finished Apr 02 01:01:47 PM PDT 24
Peak memory 248908 kb
Host smart-cc044f70-4f05-4f4f-9e31-352a8c2284e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35772
18189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.3577218189
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.2345923766
Short name T249
Test name
Test status
Simulation time 631935936722 ps
CPU time 2954.87 seconds
Started Apr 02 01:01:27 PM PDT 24
Finished Apr 02 01:50:42 PM PDT 24
Peak memory 289168 kb
Host smart-291c8a52-a1e6-467c-847b-b09be2da1576
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345923766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.2345923766
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.987962468
Short name T180
Test name
Test status
Simulation time 95629523626 ps
CPU time 3195.21 seconds
Started Apr 02 01:01:17 PM PDT 24
Finished Apr 02 01:54:34 PM PDT 24
Peak memory 289840 kb
Host smart-10a5a8c8-d511-4ffe-9af3-064b3e6e581b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987962468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.987962468
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.759875144
Short name T625
Test name
Test status
Simulation time 2981628506 ps
CPU time 104.94 seconds
Started Apr 02 01:01:41 PM PDT 24
Finished Apr 02 01:03:26 PM PDT 24
Peak memory 256728 kb
Host smart-ccea51aa-fdec-4805-ad01-ee111656e82c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75987
5144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.759875144
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.2998310626
Short name T506
Test name
Test status
Simulation time 1078600447 ps
CPU time 52.8 seconds
Started Apr 02 01:01:32 PM PDT 24
Finished Apr 02 01:02:25 PM PDT 24
Peak memory 248712 kb
Host smart-5247cacf-3ceb-41ac-bd9d-baa30586357b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29983
10626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2998310626
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.815379134
Short name T664
Test name
Test status
Simulation time 373257653752 ps
CPU time 1501.63 seconds
Started Apr 02 01:01:21 PM PDT 24
Finished Apr 02 01:26:24 PM PDT 24
Peak memory 267320 kb
Host smart-271880ec-28e5-4b02-8c12-097ac0fe35ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815379134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.815379134
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.2893876421
Short name T81
Test name
Test status
Simulation time 327473963789 ps
CPU time 2516.86 seconds
Started Apr 02 01:01:22 PM PDT 24
Finished Apr 02 01:43:21 PM PDT 24
Peak memory 282432 kb
Host smart-dfe8cc97-a2c3-45c0-a50f-bb24b6fda34e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893876421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.2893876421
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.1997039668
Short name T525
Test name
Test status
Simulation time 1705472243 ps
CPU time 26 seconds
Started Apr 02 01:01:20 PM PDT 24
Finished Apr 02 01:01:46 PM PDT 24
Peak memory 248872 kb
Host smart-44211356-5d97-467b-9e9c-3d9034c48d1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19970
39668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.1997039668
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.3775476206
Short name T416
Test name
Test status
Simulation time 665513065 ps
CPU time 42.35 seconds
Started Apr 02 01:01:22 PM PDT 24
Finished Apr 02 01:02:05 PM PDT 24
Peak memory 255412 kb
Host smart-d9030948-e992-488c-817d-4fbef8bc9da1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37754
76206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.3775476206
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.535676721
Short name T717
Test name
Test status
Simulation time 863459916 ps
CPU time 28.31 seconds
Started Apr 02 01:01:14 PM PDT 24
Finished Apr 02 01:01:47 PM PDT 24
Peak memory 248812 kb
Host smart-458b60c0-daa6-4998-9c4f-15e72e112e4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53567
6721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.535676721
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.2534747886
Short name T48
Test name
Test status
Simulation time 137947146719 ps
CPU time 1688.97 seconds
Started Apr 02 01:01:24 PM PDT 24
Finished Apr 02 01:29:35 PM PDT 24
Peak memory 289576 kb
Host smart-5d8eeec3-f328-4de0-b8ac-11018ad58024
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534747886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.2534747886
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.1351932580
Short name T419
Test name
Test status
Simulation time 16756089951 ps
CPU time 778.27 seconds
Started Apr 02 01:01:23 PM PDT 24
Finished Apr 02 01:14:22 PM PDT 24
Peak memory 265324 kb
Host smart-ffd50152-4fdd-45fe-842b-33b3ff726b75
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351932580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.1351932580
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.2129341168
Short name T677
Test name
Test status
Simulation time 1778651143 ps
CPU time 122.83 seconds
Started Apr 02 01:01:20 PM PDT 24
Finished Apr 02 01:03:23 PM PDT 24
Peak memory 256708 kb
Host smart-b5882916-b9fa-44f8-a7b3-34bd5c0f1b6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21293
41168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.2129341168
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.488388084
Short name T637
Test name
Test status
Simulation time 773018571 ps
CPU time 46.79 seconds
Started Apr 02 01:01:19 PM PDT 24
Finished Apr 02 01:02:06 PM PDT 24
Peak memory 254932 kb
Host smart-b0c2aff9-35d0-411a-b1bc-40c48a986b0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48838
8084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.488388084
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.3854288707
Short name T691
Test name
Test status
Simulation time 36006556568 ps
CPU time 880.21 seconds
Started Apr 02 01:01:36 PM PDT 24
Finished Apr 02 01:16:16 PM PDT 24
Peak memory 272644 kb
Host smart-208b215e-74cf-4ccd-b2b9-23006c0e39ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854288707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.3854288707
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.547620756
Short name T328
Test name
Test status
Simulation time 196922145334 ps
CPU time 1571.28 seconds
Started Apr 02 01:01:32 PM PDT 24
Finished Apr 02 01:27:43 PM PDT 24
Peak memory 273588 kb
Host smart-e3bc5888-99a1-4816-91bf-fa976f1726d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547620756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.547620756
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.2761141973
Short name T565
Test name
Test status
Simulation time 20984088238 ps
CPU time 451.93 seconds
Started Apr 02 01:01:35 PM PDT 24
Finished Apr 02 01:09:07 PM PDT 24
Peak memory 248092 kb
Host smart-38145e8c-2613-42d1-b0c0-fab22f7b82e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761141973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.2761141973
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.961615033
Short name T403
Test name
Test status
Simulation time 1638182903 ps
CPU time 22.46 seconds
Started Apr 02 01:01:30 PM PDT 24
Finished Apr 02 01:01:52 PM PDT 24
Peak memory 248616 kb
Host smart-9dc1c29c-be88-4171-b3e3-145b6266dd2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96161
5033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.961615033
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.2505372286
Short name T3
Test name
Test status
Simulation time 1054573833 ps
CPU time 39.88 seconds
Started Apr 02 01:01:18 PM PDT 24
Finished Apr 02 01:01:59 PM PDT 24
Peak memory 256588 kb
Host smart-693fa212-2aa6-4db8-bef0-00b660a0f375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25053
72286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.2505372286
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.3067803327
Short name T64
Test name
Test status
Simulation time 2383496941 ps
CPU time 54.37 seconds
Started Apr 02 01:01:46 PM PDT 24
Finished Apr 02 01:02:40 PM PDT 24
Peak memory 255476 kb
Host smart-42cc65b4-9458-46fa-856e-61f2e6578aa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30678
03327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.3067803327
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.1575540252
Short name T448
Test name
Test status
Simulation time 967743971 ps
CPU time 31.49 seconds
Started Apr 02 01:01:19 PM PDT 24
Finished Apr 02 01:01:50 PM PDT 24
Peak memory 248892 kb
Host smart-47771e77-edf4-4bd8-bba5-2d4eb9fc4788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15755
40252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.1575540252
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.2136164508
Short name T197
Test name
Test status
Simulation time 139599496331 ps
CPU time 2355.68 seconds
Started Apr 02 01:01:18 PM PDT 24
Finished Apr 02 01:40:35 PM PDT 24
Peak memory 289648 kb
Host smart-52fec9c0-e653-44fa-91dc-ebc33258fcf6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136164508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.2136164508
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.1503390467
Short name T692
Test name
Test status
Simulation time 202382910906 ps
CPU time 2446.73 seconds
Started Apr 02 01:01:38 PM PDT 24
Finished Apr 02 01:42:25 PM PDT 24
Peak memory 281792 kb
Host smart-f4fcaa92-30e0-41f2-9c68-907c3a670a3b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503390467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.1503390467
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.686899802
Short name T598
Test name
Test status
Simulation time 3514019162 ps
CPU time 189.15 seconds
Started Apr 02 01:02:21 PM PDT 24
Finished Apr 02 01:05:31 PM PDT 24
Peak memory 256372 kb
Host smart-399f2ab7-a15f-456d-afe2-d5a9d98430b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68689
9802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.686899802
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.2522334667
Short name T652
Test name
Test status
Simulation time 863803446 ps
CPU time 51.32 seconds
Started Apr 02 01:01:36 PM PDT 24
Finished Apr 02 01:02:27 PM PDT 24
Peak memory 256000 kb
Host smart-e1013212-1dbb-486a-a3d4-0c5b54551018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25223
34667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.2522334667
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.881270762
Short name T238
Test name
Test status
Simulation time 39396949784 ps
CPU time 856.92 seconds
Started Apr 02 01:01:27 PM PDT 24
Finished Apr 02 01:15:44 PM PDT 24
Peak memory 272796 kb
Host smart-6f8aa53d-3008-477c-9151-d0a91c752c79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881270762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.881270762
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.4145091564
Short name T456
Test name
Test status
Simulation time 58301981903 ps
CPU time 1228.59 seconds
Started Apr 02 01:01:29 PM PDT 24
Finished Apr 02 01:21:58 PM PDT 24
Peak memory 289388 kb
Host smart-50349824-04d2-407f-a2d2-24337d953079
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145091564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.4145091564
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.400314332
Short name T275
Test name
Test status
Simulation time 8273659726 ps
CPU time 330.85 seconds
Started Apr 02 01:01:25 PM PDT 24
Finished Apr 02 01:06:57 PM PDT 24
Peak memory 247360 kb
Host smart-83e556a2-9e24-474f-8fa0-9a56d111a44a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400314332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.400314332
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.2113000538
Short name T632
Test name
Test status
Simulation time 1541179357 ps
CPU time 26.28 seconds
Started Apr 02 01:01:19 PM PDT 24
Finished Apr 02 01:01:47 PM PDT 24
Peak memory 257092 kb
Host smart-aa0cf2ce-dcae-4488-b5a0-17a8130ecf82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21130
00538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.2113000538
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.3182277790
Short name T558
Test name
Test status
Simulation time 291168595 ps
CPU time 9.7 seconds
Started Apr 02 01:01:24 PM PDT 24
Finished Apr 02 01:01:35 PM PDT 24
Peak memory 251624 kb
Host smart-01b14a2b-9120-4cea-908e-c87f29dda556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31822
77790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.3182277790
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.1803483282
Short name T492
Test name
Test status
Simulation time 3340947520 ps
CPU time 69.88 seconds
Started Apr 02 01:01:21 PM PDT 24
Finished Apr 02 01:02:32 PM PDT 24
Peak memory 256716 kb
Host smart-13fdd252-1b74-45a1-b500-c1b84bc6cf13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18034
83282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.1803483282
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.3122696845
Short name T39
Test name
Test status
Simulation time 3674081726 ps
CPU time 61.32 seconds
Started Apr 02 01:01:26 PM PDT 24
Finished Apr 02 01:02:28 PM PDT 24
Peak memory 256308 kb
Host smart-c14044a9-8d63-49ac-b647-01982533316a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31226
96845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.3122696845
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.1587911235
Short name T297
Test name
Test status
Simulation time 99026674916 ps
CPU time 1305.06 seconds
Started Apr 02 01:01:23 PM PDT 24
Finished Apr 02 01:23:09 PM PDT 24
Peak memory 286832 kb
Host smart-04001ac6-c854-4372-9218-e100e9f7dee9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587911235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.1587911235
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.627018838
Short name T73
Test name
Test status
Simulation time 13354338180 ps
CPU time 1423.3 seconds
Started Apr 02 01:01:35 PM PDT 24
Finished Apr 02 01:25:19 PM PDT 24
Peak memory 289984 kb
Host smart-0e05ac44-8408-4557-9c7f-2dc1a2c31847
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627018838 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.627018838
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.3542559963
Short name T704
Test name
Test status
Simulation time 64467475297 ps
CPU time 768.31 seconds
Started Apr 02 01:01:37 PM PDT 24
Finished Apr 02 01:14:25 PM PDT 24
Peak memory 273484 kb
Host smart-05b8a1f4-106f-4804-9f60-26d7ce0a6225
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542559963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.3542559963
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.2193014678
Short name T281
Test name
Test status
Simulation time 14358298492 ps
CPU time 139.38 seconds
Started Apr 02 01:01:36 PM PDT 24
Finished Apr 02 01:03:55 PM PDT 24
Peak memory 256428 kb
Host smart-9999ffe3-6ae0-4b19-8c72-0c7aa6358ad4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21930
14678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.2193014678
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.3917244929
Short name T611
Test name
Test status
Simulation time 1519876532 ps
CPU time 27.23 seconds
Started Apr 02 01:01:33 PM PDT 24
Finished Apr 02 01:02:01 PM PDT 24
Peak memory 255296 kb
Host smart-c87275b3-5b9b-4005-a6fc-e44ed93d9d88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39172
44929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.3917244929
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.641211115
Short name T476
Test name
Test status
Simulation time 9169251350 ps
CPU time 937.36 seconds
Started Apr 02 01:01:22 PM PDT 24
Finished Apr 02 01:17:00 PM PDT 24
Peak memory 273572 kb
Host smart-e882a340-3d37-4ab7-a051-0f4b783728fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641211115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.641211115
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.1982781039
Short name T631
Test name
Test status
Simulation time 11427291954 ps
CPU time 442.64 seconds
Started Apr 02 01:01:36 PM PDT 24
Finished Apr 02 01:08:59 PM PDT 24
Peak memory 248196 kb
Host smart-fbd92943-9694-49cc-a93e-956b17e485d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982781039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.1982781039
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.2312096990
Short name T268
Test name
Test status
Simulation time 212708453 ps
CPU time 19.69 seconds
Started Apr 02 01:01:35 PM PDT 24
Finished Apr 02 01:01:55 PM PDT 24
Peak memory 248880 kb
Host smart-b9d53201-cd56-41d6-9374-5230a99ede4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23120
96990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.2312096990
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.2534850276
Short name T653
Test name
Test status
Simulation time 1571404131 ps
CPU time 27.14 seconds
Started Apr 02 01:01:35 PM PDT 24
Finished Apr 02 01:02:02 PM PDT 24
Peak memory 255976 kb
Host smart-e1093df1-fba9-4e9d-b698-5576161f3a58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25348
50276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.2534850276
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.1849749940
Short name T110
Test name
Test status
Simulation time 251988621 ps
CPU time 14.54 seconds
Started Apr 02 01:01:31 PM PDT 24
Finished Apr 02 01:01:46 PM PDT 24
Peak memory 247264 kb
Host smart-7abd6d43-9f79-4f33-a0d1-42a324d7faa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18497
49940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.1849749940
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.1113724942
Short name T550
Test name
Test status
Simulation time 87950156 ps
CPU time 7.28 seconds
Started Apr 02 01:01:20 PM PDT 24
Finished Apr 02 01:01:28 PM PDT 24
Peak memory 248852 kb
Host smart-07767858-066a-4a95-b24d-2830880f5bc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11137
24942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.1113724942
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.3286678429
Short name T417
Test name
Test status
Simulation time 115320875048 ps
CPU time 1921.59 seconds
Started Apr 02 01:01:27 PM PDT 24
Finished Apr 02 01:33:29 PM PDT 24
Peak memory 283396 kb
Host smart-41c4e096-0d34-4c9e-9556-59c40438637b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286678429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.3286678429
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.2167140497
Short name T501
Test name
Test status
Simulation time 3426827043 ps
CPU time 91.2 seconds
Started Apr 02 01:01:40 PM PDT 24
Finished Apr 02 01:03:11 PM PDT 24
Peak memory 256680 kb
Host smart-6376c027-2d52-438e-974e-f1f9dfc4fc93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21671
40497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.2167140497
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.530918035
Short name T441
Test name
Test status
Simulation time 2411606754 ps
CPU time 71.05 seconds
Started Apr 02 01:01:27 PM PDT 24
Finished Apr 02 01:02:38 PM PDT 24
Peak memory 248900 kb
Host smart-75e102a2-9a2f-4043-85f3-e040466d3213
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53091
8035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.530918035
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.244037783
Short name T338
Test name
Test status
Simulation time 131300962689 ps
CPU time 2919.76 seconds
Started Apr 02 01:01:38 PM PDT 24
Finished Apr 02 01:50:18 PM PDT 24
Peak memory 289528 kb
Host smart-2cdfe096-2eb1-4ecc-b509-e425707d45bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244037783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.244037783
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.2974441052
Short name T705
Test name
Test status
Simulation time 13836415168 ps
CPU time 1488.19 seconds
Started Apr 02 01:01:24 PM PDT 24
Finished Apr 02 01:26:13 PM PDT 24
Peak memory 288872 kb
Host smart-d50397d5-c2e7-4b7f-90b8-8bf83f21566f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974441052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.2974441052
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.1099009024
Short name T541
Test name
Test status
Simulation time 7541498762 ps
CPU time 278.29 seconds
Started Apr 02 01:01:38 PM PDT 24
Finished Apr 02 01:06:17 PM PDT 24
Peak memory 247020 kb
Host smart-13375cf9-a2c9-4fa9-88e6-928c2780313c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099009024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.1099009024
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2131924821
Short name T521
Test name
Test status
Simulation time 204664471 ps
CPU time 12.21 seconds
Started Apr 02 01:01:23 PM PDT 24
Finished Apr 02 01:01:36 PM PDT 24
Peak memory 254148 kb
Host smart-ea6e3d06-335b-4306-b0fa-8b7f6865dc3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21319
24821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2131924821
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.2762868607
Short name T83
Test name
Test status
Simulation time 190927233 ps
CPU time 16.25 seconds
Started Apr 02 01:01:38 PM PDT 24
Finished Apr 02 01:01:54 PM PDT 24
Peak memory 248888 kb
Host smart-ee2de1d4-9dd3-4a0d-a619-bde06154c336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27628
68607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.2762868607
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.3182089295
Short name T538
Test name
Test status
Simulation time 1222672072 ps
CPU time 18.26 seconds
Started Apr 02 01:01:38 PM PDT 24
Finished Apr 02 01:01:56 PM PDT 24
Peak memory 255604 kb
Host smart-e31009ec-70c1-4863-8bdf-0783e8c8b906
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31820
89295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.3182089295
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.3882693719
Short name T545
Test name
Test status
Simulation time 265722482 ps
CPU time 26.97 seconds
Started Apr 02 01:01:35 PM PDT 24
Finished Apr 02 01:02:03 PM PDT 24
Peak memory 249188 kb
Host smart-a0a6b4ac-30fc-498b-a025-1b3cd2fb2e4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38826
93719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.3882693719
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.2629104690
Short name T199
Test name
Test status
Simulation time 50459991527 ps
CPU time 3166.96 seconds
Started Apr 02 01:01:25 PM PDT 24
Finished Apr 02 01:54:13 PM PDT 24
Peak memory 300956 kb
Host smart-904021d8-cbdf-4881-8b35-b3837d81af0b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629104690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.2629104690
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.589817079
Short name T442
Test name
Test status
Simulation time 6302945604 ps
CPU time 823.24 seconds
Started Apr 02 01:01:23 PM PDT 24
Finished Apr 02 01:15:08 PM PDT 24
Peak memory 268340 kb
Host smart-89cc0706-4a87-469f-8d4a-e0e43104e804
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589817079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.589817079
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.566739136
Short name T509
Test name
Test status
Simulation time 1383463011 ps
CPU time 31.92 seconds
Started Apr 02 01:01:36 PM PDT 24
Finished Apr 02 01:02:08 PM PDT 24
Peak memory 254600 kb
Host smart-f3a4b1ac-6923-455f-9cd0-7e3f52975dc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56673
9136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.566739136
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.3567089813
Short name T402
Test name
Test status
Simulation time 101845568 ps
CPU time 11.43 seconds
Started Apr 02 01:01:37 PM PDT 24
Finished Apr 02 01:01:48 PM PDT 24
Peak memory 248744 kb
Host smart-94a589e8-0c7e-4033-a46b-2d7af937e003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35670
89813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.3567089813
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.311375696
Short name T178
Test name
Test status
Simulation time 24236329877 ps
CPU time 1384.29 seconds
Started Apr 02 01:01:40 PM PDT 24
Finished Apr 02 01:24:44 PM PDT 24
Peak memory 273588 kb
Host smart-a8d25fcc-f51b-4da4-8ecf-c6179fbc6c0c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311375696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.311375696
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.3815972340
Short name T321
Test name
Test status
Simulation time 35850323446 ps
CPU time 385.23 seconds
Started Apr 02 01:01:39 PM PDT 24
Finished Apr 02 01:08:04 PM PDT 24
Peak memory 246896 kb
Host smart-1530914b-1f38-4742-8cee-4706acf05055
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815972340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.3815972340
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.2582927913
Short name T685
Test name
Test status
Simulation time 4154390647 ps
CPU time 51.7 seconds
Started Apr 02 01:01:32 PM PDT 24
Finished Apr 02 01:02:24 PM PDT 24
Peak memory 248876 kb
Host smart-c5ce11b5-1a76-4b70-aa08-e2656498d8f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25829
27913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.2582927913
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.4273641247
Short name T463
Test name
Test status
Simulation time 1294732164 ps
CPU time 34.75 seconds
Started Apr 02 01:01:32 PM PDT 24
Finished Apr 02 01:02:07 PM PDT 24
Peak memory 255124 kb
Host smart-4b841c21-5857-42b7-8636-99a195a904ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42736
41247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.4273641247
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.2599688842
Short name T67
Test name
Test status
Simulation time 127361844 ps
CPU time 15.67 seconds
Started Apr 02 01:01:23 PM PDT 24
Finished Apr 02 01:01:41 PM PDT 24
Peak memory 254952 kb
Host smart-3712308d-22bb-4dc4-a4f9-dcc1490c8d4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25996
88842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.2599688842
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.361442087
Short name T363
Test name
Test status
Simulation time 3916090799 ps
CPU time 71.51 seconds
Started Apr 02 01:01:30 PM PDT 24
Finished Apr 02 01:02:42 PM PDT 24
Peak memory 248924 kb
Host smart-be093390-5c9e-40f7-8fa6-62f2cf5907be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36144
2087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.361442087
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.2623954861
Short name T622
Test name
Test status
Simulation time 23426682454 ps
CPU time 671.29 seconds
Started Apr 02 01:01:40 PM PDT 24
Finished Apr 02 01:12:52 PM PDT 24
Peak memory 256884 kb
Host smart-4e0fe345-82fe-4868-a4ed-1d4cb6463647
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623954861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.2623954861
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.3463387051
Short name T255
Test name
Test status
Simulation time 67781051184 ps
CPU time 1887.84 seconds
Started Apr 02 01:01:26 PM PDT 24
Finished Apr 02 01:32:54 PM PDT 24
Peak memory 298300 kb
Host smart-f546cffa-5e8d-4a93-8a23-baa4f60f81ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463387051 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.3463387051
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.3987089734
Short name T214
Test name
Test status
Simulation time 29653053 ps
CPU time 2.31 seconds
Started Apr 02 01:00:47 PM PDT 24
Finished Apr 02 01:00:50 PM PDT 24
Peak memory 249088 kb
Host smart-86149817-d2ad-4a72-bd6b-03dc8d89bc45
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3987089734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.3987089734
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.2659315429
Short name T574
Test name
Test status
Simulation time 111676088857 ps
CPU time 1232.13 seconds
Started Apr 02 01:00:47 PM PDT 24
Finished Apr 02 01:21:20 PM PDT 24
Peak memory 288320 kb
Host smart-9e046c32-25bb-4896-a0e0-0cdb22f1bc8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659315429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.2659315429
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.1158362693
Short name T432
Test name
Test status
Simulation time 1275415356 ps
CPU time 17.68 seconds
Started Apr 02 01:00:53 PM PDT 24
Finished Apr 02 01:01:14 PM PDT 24
Peak memory 251312 kb
Host smart-0b71fa48-9da4-4cfd-bdb2-907121255bab
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1158362693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1158362693
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.3897209555
Short name T671
Test name
Test status
Simulation time 204021579 ps
CPU time 12.59 seconds
Started Apr 02 01:00:54 PM PDT 24
Finished Apr 02 01:01:09 PM PDT 24
Peak memory 254976 kb
Host smart-c7846fc9-1277-480a-a3e2-92848ba42069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38972
09555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.3897209555
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.1284095788
Short name T360
Test name
Test status
Simulation time 45516853 ps
CPU time 3.96 seconds
Started Apr 02 01:01:00 PM PDT 24
Finished Apr 02 01:01:08 PM PDT 24
Peak memory 239160 kb
Host smart-2b547768-7a4a-4f6d-ad9e-62baa4609964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12840
95788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.1284095788
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.3823622999
Short name T6
Test name
Test status
Simulation time 18754868974 ps
CPU time 1298.65 seconds
Started Apr 02 01:00:52 PM PDT 24
Finished Apr 02 01:22:35 PM PDT 24
Peak memory 265292 kb
Host smart-e81a84b5-b827-4b5d-83e7-e392551ad3d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823622999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.3823622999
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.1733973464
Short name T405
Test name
Test status
Simulation time 30992419373 ps
CPU time 1777.33 seconds
Started Apr 02 01:00:47 PM PDT 24
Finished Apr 02 01:30:24 PM PDT 24
Peak memory 268476 kb
Host smart-43393d99-1f75-4adb-99ef-6ef6cf13e363
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733973464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.1733973464
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.83392049
Short name T31
Test name
Test status
Simulation time 470083515 ps
CPU time 25.9 seconds
Started Apr 02 01:00:36 PM PDT 24
Finished Apr 02 01:01:02 PM PDT 24
Peak memory 255128 kb
Host smart-08ef2c7a-0cfb-49ec-a43e-5e14971cf7e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83392
049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.83392049
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.739139371
Short name T25
Test name
Test status
Simulation time 1991577440 ps
CPU time 23.3 seconds
Started Apr 02 01:00:56 PM PDT 24
Finished Apr 02 01:01:21 PM PDT 24
Peak memory 254928 kb
Host smart-7853d123-1bd5-4f45-9d6c-816feefb7337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73913
9371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.739139371
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.335218855
Short name T650
Test name
Test status
Simulation time 80605300 ps
CPU time 7.28 seconds
Started Apr 02 01:00:53 PM PDT 24
Finished Apr 02 01:01:03 PM PDT 24
Peak memory 248956 kb
Host smart-a02af768-2099-471d-82a9-b2e2923d4355
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33521
8855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.335218855
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.4225334824
Short name T530
Test name
Test status
Simulation time 2296030225 ps
CPU time 32.35 seconds
Started Apr 02 01:00:45 PM PDT 24
Finished Apr 02 01:01:18 PM PDT 24
Peak memory 248972 kb
Host smart-50c08b5b-9bd7-4e3b-a849-8045460c4035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42253
34824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.4225334824
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.113143640
Short name T712
Test name
Test status
Simulation time 12587852564 ps
CPU time 1212.16 seconds
Started Apr 02 01:01:28 PM PDT 24
Finished Apr 02 01:21:40 PM PDT 24
Peak memory 284876 kb
Host smart-18c26e14-a5f2-4c9e-9d9d-4c0b0585bc81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113143640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.113143640
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.2082628100
Short name T225
Test name
Test status
Simulation time 17042118853 ps
CPU time 271.22 seconds
Started Apr 02 01:01:26 PM PDT 24
Finished Apr 02 01:05:57 PM PDT 24
Peak memory 256984 kb
Host smart-3bc6cd1e-670e-4e27-abc7-6b870dc9ee9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20826
28100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.2082628100
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.4277025698
Short name T485
Test name
Test status
Simulation time 159928994 ps
CPU time 16.31 seconds
Started Apr 02 01:01:40 PM PDT 24
Finished Apr 02 01:01:56 PM PDT 24
Peak memory 248908 kb
Host smart-6de95eb7-bf02-48bc-91ac-8dcb471d8d01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42770
25698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.4277025698
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.999516741
Short name T316
Test name
Test status
Simulation time 151479153737 ps
CPU time 2546.89 seconds
Started Apr 02 01:01:38 PM PDT 24
Finished Apr 02 01:44:05 PM PDT 24
Peak memory 289176 kb
Host smart-b7445247-e526-42ed-9b76-140c3fbdbc43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999516741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.999516741
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.3639889623
Short name T413
Test name
Test status
Simulation time 574850693298 ps
CPU time 2774.83 seconds
Started Apr 02 01:01:28 PM PDT 24
Finished Apr 02 01:47:43 PM PDT 24
Peak memory 281208 kb
Host smart-f09b5e78-2b63-42f4-8a79-b9727c6ca89d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639889623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3639889623
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.4126509031
Short name T306
Test name
Test status
Simulation time 9576593134 ps
CPU time 201.59 seconds
Started Apr 02 01:01:28 PM PDT 24
Finished Apr 02 01:04:50 PM PDT 24
Peak memory 247912 kb
Host smart-49319024-e686-488f-b4b9-cc1b63cf9124
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126509031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.4126509031
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.2542963975
Short name T605
Test name
Test status
Simulation time 499003047 ps
CPU time 29.14 seconds
Started Apr 02 01:01:24 PM PDT 24
Finished Apr 02 01:01:54 PM PDT 24
Peak memory 248888 kb
Host smart-61f802fb-f7b6-4b68-99dc-65dc3922bd87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25429
63975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.2542963975
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.2890085028
Short name T547
Test name
Test status
Simulation time 330194133 ps
CPU time 32.12 seconds
Started Apr 02 01:01:28 PM PDT 24
Finished Apr 02 01:02:00 PM PDT 24
Peak memory 254868 kb
Host smart-ed8a9dae-1b94-4652-9a29-2ef3dd6594ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28900
85028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.2890085028
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.4206259732
Short name T430
Test name
Test status
Simulation time 819308316 ps
CPU time 5.04 seconds
Started Apr 02 01:01:27 PM PDT 24
Finished Apr 02 01:01:32 PM PDT 24
Peak memory 239024 kb
Host smart-866722fd-d9c5-4993-8ca9-7b9ae3cde32a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42062
59732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.4206259732
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.692320829
Short name T587
Test name
Test status
Simulation time 2965920230 ps
CPU time 22.79 seconds
Started Apr 02 01:01:35 PM PDT 24
Finished Apr 02 01:01:58 PM PDT 24
Peak memory 249000 kb
Host smart-d0a47887-7b95-4427-a419-b5050e3028f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69232
0829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.692320829
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.1758805623
Short name T86
Test name
Test status
Simulation time 364714432572 ps
CPU time 3434.58 seconds
Started Apr 02 01:01:29 PM PDT 24
Finished Apr 02 01:58:44 PM PDT 24
Peak memory 298140 kb
Host smart-a7db6b80-25a5-441b-a104-ba754e2d59b1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758805623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.1758805623
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.3121479737
Short name T292
Test name
Test status
Simulation time 32876121591 ps
CPU time 1970.5 seconds
Started Apr 02 01:01:32 PM PDT 24
Finished Apr 02 01:34:23 PM PDT 24
Peak memory 273516 kb
Host smart-05bb0bc3-9be6-47c0-a7cd-cd159eb71c4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121479737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.3121479737
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.2401315465
Short name T690
Test name
Test status
Simulation time 220644318 ps
CPU time 23.51 seconds
Started Apr 02 01:01:36 PM PDT 24
Finished Apr 02 01:02:00 PM PDT 24
Peak memory 247360 kb
Host smart-46135e25-b89e-4a12-a4b9-6177b778fec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24013
15465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.2401315465
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.484200697
Short name T19
Test name
Test status
Simulation time 285770882 ps
CPU time 19.95 seconds
Started Apr 02 01:01:39 PM PDT 24
Finished Apr 02 01:01:59 PM PDT 24
Peak memory 255028 kb
Host smart-59f82a95-3804-404c-b9e9-186f23f6bff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48420
0697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.484200697
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.408443564
Short name T329
Test name
Test status
Simulation time 167429921302 ps
CPU time 1553.56 seconds
Started Apr 02 01:01:32 PM PDT 24
Finished Apr 02 01:27:26 PM PDT 24
Peak memory 266300 kb
Host smart-c2d1fa23-659d-4f4b-951d-b3893b478984
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408443564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.408443564
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.3211412545
Short name T429
Test name
Test status
Simulation time 37789004073 ps
CPU time 2315.41 seconds
Started Apr 02 01:01:39 PM PDT 24
Finished Apr 02 01:40:15 PM PDT 24
Peak memory 289920 kb
Host smart-1497bbfa-afb3-4c49-bcd6-2d781f88f9ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211412545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.3211412545
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.51730669
Short name T564
Test name
Test status
Simulation time 12107848454 ps
CPU time 262.23 seconds
Started Apr 02 01:01:40 PM PDT 24
Finished Apr 02 01:06:02 PM PDT 24
Peak memory 247924 kb
Host smart-235c34c2-e1a5-4a2c-a964-1ff9818110ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51730669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.51730669
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.3237090985
Short name T616
Test name
Test status
Simulation time 639073234 ps
CPU time 40.16 seconds
Started Apr 02 01:01:38 PM PDT 24
Finished Apr 02 01:02:18 PM PDT 24
Peak memory 248716 kb
Host smart-46fd268f-9e06-4333-a202-831db3e2bc9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32370
90985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.3237090985
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.3381739844
Short name T433
Test name
Test status
Simulation time 510670964 ps
CPU time 26.55 seconds
Started Apr 02 01:01:39 PM PDT 24
Finished Apr 02 01:02:05 PM PDT 24
Peak memory 248900 kb
Host smart-f6545f4d-6cb0-4d58-96df-25e1dfc5df0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33817
39844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.3381739844
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.1978892316
Short name T617
Test name
Test status
Simulation time 224211587 ps
CPU time 14.41 seconds
Started Apr 02 01:01:32 PM PDT 24
Finished Apr 02 01:01:46 PM PDT 24
Peak memory 256760 kb
Host smart-f52a0b21-7618-4697-b792-6376cbf2cdc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19788
92316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.1978892316
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.3289474825
Short name T713
Test name
Test status
Simulation time 241030225 ps
CPU time 16.6 seconds
Started Apr 02 01:01:38 PM PDT 24
Finished Apr 02 01:01:55 PM PDT 24
Peak memory 254136 kb
Host smart-c9a92f36-b8b9-4a38-837a-b5e2a635187a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32894
74825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.3289474825
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.1676435911
Short name T273
Test name
Test status
Simulation time 12723812527 ps
CPU time 1225.03 seconds
Started Apr 02 01:01:30 PM PDT 24
Finished Apr 02 01:21:55 PM PDT 24
Peak memory 289392 kb
Host smart-cb89b57b-55cb-4c70-9e2f-458af3c2b687
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676435911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.1676435911
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.2084602067
Short name T240
Test name
Test status
Simulation time 26445233725 ps
CPU time 1589.81 seconds
Started Apr 02 01:01:30 PM PDT 24
Finished Apr 02 01:28:00 PM PDT 24
Peak memory 281840 kb
Host smart-e7371b31-5405-4b11-b3cc-1fff27bb5c33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084602067 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.2084602067
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.3211662748
Short name T184
Test name
Test status
Simulation time 321293038862 ps
CPU time 2272.86 seconds
Started Apr 02 01:01:30 PM PDT 24
Finished Apr 02 01:39:23 PM PDT 24
Peak memory 285868 kb
Host smart-b0f01530-367a-4f99-9890-d833091cbcce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211662748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.3211662748
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.173756418
Short name T656
Test name
Test status
Simulation time 5633424982 ps
CPU time 299.86 seconds
Started Apr 02 01:01:45 PM PDT 24
Finished Apr 02 01:06:45 PM PDT 24
Peak memory 256992 kb
Host smart-edcf03f3-96ed-4155-a54d-e30b6251b17e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17375
6418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.173756418
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.1015573602
Short name T70
Test name
Test status
Simulation time 1391628095 ps
CPU time 35.27 seconds
Started Apr 02 01:01:40 PM PDT 24
Finished Apr 02 01:02:15 PM PDT 24
Peak memory 248780 kb
Host smart-4dad65dc-3210-4b52-a952-75ea93d3fdfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10155
73602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1015573602
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.3039200377
Short name T688
Test name
Test status
Simulation time 40903954285 ps
CPU time 1019.11 seconds
Started Apr 02 01:01:41 PM PDT 24
Finished Apr 02 01:18:41 PM PDT 24
Peak memory 266384 kb
Host smart-8f567121-f051-45aa-8a3e-1c128007c76c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039200377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.3039200377
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.4189231241
Short name T570
Test name
Test status
Simulation time 12220353596 ps
CPU time 558.31 seconds
Started Apr 02 01:01:46 PM PDT 24
Finished Apr 02 01:11:04 PM PDT 24
Peak memory 265252 kb
Host smart-839301b7-51b1-4f84-a3c5-6780440683ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189231241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.4189231241
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.1293344673
Short name T309
Test name
Test status
Simulation time 34621139733 ps
CPU time 362.69 seconds
Started Apr 02 01:01:41 PM PDT 24
Finished Apr 02 01:07:44 PM PDT 24
Peak memory 247876 kb
Host smart-6074ccff-73b4-44df-ab9e-d59e15405a1f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293344673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.1293344673
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.280679524
Short name T369
Test name
Test status
Simulation time 46829087 ps
CPU time 4.57 seconds
Started Apr 02 01:01:36 PM PDT 24
Finished Apr 02 01:01:41 PM PDT 24
Peak memory 240676 kb
Host smart-84e18147-4035-4e0a-84a2-6569deb0657f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28067
9524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.280679524
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.2399095408
Short name T444
Test name
Test status
Simulation time 789301986 ps
CPU time 30.25 seconds
Started Apr 02 01:01:38 PM PDT 24
Finished Apr 02 01:02:09 PM PDT 24
Peak memory 255352 kb
Host smart-2f5500eb-520e-4dd1-9e1a-d3e081a8cd2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23990
95408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.2399095408
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.1581403843
Short name T261
Test name
Test status
Simulation time 2076627740 ps
CPU time 66.52 seconds
Started Apr 02 01:01:30 PM PDT 24
Finished Apr 02 01:02:37 PM PDT 24
Peak memory 255228 kb
Host smart-508023a8-0398-4c74-bdd0-4d31461d23a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15814
03843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.1581403843
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.914876363
Short name T228
Test name
Test status
Simulation time 1099309924 ps
CPU time 24.27 seconds
Started Apr 02 01:01:36 PM PDT 24
Finished Apr 02 01:02:01 PM PDT 24
Peak memory 248076 kb
Host smart-5a266cfc-3b02-4979-9e4f-f35ea3a44c83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91487
6363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.914876363
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.1428575837
Short name T46
Test name
Test status
Simulation time 3114480234 ps
CPU time 95.99 seconds
Started Apr 02 01:01:37 PM PDT 24
Finished Apr 02 01:03:13 PM PDT 24
Peak memory 256560 kb
Host smart-262e3df2-cb75-4f43-b489-02f3f8f38bd2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428575837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.1428575837
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.1982783296
Short name T427
Test name
Test status
Simulation time 115578530546 ps
CPU time 1674.03 seconds
Started Apr 02 01:01:42 PM PDT 24
Finished Apr 02 01:29:36 PM PDT 24
Peak memory 273536 kb
Host smart-6db806c9-e833-4aeb-a414-14569ad2a169
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982783296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.1982783296
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.3671918144
Short name T365
Test name
Test status
Simulation time 843499882 ps
CPU time 20.4 seconds
Started Apr 02 01:01:42 PM PDT 24
Finished Apr 02 01:02:02 PM PDT 24
Peak memory 248704 kb
Host smart-8db93049-ecd2-4290-845f-02b09832bdbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36719
18144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.3671918144
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.2415737470
Short name T686
Test name
Test status
Simulation time 4958973078 ps
CPU time 75.84 seconds
Started Apr 02 01:01:42 PM PDT 24
Finished Apr 02 01:02:58 PM PDT 24
Peak memory 255712 kb
Host smart-81e5115f-e290-4597-aedd-9170bbfc1df9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24157
37470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.2415737470
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.3234461413
Short name T682
Test name
Test status
Simulation time 15023692532 ps
CPU time 1662.51 seconds
Started Apr 02 01:01:38 PM PDT 24
Finished Apr 02 01:29:21 PM PDT 24
Peak memory 289064 kb
Host smart-3e51c8be-2778-4499-ad32-c40fb989f5da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234461413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.3234461413
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.4057475199
Short name T604
Test name
Test status
Simulation time 22342233538 ps
CPU time 447.17 seconds
Started Apr 02 01:01:34 PM PDT 24
Finished Apr 02 01:09:01 PM PDT 24
Peak memory 247064 kb
Host smart-2e62c825-c38a-4c74-9606-6851fd3bb2cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057475199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.4057475199
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.1944755393
Short name T437
Test name
Test status
Simulation time 1033066662 ps
CPU time 54.95 seconds
Started Apr 02 01:01:44 PM PDT 24
Finished Apr 02 01:02:40 PM PDT 24
Peak memory 256072 kb
Host smart-38ba7918-97f1-4eef-b88d-568419715ff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19447
55393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1944755393
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.1666999081
Short name T381
Test name
Test status
Simulation time 1070761047 ps
CPU time 63.25 seconds
Started Apr 02 01:01:40 PM PDT 24
Finished Apr 02 01:02:44 PM PDT 24
Peak memory 255676 kb
Host smart-3cf9a782-e463-4fdf-8d27-c04716a9c82b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16669
99081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.1666999081
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.3530966307
Short name T91
Test name
Test status
Simulation time 852933329 ps
CPU time 49.39 seconds
Started Apr 02 01:01:42 PM PDT 24
Finished Apr 02 01:02:31 PM PDT 24
Peak memory 254804 kb
Host smart-79fc0fe1-5498-471e-8fc5-332120ff793b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35309
66307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.3530966307
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.1410861550
Short name T186
Test name
Test status
Simulation time 769398142 ps
CPU time 43.8 seconds
Started Apr 02 01:01:44 PM PDT 24
Finished Apr 02 01:02:28 PM PDT 24
Peak memory 248892 kb
Host smart-f0699730-a69d-47ce-adf9-2e967b6190dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14108
61550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.1410861550
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.4121322404
Short name T703
Test name
Test status
Simulation time 249915225277 ps
CPU time 2913.95 seconds
Started Apr 02 01:01:42 PM PDT 24
Finished Apr 02 01:50:16 PM PDT 24
Peak memory 299296 kb
Host smart-958a40fc-c649-4515-9ea5-00ffaf0151eb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121322404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.4121322404
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.3437339926
Short name T581
Test name
Test status
Simulation time 8223944188 ps
CPU time 969.97 seconds
Started Apr 02 01:01:37 PM PDT 24
Finished Apr 02 01:17:47 PM PDT 24
Peak memory 273416 kb
Host smart-c44af93c-3b4e-412f-9e2e-a2bedfe0174d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437339926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.3437339926
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.845521420
Short name T195
Test name
Test status
Simulation time 4185031790 ps
CPU time 239.56 seconds
Started Apr 02 01:01:42 PM PDT 24
Finished Apr 02 01:05:42 PM PDT 24
Peak memory 256640 kb
Host smart-1e5976aa-b14f-4022-a1e4-2a8ec9532b0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84552
1420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.845521420
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.124451076
Short name T20
Test name
Test status
Simulation time 1099403527 ps
CPU time 21.61 seconds
Started Apr 02 01:01:44 PM PDT 24
Finished Apr 02 01:02:06 PM PDT 24
Peak memory 254488 kb
Host smart-505abd27-f092-4d7b-b65c-9e85d4654f55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12445
1076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.124451076
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.3025526285
Short name T231
Test name
Test status
Simulation time 35999383859 ps
CPU time 1119.25 seconds
Started Apr 02 01:01:45 PM PDT 24
Finished Apr 02 01:20:25 PM PDT 24
Peak memory 268468 kb
Host smart-3e8001c2-1a3e-4dda-a5a0-79cc3c2301a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025526285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.3025526285
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.3895865914
Short name T237
Test name
Test status
Simulation time 76369513584 ps
CPU time 1540.54 seconds
Started Apr 02 01:01:37 PM PDT 24
Finished Apr 02 01:27:18 PM PDT 24
Peak memory 288836 kb
Host smart-b3c65c23-5cb2-471d-96eb-a817aa82b595
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895865914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.3895865914
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.3119542246
Short name T304
Test name
Test status
Simulation time 58850330567 ps
CPU time 566.81 seconds
Started Apr 02 01:01:36 PM PDT 24
Finished Apr 02 01:11:03 PM PDT 24
Peak memory 248104 kb
Host smart-ebcf3ab6-220e-4662-b111-5ae46f244f00
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119542246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.3119542246
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.564066132
Short name T380
Test name
Test status
Simulation time 2555645134 ps
CPU time 24.9 seconds
Started Apr 02 01:01:38 PM PDT 24
Finished Apr 02 01:02:03 PM PDT 24
Peak memory 256116 kb
Host smart-40e5e5c8-9cf2-4c46-aaf4-72ad2529ab0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56406
6132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.564066132
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.764799432
Short name T421
Test name
Test status
Simulation time 359901029 ps
CPU time 7.09 seconds
Started Apr 02 01:01:41 PM PDT 24
Finished Apr 02 01:01:48 PM PDT 24
Peak memory 250696 kb
Host smart-ae42198d-0ef6-4d87-9ea1-9e5bee957591
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76479
9432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.764799432
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.1637909439
Short name T543
Test name
Test status
Simulation time 1406007452 ps
CPU time 23.32 seconds
Started Apr 02 01:01:39 PM PDT 24
Finished Apr 02 01:02:03 PM PDT 24
Peak memory 248888 kb
Host smart-f455dd6e-a4ed-4d90-82e4-6dd6c1d5475e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16379
09439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.1637909439
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.1629800152
Short name T58
Test name
Test status
Simulation time 2023607118 ps
CPU time 64.41 seconds
Started Apr 02 01:01:47 PM PDT 24
Finished Apr 02 01:02:51 PM PDT 24
Peak memory 256164 kb
Host smart-c66c3cfa-2608-4b33-85bf-8c3c6163048e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16298
00152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.1629800152
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.875291282
Short name T462
Test name
Test status
Simulation time 38438123681 ps
CPU time 2224.56 seconds
Started Apr 02 01:01:46 PM PDT 24
Finished Apr 02 01:38:51 PM PDT 24
Peak memory 289420 kb
Host smart-89b84c6b-6021-49f9-9912-aeeb2a8fd7cd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875291282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_han
dler_stress_all.875291282
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.3989387315
Short name T256
Test name
Test status
Simulation time 87359052621 ps
CPU time 2762.26 seconds
Started Apr 02 01:01:41 PM PDT 24
Finished Apr 02 01:47:43 PM PDT 24
Peak memory 305480 kb
Host smart-4bf5fa0b-8cf3-406f-b6f0-0c7c8288c824
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989387315 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.3989387315
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.1594325106
Short name T422
Test name
Test status
Simulation time 216414056748 ps
CPU time 1533.82 seconds
Started Apr 02 01:01:43 PM PDT 24
Finished Apr 02 01:27:17 PM PDT 24
Peak memory 273572 kb
Host smart-65d184cc-71a2-47a3-8ca1-8c9756b13108
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594325106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.1594325106
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.62465683
Short name T636
Test name
Test status
Simulation time 829847989 ps
CPU time 54.06 seconds
Started Apr 02 01:01:37 PM PDT 24
Finished Apr 02 01:02:31 PM PDT 24
Peak memory 248832 kb
Host smart-36ce7a1c-97aa-4356-9cb5-d669c7cdedbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62465
683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.62465683
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.2328722459
Short name T610
Test name
Test status
Simulation time 1198309925 ps
CPU time 68.4 seconds
Started Apr 02 01:01:44 PM PDT 24
Finished Apr 02 01:02:52 PM PDT 24
Peak memory 254808 kb
Host smart-cce2b50f-569e-4ee4-b429-a48cb50bd42d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23287
22459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.2328722459
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.2692067868
Short name T532
Test name
Test status
Simulation time 136421350697 ps
CPU time 2285.31 seconds
Started Apr 02 01:01:37 PM PDT 24
Finished Apr 02 01:39:43 PM PDT 24
Peak memory 281728 kb
Host smart-bd161cb1-a2e0-4534-86dc-418bc6878926
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692067868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.2692067868
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.2123663501
Short name T520
Test name
Test status
Simulation time 15771578346 ps
CPU time 174.69 seconds
Started Apr 02 01:01:46 PM PDT 24
Finished Apr 02 01:04:41 PM PDT 24
Peak memory 247772 kb
Host smart-ef3afc64-bfd8-4da0-87c5-eef8e27fba1f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123663501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.2123663501
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.3944813658
Short name T601
Test name
Test status
Simulation time 605987305 ps
CPU time 41.12 seconds
Started Apr 02 01:01:45 PM PDT 24
Finished Apr 02 01:02:26 PM PDT 24
Peak memory 255676 kb
Host smart-c0118f2f-9503-425b-9a07-3c5befb3aa58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39448
13658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.3944813658
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.2816421572
Short name T696
Test name
Test status
Simulation time 285811417 ps
CPU time 45.57 seconds
Started Apr 02 01:01:44 PM PDT 24
Finished Apr 02 01:02:29 PM PDT 24
Peak memory 247404 kb
Host smart-62782846-4c83-4817-80ec-bd6728889624
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28164
21572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.2816421572
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.1775757669
Short name T61
Test name
Test status
Simulation time 878106419 ps
CPU time 14.86 seconds
Started Apr 02 01:01:47 PM PDT 24
Finished Apr 02 01:02:02 PM PDT 24
Peak memory 248880 kb
Host smart-c36380c2-099c-46f0-bae5-f95626479be6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17757
57669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.1775757669
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.115458183
Short name T640
Test name
Test status
Simulation time 1700109702 ps
CPU time 55.51 seconds
Started Apr 02 01:01:48 PM PDT 24
Finished Apr 02 01:02:43 PM PDT 24
Peak memory 248864 kb
Host smart-bf278fb0-c9a0-443a-b019-28a498225cae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11545
8183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.115458183
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.3968063389
Short name T226
Test name
Test status
Simulation time 132155101 ps
CPU time 13.26 seconds
Started Apr 02 01:01:48 PM PDT 24
Finished Apr 02 01:02:02 PM PDT 24
Peak memory 248876 kb
Host smart-ddefc800-ed4a-4c4a-9842-69e2bdac7881
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968063389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.3968063389
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.3050784184
Short name T527
Test name
Test status
Simulation time 60823414494 ps
CPU time 1790.48 seconds
Started Apr 02 01:01:45 PM PDT 24
Finished Apr 02 01:31:35 PM PDT 24
Peak memory 266396 kb
Host smart-78e89f10-1306-4ad4-80a8-a08908877bdd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050784184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.3050784184
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.1558078753
Short name T534
Test name
Test status
Simulation time 4608831867 ps
CPU time 98.78 seconds
Started Apr 02 01:01:44 PM PDT 24
Finished Apr 02 01:03:23 PM PDT 24
Peak memory 257088 kb
Host smart-77bde218-9e92-4bed-b9ef-3438dbfe4686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15580
78753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.1558078753
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.938479929
Short name T224
Test name
Test status
Simulation time 430753736 ps
CPU time 8.46 seconds
Started Apr 02 01:01:43 PM PDT 24
Finished Apr 02 01:01:52 PM PDT 24
Peak memory 240624 kb
Host smart-0009e0f1-74b8-49c8-af76-bd443478e86d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93847
9929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.938479929
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.3173607907
Short name T474
Test name
Test status
Simulation time 17984157104 ps
CPU time 929.8 seconds
Started Apr 02 01:01:46 PM PDT 24
Finished Apr 02 01:17:16 PM PDT 24
Peak memory 272808 kb
Host smart-ef1bea03-2618-4f0b-920b-afb67dae59e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173607907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3173607907
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.820955936
Short name T412
Test name
Test status
Simulation time 123071640417 ps
CPU time 1925.8 seconds
Started Apr 02 01:01:43 PM PDT 24
Finished Apr 02 01:33:49 PM PDT 24
Peak memory 284016 kb
Host smart-a717ddc4-6a63-447e-a035-2f27bf07a1fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820955936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.820955936
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.606315121
Short name T310
Test name
Test status
Simulation time 3418721608 ps
CPU time 143.2 seconds
Started Apr 02 01:01:47 PM PDT 24
Finished Apr 02 01:04:11 PM PDT 24
Peak memory 247712 kb
Host smart-f441bc5d-eace-4d48-8e4f-bb4c4ea1e73c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606315121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.606315121
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.3928952008
Short name T554
Test name
Test status
Simulation time 167223259 ps
CPU time 7.11 seconds
Started Apr 02 01:01:44 PM PDT 24
Finished Apr 02 01:01:52 PM PDT 24
Peak memory 248684 kb
Host smart-bd319260-a233-4931-ac2f-f7b0cfb87fbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39289
52008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.3928952008
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.61757418
Short name T453
Test name
Test status
Simulation time 2111606732 ps
CPU time 59.47 seconds
Started Apr 02 01:01:48 PM PDT 24
Finished Apr 02 01:02:48 PM PDT 24
Peak memory 248876 kb
Host smart-87ecebc9-1ace-4da0-a0b4-f5c7d1613b35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61757
418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.61757418
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.948213793
Short name T715
Test name
Test status
Simulation time 3435508208 ps
CPU time 58.12 seconds
Started Apr 02 01:01:44 PM PDT 24
Finished Apr 02 01:02:43 PM PDT 24
Peak memory 248948 kb
Host smart-5ee90d57-b42c-4677-ae65-4693a441af33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94821
3793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.948213793
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.3594634968
Short name T460
Test name
Test status
Simulation time 2439472830 ps
CPU time 65.08 seconds
Started Apr 02 01:01:43 PM PDT 24
Finished Apr 02 01:02:48 PM PDT 24
Peak memory 248944 kb
Host smart-b90b6da6-6b1a-4e04-a7f7-277bd8718f04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35946
34968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.3594634968
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.2306151002
Short name T500
Test name
Test status
Simulation time 199907962349 ps
CPU time 2310.4 seconds
Started Apr 02 01:01:48 PM PDT 24
Finished Apr 02 01:40:18 PM PDT 24
Peak memory 273104 kb
Host smart-c6af2dab-cae4-401f-9dad-e78685fe28bd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306151002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.2306151002
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.789641162
Short name T634
Test name
Test status
Simulation time 54248735851 ps
CPU time 1263.27 seconds
Started Apr 02 01:01:59 PM PDT 24
Finished Apr 02 01:23:02 PM PDT 24
Peak memory 273528 kb
Host smart-d0be6ce7-57d9-4d77-a309-525bd06c77b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789641162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.789641162
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.3760348462
Short name T629
Test name
Test status
Simulation time 8845221686 ps
CPU time 46.37 seconds
Started Apr 02 01:01:45 PM PDT 24
Finished Apr 02 01:02:31 PM PDT 24
Peak memory 256456 kb
Host smart-18da561c-3935-4e89-9eca-9fd0b46cbf35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37603
48462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.3760348462
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.3930218981
Short name T646
Test name
Test status
Simulation time 96727305 ps
CPU time 11.76 seconds
Started Apr 02 01:01:43 PM PDT 24
Finished Apr 02 01:01:54 PM PDT 24
Peak memory 248780 kb
Host smart-8098338c-b878-4292-aa93-2787f325636d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39302
18981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.3930218981
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.1842633007
Short name T669
Test name
Test status
Simulation time 40826643710 ps
CPU time 2413.74 seconds
Started Apr 02 01:01:47 PM PDT 24
Finished Apr 02 01:42:01 PM PDT 24
Peak memory 273560 kb
Host smart-1604cf83-83e7-49de-a3c3-1462d313f6be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842633007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.1842633007
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.782971190
Short name T100
Test name
Test status
Simulation time 7104682761 ps
CPU time 797.1 seconds
Started Apr 02 01:01:56 PM PDT 24
Finished Apr 02 01:15:13 PM PDT 24
Peak memory 273400 kb
Host smart-f4c7cbc3-092e-4f8e-a92d-f1a74312de12
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782971190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.782971190
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.3955640244
Short name T242
Test name
Test status
Simulation time 29851910098 ps
CPU time 294.16 seconds
Started Apr 02 01:01:46 PM PDT 24
Finished Apr 02 01:06:40 PM PDT 24
Peak memory 256104 kb
Host smart-48129cbb-67ac-4645-a364-ba0110d88205
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955640244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.3955640244
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.2062820802
Short name T562
Test name
Test status
Simulation time 442950697 ps
CPU time 25.9 seconds
Started Apr 02 01:01:49 PM PDT 24
Finished Apr 02 01:02:15 PM PDT 24
Peak memory 248884 kb
Host smart-9f99446b-1f76-4a9e-aa36-c9dfc7e28c89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20628
20802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.2062820802
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.2862738726
Short name T396
Test name
Test status
Simulation time 212657228 ps
CPU time 17.93 seconds
Started Apr 02 01:01:47 PM PDT 24
Finished Apr 02 01:02:05 PM PDT 24
Peak memory 248868 kb
Host smart-1e814b59-8bd9-4747-aa26-9d14d8ef5585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28627
38726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.2862738726
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.1260436979
Short name T105
Test name
Test status
Simulation time 112777674 ps
CPU time 16.75 seconds
Started Apr 02 01:01:47 PM PDT 24
Finished Apr 02 01:02:04 PM PDT 24
Peak memory 255348 kb
Host smart-9d3a0df8-bbe4-43fe-8058-8b3a089503e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12604
36979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.1260436979
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.2890078011
Short name T473
Test name
Test status
Simulation time 983957578 ps
CPU time 23.51 seconds
Started Apr 02 01:01:43 PM PDT 24
Finished Apr 02 01:02:06 PM PDT 24
Peak memory 248916 kb
Host smart-8f3831f0-85b4-4382-84bb-fe813f60a390
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28900
78011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.2890078011
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.159186174
Short name T262
Test name
Test status
Simulation time 14343467304 ps
CPU time 408.32 seconds
Started Apr 02 01:01:48 PM PDT 24
Finished Apr 02 01:08:36 PM PDT 24
Peak memory 257096 kb
Host smart-7723cbb8-73de-4911-8841-ed50e79290e4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159186174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_han
dler_stress_all.159186174
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.3495797131
Short name T654
Test name
Test status
Simulation time 70095067889 ps
CPU time 1373.43 seconds
Started Apr 02 01:01:47 PM PDT 24
Finished Apr 02 01:24:40 PM PDT 24
Peak memory 272248 kb
Host smart-42e833a1-1e88-4c54-8db1-29e09f5b04ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495797131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.3495797131
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.1040679251
Short name T575
Test name
Test status
Simulation time 5912163750 ps
CPU time 320.32 seconds
Started Apr 02 01:01:54 PM PDT 24
Finished Apr 02 01:07:14 PM PDT 24
Peak memory 257132 kb
Host smart-0d3cc854-8e52-4b74-8b7c-1a394b89f5bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10406
79251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.1040679251
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.3197877890
Short name T461
Test name
Test status
Simulation time 4140125410 ps
CPU time 59.93 seconds
Started Apr 02 01:01:56 PM PDT 24
Finished Apr 02 01:02:56 PM PDT 24
Peak memory 256488 kb
Host smart-04b5f8e3-b3fd-4425-8c4f-4143d8193ed6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31978
77890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.3197877890
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.1689170712
Short name T331
Test name
Test status
Simulation time 130008701395 ps
CPU time 2084.5 seconds
Started Apr 02 01:01:55 PM PDT 24
Finished Apr 02 01:36:40 PM PDT 24
Peak memory 289900 kb
Host smart-08409023-6a52-4ed0-bf96-11226d5a2d18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689170712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.1689170712
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.4206244894
Short name T507
Test name
Test status
Simulation time 16045317780 ps
CPU time 1185.6 seconds
Started Apr 02 01:01:50 PM PDT 24
Finished Apr 02 01:21:36 PM PDT 24
Peak memory 287068 kb
Host smart-84ac7506-afd0-425a-9e33-f6bd134daa41
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206244894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.4206244894
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.2655875057
Short name T635
Test name
Test status
Simulation time 10838772074 ps
CPU time 268.09 seconds
Started Apr 02 01:01:51 PM PDT 24
Finished Apr 02 01:06:19 PM PDT 24
Peak memory 248256 kb
Host smart-1b356d44-bb7c-4f54-aaed-dca082d7e745
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655875057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.2655875057
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.3300405593
Short name T361
Test name
Test status
Simulation time 5289977384 ps
CPU time 39.81 seconds
Started Apr 02 01:01:53 PM PDT 24
Finished Apr 02 01:02:33 PM PDT 24
Peak memory 248832 kb
Host smart-9a66d974-a9f2-4a25-89d0-14c2c8878c88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33004
05593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.3300405593
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.3850665802
Short name T647
Test name
Test status
Simulation time 1020362093 ps
CPU time 32.35 seconds
Started Apr 02 01:01:46 PM PDT 24
Finished Apr 02 01:02:19 PM PDT 24
Peak memory 255616 kb
Host smart-7be2526b-3284-41bf-ae0b-115743bf7993
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38506
65802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.3850665802
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.3642080093
Short name T60
Test name
Test status
Simulation time 2401128854 ps
CPU time 44.22 seconds
Started Apr 02 01:01:50 PM PDT 24
Finished Apr 02 01:02:34 PM PDT 24
Peak memory 255360 kb
Host smart-9e87e2e4-63b9-44ee-8719-d67f03261217
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36420
80093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3642080093
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.3515235510
Short name T398
Test name
Test status
Simulation time 303755469 ps
CPU time 27.95 seconds
Started Apr 02 01:01:46 PM PDT 24
Finished Apr 02 01:02:14 PM PDT 24
Peak memory 257096 kb
Host smart-fe652dc1-fce2-42d0-a7e6-e2d9b9a5caf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35152
35510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3515235510
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.3858143528
Short name T491
Test name
Test status
Simulation time 49286183783 ps
CPU time 1277.59 seconds
Started Apr 02 01:01:50 PM PDT 24
Finished Apr 02 01:23:08 PM PDT 24
Peak memory 289364 kb
Host smart-945f122f-0119-40c2-b2c2-b8496b34581c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858143528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.3858143528
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.2297799172
Short name T496
Test name
Test status
Simulation time 21608657708 ps
CPU time 2222.81 seconds
Started Apr 02 01:01:59 PM PDT 24
Finished Apr 02 01:39:02 PM PDT 24
Peak memory 305084 kb
Host smart-fa6e8bd7-5310-42ab-9d50-8d750f3005b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297799172 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.2297799172
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.3915698097
Short name T32
Test name
Test status
Simulation time 14913010676 ps
CPU time 1432.59 seconds
Started Apr 02 01:01:53 PM PDT 24
Finished Apr 02 01:25:46 PM PDT 24
Peak memory 285152 kb
Host smart-aed09da4-24d5-42f1-8eb6-2ab2fb59260d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915698097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.3915698097
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.2202959340
Short name T35
Test name
Test status
Simulation time 5720387297 ps
CPU time 176.85 seconds
Started Apr 02 01:01:50 PM PDT 24
Finished Apr 02 01:04:47 PM PDT 24
Peak memory 257136 kb
Host smart-28579dd4-22dd-4068-b9a5-d4e5b8b9843a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22029
59340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2202959340
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.418437338
Short name T535
Test name
Test status
Simulation time 132129564 ps
CPU time 10.45 seconds
Started Apr 02 01:01:53 PM PDT 24
Finished Apr 02 01:02:04 PM PDT 24
Peak memory 249964 kb
Host smart-b1a20972-2c94-4dac-bc52-7fe707c174ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41843
7338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.418437338
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.546722774
Short name T466
Test name
Test status
Simulation time 13758235246 ps
CPU time 1027.47 seconds
Started Apr 02 01:01:59 PM PDT 24
Finished Apr 02 01:19:07 PM PDT 24
Peak memory 273420 kb
Host smart-67f766d1-5de1-4f07-8f23-50f799bd2a6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546722774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.546722774
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.3982582487
Short name T553
Test name
Test status
Simulation time 36119059739 ps
CPU time 2651.17 seconds
Started Apr 02 01:02:05 PM PDT 24
Finished Apr 02 01:46:16 PM PDT 24
Peak memory 289412 kb
Host smart-4296a563-bf83-47d3-af73-27b0c15a1a94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982582487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.3982582487
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.2692764676
Short name T658
Test name
Test status
Simulation time 19199379382 ps
CPU time 412.88 seconds
Started Apr 02 01:01:51 PM PDT 24
Finished Apr 02 01:08:44 PM PDT 24
Peak memory 247836 kb
Host smart-2cb10458-22f1-4092-9cd4-d67610fde4e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692764676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.2692764676
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.4070821785
Short name T661
Test name
Test status
Simulation time 275349129 ps
CPU time 9.54 seconds
Started Apr 02 01:01:52 PM PDT 24
Finished Apr 02 01:02:02 PM PDT 24
Peak memory 251956 kb
Host smart-9eda05d8-e89d-47d0-bca3-c4d53ddb1265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40708
21785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.4070821785
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.1860719025
Short name T406
Test name
Test status
Simulation time 799354214 ps
CPU time 45.82 seconds
Started Apr 02 01:01:49 PM PDT 24
Finished Apr 02 01:02:35 PM PDT 24
Peak memory 247604 kb
Host smart-7c823cf2-9857-41e1-a986-12adddce2d4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18607
19025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.1860719025
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.3342858852
Short name T274
Test name
Test status
Simulation time 15056537368 ps
CPU time 70.85 seconds
Started Apr 02 01:01:56 PM PDT 24
Finished Apr 02 01:03:07 PM PDT 24
Peak memory 255556 kb
Host smart-b1f54abb-3bb1-47e0-97c1-725586dc294f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33428
58852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.3342858852
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.1616766479
Short name T227
Test name
Test status
Simulation time 190606292 ps
CPU time 11.77 seconds
Started Apr 02 01:01:51 PM PDT 24
Finished Apr 02 01:02:03 PM PDT 24
Peak memory 248876 kb
Host smart-97a17c31-e850-4064-b622-b83292639248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16167
66479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.1616766479
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.2265558318
Short name T628
Test name
Test status
Simulation time 43685306194 ps
CPU time 1626.78 seconds
Started Apr 02 01:01:54 PM PDT 24
Finished Apr 02 01:29:01 PM PDT 24
Peak memory 302156 kb
Host smart-dcf4beae-2dde-4522-bd36-44550ecfefc2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265558318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.2265558318
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.728161475
Short name T266
Test name
Test status
Simulation time 56134849744 ps
CPU time 1121.4 seconds
Started Apr 02 01:01:50 PM PDT 24
Finished Apr 02 01:20:32 PM PDT 24
Peak memory 290032 kb
Host smart-3bdf2337-e06e-4b4f-9b65-7ba70c370371
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728161475 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.728161475
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.1527635743
Short name T219
Test name
Test status
Simulation time 66855348 ps
CPU time 2.42 seconds
Started Apr 02 01:00:45 PM PDT 24
Finished Apr 02 01:00:54 PM PDT 24
Peak memory 249112 kb
Host smart-78524752-6e65-4afa-8f6a-752b776e6253
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1527635743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.1527635743
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.320743930
Short name T107
Test name
Test status
Simulation time 8502506688 ps
CPU time 809.65 seconds
Started Apr 02 01:00:48 PM PDT 24
Finished Apr 02 01:14:18 PM PDT 24
Peak memory 273592 kb
Host smart-1948d601-d6fa-473d-9e0e-e44dfb187293
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320743930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.320743930
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.306411137
Short name T609
Test name
Test status
Simulation time 421290084 ps
CPU time 19.76 seconds
Started Apr 02 01:00:58 PM PDT 24
Finished Apr 02 01:01:19 PM PDT 24
Peak memory 240660 kb
Host smart-4b3a6f16-81c4-4034-ae89-63e22130c988
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=306411137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.306411137
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.2474223878
Short name T589
Test name
Test status
Simulation time 2091046779 ps
CPU time 48.22 seconds
Started Apr 02 01:01:08 PM PDT 24
Finished Apr 02 01:02:04 PM PDT 24
Peak memory 256668 kb
Host smart-495902ef-2773-4f2d-9497-d8e01443e6bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24742
23878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.2474223878
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.2644167982
Short name T676
Test name
Test status
Simulation time 79906233 ps
CPU time 3.26 seconds
Started Apr 02 01:01:07 PM PDT 24
Finished Apr 02 01:01:13 PM PDT 24
Peak memory 240536 kb
Host smart-a4e48056-b72c-4103-9fc3-05d17a116b25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26441
67982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.2644167982
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.2607165919
Short name T14
Test name
Test status
Simulation time 32700499448 ps
CPU time 706.42 seconds
Started Apr 02 01:00:47 PM PDT 24
Finished Apr 02 01:12:34 PM PDT 24
Peak memory 270692 kb
Host smart-5af80673-6cf2-41fb-927c-01f6389b4c47
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607165919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.2607165919
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.2938692614
Short name T434
Test name
Test status
Simulation time 381136140652 ps
CPU time 2632.48 seconds
Started Apr 02 01:00:38 PM PDT 24
Finished Apr 02 01:44:31 PM PDT 24
Peak memory 289448 kb
Host smart-38f75929-d2ca-45d5-bd39-18610e9465fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938692614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.2938692614
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.3387750648
Short name T322
Test name
Test status
Simulation time 61166314193 ps
CPU time 124.53 seconds
Started Apr 02 01:00:54 PM PDT 24
Finished Apr 02 01:03:01 PM PDT 24
Peak memory 246964 kb
Host smart-3cc1c984-6c1d-4458-9fb4-e39c4962811d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387750648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.3387750648
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.731302020
Short name T549
Test name
Test status
Simulation time 1127542214 ps
CPU time 66.19 seconds
Started Apr 02 01:01:11 PM PDT 24
Finished Apr 02 01:02:23 PM PDT 24
Peak memory 248780 kb
Host smart-22560bbe-a1d2-4019-9971-42d63dff214e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73130
2020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.731302020
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.2306066785
Short name T426
Test name
Test status
Simulation time 4871567267 ps
CPU time 33.98 seconds
Started Apr 02 01:00:46 PM PDT 24
Finished Apr 02 01:01:21 PM PDT 24
Peak memory 255040 kb
Host smart-ffad6eeb-75c5-43e6-8de1-7bbfe5a62882
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23060
66785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.2306066785
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.248185606
Short name T13
Test name
Test status
Simulation time 360345254 ps
CPU time 23.26 seconds
Started Apr 02 01:00:45 PM PDT 24
Finished Apr 02 01:01:09 PM PDT 24
Peak memory 270604 kb
Host smart-175f2f72-37b8-40b6-93cd-7f7e53ff1056
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=248185606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.248185606
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.3747757804
Short name T233
Test name
Test status
Simulation time 236222242 ps
CPU time 8.95 seconds
Started Apr 02 01:00:49 PM PDT 24
Finished Apr 02 01:01:00 PM PDT 24
Peak memory 248872 kb
Host smart-9ea4e39b-31e3-49f5-a13b-8d54db70ec66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37477
57804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.3747757804
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.254797966
Short name T23
Test name
Test status
Simulation time 443037413 ps
CPU time 31.5 seconds
Started Apr 02 01:01:08 PM PDT 24
Finished Apr 02 01:01:45 PM PDT 24
Peak memory 255800 kb
Host smart-33291664-b2e5-4bc0-b915-476d02ea5e67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25479
7966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.254797966
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.287743080
Short name T701
Test name
Test status
Simulation time 1282345601 ps
CPU time 34.11 seconds
Started Apr 02 01:00:53 PM PDT 24
Finished Apr 02 01:01:30 PM PDT 24
Peak memory 256228 kb
Host smart-8710982a-a7af-4417-80cf-cbf777bf1c98
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287743080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_hand
ler_stress_all.287743080
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.4289047668
Short name T175
Test name
Test status
Simulation time 113116613347 ps
CPU time 1201.88 seconds
Started Apr 02 01:01:09 PM PDT 24
Finished Apr 02 01:21:18 PM PDT 24
Peak memory 283224 kb
Host smart-26ce345e-e1a0-4a38-bb4f-e815e120e9aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289047668 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.4289047668
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.711995830
Short name T590
Test name
Test status
Simulation time 28553358821 ps
CPU time 845.91 seconds
Started Apr 02 01:01:55 PM PDT 24
Finished Apr 02 01:16:01 PM PDT 24
Peak memory 267328 kb
Host smart-5a711035-d423-460a-9de4-1b5995aac6af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711995830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.711995830
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.3490621991
Short name T536
Test name
Test status
Simulation time 1524900846 ps
CPU time 129.57 seconds
Started Apr 02 01:01:57 PM PDT 24
Finished Apr 02 01:04:07 PM PDT 24
Peak memory 256672 kb
Host smart-bdecebda-8325-406a-9010-7fa28e429ee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34906
21991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.3490621991
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.1062779543
Short name T71
Test name
Test status
Simulation time 11377517954 ps
CPU time 44.3 seconds
Started Apr 02 01:01:56 PM PDT 24
Finished Apr 02 01:02:41 PM PDT 24
Peak memory 255592 kb
Host smart-9fb8b275-7f29-4af5-8bac-bdbe572af0ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10627
79543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.1062779543
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.2302669849
Short name T708
Test name
Test status
Simulation time 38088384458 ps
CPU time 920.78 seconds
Started Apr 02 01:01:57 PM PDT 24
Finished Apr 02 01:17:17 PM PDT 24
Peak memory 273520 kb
Host smart-10686748-4174-438d-920e-8b47f1746134
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302669849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.2302669849
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.1138742366
Short name T99
Test name
Test status
Simulation time 45056520281 ps
CPU time 1436.06 seconds
Started Apr 02 01:01:58 PM PDT 24
Finished Apr 02 01:25:54 PM PDT 24
Peak memory 272716 kb
Host smart-ab2ced4c-e7b6-4f53-9e1e-149f9e125c29
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138742366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.1138742366
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.2526540969
Short name T439
Test name
Test status
Simulation time 59503872007 ps
CPU time 280.93 seconds
Started Apr 02 01:01:55 PM PDT 24
Finished Apr 02 01:06:36 PM PDT 24
Peak memory 247768 kb
Host smart-1b93561b-4f14-4507-b5b7-54e8f72babc3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526540969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.2526540969
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.1835575562
Short name T409
Test name
Test status
Simulation time 703382205 ps
CPU time 38.39 seconds
Started Apr 02 01:01:56 PM PDT 24
Finished Apr 02 01:02:34 PM PDT 24
Peak memory 248904 kb
Host smart-29282950-aedf-42e8-87c4-c4df919660f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18355
75562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.1835575562
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.726458948
Short name T94
Test name
Test status
Simulation time 681173377 ps
CPU time 36.29 seconds
Started Apr 02 01:01:56 PM PDT 24
Finished Apr 02 01:02:33 PM PDT 24
Peak memory 248828 kb
Host smart-e6b29556-6ad1-44b0-94a9-f8e0fb6a26d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72645
8948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.726458948
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.1939516005
Short name T455
Test name
Test status
Simulation time 36272146 ps
CPU time 3.37 seconds
Started Apr 02 01:01:55 PM PDT 24
Finished Apr 02 01:01:59 PM PDT 24
Peak memory 240628 kb
Host smart-117199b6-9c06-46b1-b90c-8da9767debd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19395
16005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.1939516005
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.1425067346
Short name T487
Test name
Test status
Simulation time 45678480511 ps
CPU time 2445.48 seconds
Started Apr 02 01:02:00 PM PDT 24
Finished Apr 02 01:42:46 PM PDT 24
Peak memory 289708 kb
Host smart-5f24f7d8-d7ea-481f-a9e3-90da37b33f9c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425067346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.1425067346
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.2433875533
Short name T435
Test name
Test status
Simulation time 112109607020 ps
CPU time 1857.15 seconds
Started Apr 02 01:01:59 PM PDT 24
Finished Apr 02 01:32:57 PM PDT 24
Peak memory 288608 kb
Host smart-17eb008a-9c12-4ba4-a331-c6503a2b6dfb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433875533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.2433875533
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.3351771280
Short name T624
Test name
Test status
Simulation time 17246165691 ps
CPU time 236.35 seconds
Started Apr 02 01:02:00 PM PDT 24
Finished Apr 02 01:05:56 PM PDT 24
Peak memory 257184 kb
Host smart-c7d0aa47-2f94-4918-8562-a23ca6a6ae08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33517
71280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.3351771280
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.1889661037
Short name T508
Test name
Test status
Simulation time 247398982 ps
CPU time 19.84 seconds
Started Apr 02 01:01:55 PM PDT 24
Finished Apr 02 01:02:15 PM PDT 24
Peak memory 255592 kb
Host smart-ed3a21c1-b0c1-4e9a-9330-35d70a48b0aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18896
61037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.1889661037
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.3046913035
Short name T230
Test name
Test status
Simulation time 52211269855 ps
CPU time 1969.05 seconds
Started Apr 02 01:02:00 PM PDT 24
Finished Apr 02 01:34:50 PM PDT 24
Peak memory 272572 kb
Host smart-ff36d43c-a59f-4746-a0ae-1401a947f5cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046913035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.3046913035
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.3377756120
Short name T716
Test name
Test status
Simulation time 8374441184 ps
CPU time 719.01 seconds
Started Apr 02 01:02:00 PM PDT 24
Finished Apr 02 01:13:59 PM PDT 24
Peak memory 265504 kb
Host smart-5598b85b-8c4d-4a64-9c67-97b5cc113fc1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377756120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.3377756120
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.2358366801
Short name T308
Test name
Test status
Simulation time 111689747333 ps
CPU time 359.49 seconds
Started Apr 02 01:02:01 PM PDT 24
Finished Apr 02 01:08:01 PM PDT 24
Peak memory 247996 kb
Host smart-ba42dac5-ac8c-4cbb-961f-cb51904825e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358366801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.2358366801
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.1894797437
Short name T668
Test name
Test status
Simulation time 3222853736 ps
CPU time 47.33 seconds
Started Apr 02 01:01:56 PM PDT 24
Finished Apr 02 01:02:43 PM PDT 24
Peak memory 248888 kb
Host smart-5f93dd78-aaf3-4fa6-a96c-ad4b416280da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18947
97437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.1894797437
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.3150929103
Short name T452
Test name
Test status
Simulation time 488203435 ps
CPU time 20.13 seconds
Started Apr 02 01:01:55 PM PDT 24
Finished Apr 02 01:02:15 PM PDT 24
Peak memory 248576 kb
Host smart-cce9dd45-d502-48ec-81a0-d3903009c866
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31509
29103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.3150929103
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.2508300339
Short name T390
Test name
Test status
Simulation time 527492162 ps
CPU time 33.39 seconds
Started Apr 02 01:02:01 PM PDT 24
Finished Apr 02 01:02:35 PM PDT 24
Peak memory 255924 kb
Host smart-ffe74671-2b09-4118-a848-b563c0a2dd27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25083
00339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.2508300339
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.268548026
Short name T40
Test name
Test status
Simulation time 4171914906 ps
CPU time 99.53 seconds
Started Apr 02 01:02:02 PM PDT 24
Finished Apr 02 01:03:41 PM PDT 24
Peak memory 256996 kb
Host smart-30ce14c0-2d11-49fe-a052-219d438f671e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268548026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_han
dler_stress_all.268548026
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.1944328193
Short name T62
Test name
Test status
Simulation time 92937314407 ps
CPU time 4000.91 seconds
Started Apr 02 01:02:04 PM PDT 24
Finished Apr 02 02:08:46 PM PDT 24
Peak memory 321228 kb
Host smart-d2b09dac-076f-4639-8e5c-d7d991eb0c0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944328193 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.1944328193
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.4124460032
Short name T517
Test name
Test status
Simulation time 139412784924 ps
CPU time 1165.35 seconds
Started Apr 02 01:02:06 PM PDT 24
Finished Apr 02 01:21:32 PM PDT 24
Peak memory 281812 kb
Host smart-dffaf9b4-9ecd-4ef7-84d4-c551da4754e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124460032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.4124460032
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.1749305726
Short name T594
Test name
Test status
Simulation time 107686935 ps
CPU time 12.34 seconds
Started Apr 02 01:02:03 PM PDT 24
Finished Apr 02 01:02:15 PM PDT 24
Peak memory 248596 kb
Host smart-287c662e-8483-4236-b9b5-b06fff3c3329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17493
05726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.1749305726
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.1674453058
Short name T181
Test name
Test status
Simulation time 1582383051 ps
CPU time 33.07 seconds
Started Apr 02 01:01:58 PM PDT 24
Finished Apr 02 01:02:31 PM PDT 24
Peak memory 255452 kb
Host smart-3f95f225-ec3f-400d-acbf-c0cdc5e50ed9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16744
53058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.1674453058
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.466439605
Short name T335
Test name
Test status
Simulation time 46215358326 ps
CPU time 2608.74 seconds
Started Apr 02 01:02:02 PM PDT 24
Finished Apr 02 01:45:31 PM PDT 24
Peak memory 289172 kb
Host smart-e48f81fb-83b7-47cf-b7c1-e753b68d678e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466439605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.466439605
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.3432886708
Short name T458
Test name
Test status
Simulation time 138295808213 ps
CPU time 2285.34 seconds
Started Apr 02 01:02:05 PM PDT 24
Finished Apr 02 01:40:10 PM PDT 24
Peak memory 273484 kb
Host smart-b3ad1714-3b62-4ac8-97db-2d0e42e6cd5e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432886708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.3432886708
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.845621752
Short name T323
Test name
Test status
Simulation time 30181459434 ps
CPU time 335.53 seconds
Started Apr 02 01:02:02 PM PDT 24
Finished Apr 02 01:07:38 PM PDT 24
Peak memory 247916 kb
Host smart-1f3f32b7-d102-44f5-b283-8cd2233b634c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845621752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.845621752
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.1803597156
Short name T672
Test name
Test status
Simulation time 6099718373 ps
CPU time 28.99 seconds
Started Apr 02 01:02:00 PM PDT 24
Finished Apr 02 01:02:29 PM PDT 24
Peak memory 256168 kb
Host smart-f67b74db-9626-4609-bb03-e64622220f09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18035
97156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.1803597156
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.3893085146
Short name T368
Test name
Test status
Simulation time 243442003 ps
CPU time 16.99 seconds
Started Apr 02 01:01:59 PM PDT 24
Finished Apr 02 01:02:16 PM PDT 24
Peak memory 253704 kb
Host smart-135abf46-d64e-4240-b6ca-61268aa6bf8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38930
85146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.3893085146
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.564602582
Short name T59
Test name
Test status
Simulation time 300865485 ps
CPU time 9.13 seconds
Started Apr 02 01:02:05 PM PDT 24
Finished Apr 02 01:02:14 PM PDT 24
Peak memory 252984 kb
Host smart-93807567-23cc-47b6-9aa3-992a0c536c1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56460
2582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.564602582
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.2565455970
Short name T388
Test name
Test status
Simulation time 4037682419 ps
CPU time 55.45 seconds
Started Apr 02 01:01:59 PM PDT 24
Finished Apr 02 01:02:54 PM PDT 24
Peak memory 255800 kb
Host smart-d6be2aeb-9acb-48e4-8c5e-3c01953e9dff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25654
55970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2565455970
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.3494239008
Short name T585
Test name
Test status
Simulation time 35605052938 ps
CPU time 2395.86 seconds
Started Apr 02 01:02:03 PM PDT 24
Finished Apr 02 01:41:59 PM PDT 24
Peak memory 289936 kb
Host smart-2747514c-f906-4e77-9a6c-7bc0bdf7675f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494239008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.3494239008
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.4151932118
Short name T464
Test name
Test status
Simulation time 44314165454 ps
CPU time 1818.18 seconds
Started Apr 02 01:02:07 PM PDT 24
Finished Apr 02 01:32:25 PM PDT 24
Peak memory 273568 kb
Host smart-f6cff983-963a-4711-9a38-60ded202b8cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151932118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.4151932118
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.2797615713
Short name T424
Test name
Test status
Simulation time 3044289928 ps
CPU time 145.58 seconds
Started Apr 02 01:02:02 PM PDT 24
Finished Apr 02 01:04:28 PM PDT 24
Peak memory 256576 kb
Host smart-37663c79-4f02-4b63-8263-d4949da285ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27976
15713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.2797615713
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.3948362849
Short name T436
Test name
Test status
Simulation time 50814438 ps
CPU time 4.03 seconds
Started Apr 02 01:02:03 PM PDT 24
Finished Apr 02 01:02:07 PM PDT 24
Peak memory 251492 kb
Host smart-388df25c-4533-4a27-808f-8025c4d57665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39483
62849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.3948362849
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.830950498
Short name T699
Test name
Test status
Simulation time 31900673560 ps
CPU time 2070.76 seconds
Started Apr 02 01:02:07 PM PDT 24
Finished Apr 02 01:36:39 PM PDT 24
Peak memory 282160 kb
Host smart-708b0a6f-32be-471d-8881-587dd9f194a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830950498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.830950498
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.1535169218
Short name T407
Test name
Test status
Simulation time 31758235597 ps
CPU time 1844.29 seconds
Started Apr 02 01:02:07 PM PDT 24
Finished Apr 02 01:32:52 PM PDT 24
Peak memory 281732 kb
Host smart-607c9f36-07b7-4bb3-b52b-791aa24a9dfc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535169218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.1535169218
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.325040463
Short name T317
Test name
Test status
Simulation time 29163850850 ps
CPU time 403.01 seconds
Started Apr 02 01:02:09 PM PDT 24
Finished Apr 02 01:08:53 PM PDT 24
Peak memory 247896 kb
Host smart-10055bb2-66ea-461b-af99-b0371c4dd14c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325040463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.325040463
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.3218018813
Short name T649
Test name
Test status
Simulation time 900815576 ps
CPU time 23.02 seconds
Started Apr 02 01:02:07 PM PDT 24
Finished Apr 02 01:02:30 PM PDT 24
Peak memory 256496 kb
Host smart-bf8138bc-c5a1-4440-bc73-ef682831d9ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32180
18813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.3218018813
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.1732489521
Short name T630
Test name
Test status
Simulation time 1775003119 ps
CPU time 31.99 seconds
Started Apr 02 01:02:03 PM PDT 24
Finished Apr 02 01:02:35 PM PDT 24
Peak memory 255592 kb
Host smart-ff7dfb9f-bf7b-431d-b81a-0ffc55995453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17324
89521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.1732489521
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.971934502
Short name T495
Test name
Test status
Simulation time 165404621 ps
CPU time 14.21 seconds
Started Apr 02 01:02:09 PM PDT 24
Finished Apr 02 01:02:23 PM PDT 24
Peak memory 252568 kb
Host smart-2f2fa746-36c6-4304-a603-a62f7dfd11f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97193
4502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.971934502
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.686915321
Short name T176
Test name
Test status
Simulation time 194575871 ps
CPU time 15.47 seconds
Started Apr 02 01:02:09 PM PDT 24
Finished Apr 02 01:02:24 PM PDT 24
Peak memory 248860 kb
Host smart-edf7e8f5-de7b-4d31-9c79-1734d5bf2b8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68691
5321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.686915321
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.708885677
Short name T279
Test name
Test status
Simulation time 115605702296 ps
CPU time 2071.67 seconds
Started Apr 02 01:02:09 PM PDT 24
Finished Apr 02 01:36:41 PM PDT 24
Peak memory 285732 kb
Host smart-5fcbbb05-8f31-411f-b806-080e46061c45
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708885677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_han
dler_stress_all.708885677
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.2106833752
Short name T80
Test name
Test status
Simulation time 96261774815 ps
CPU time 7668.79 seconds
Started Apr 02 01:02:08 PM PDT 24
Finished Apr 02 03:09:58 PM PDT 24
Peak memory 363128 kb
Host smart-c45581bd-7e9b-48f3-ab33-fda4271639bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106833752 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.2106833752
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.2399136072
Short name T643
Test name
Test status
Simulation time 74800736043 ps
CPU time 2730.48 seconds
Started Apr 02 01:02:09 PM PDT 24
Finished Apr 02 01:47:40 PM PDT 24
Peak memory 288432 kb
Host smart-588d93c1-d79b-42e0-89c5-b317dfc8929b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399136072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.2399136072
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.2468515941
Short name T490
Test name
Test status
Simulation time 12397345661 ps
CPU time 161.85 seconds
Started Apr 02 01:02:09 PM PDT 24
Finished Apr 02 01:04:51 PM PDT 24
Peak memory 257056 kb
Host smart-d9a40679-0f17-44ef-ab15-534db32fd410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24685
15941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.2468515941
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.2739727743
Short name T384
Test name
Test status
Simulation time 259946582 ps
CPU time 16.63 seconds
Started Apr 02 01:02:09 PM PDT 24
Finished Apr 02 01:02:25 PM PDT 24
Peak memory 253048 kb
Host smart-ef095769-b12b-45a9-8923-59f123a112d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27397
27743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.2739727743
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.1372774897
Short name T614
Test name
Test status
Simulation time 9426623323 ps
CPU time 668.77 seconds
Started Apr 02 01:02:06 PM PDT 24
Finished Apr 02 01:13:15 PM PDT 24
Peak memory 265372 kb
Host smart-5ac72dc6-a203-4d6e-8dbf-6e5a41c9c67e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372774897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.1372774897
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.3614774510
Short name T505
Test name
Test status
Simulation time 31052445297 ps
CPU time 1505.09 seconds
Started Apr 02 01:02:07 PM PDT 24
Finished Apr 02 01:27:12 PM PDT 24
Peak memory 289460 kb
Host smart-d8a20dd4-87fb-47e3-9321-4ee6e87ee1f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614774510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.3614774510
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.1830488302
Short name T687
Test name
Test status
Simulation time 13273464873 ps
CPU time 538.75 seconds
Started Apr 02 01:02:10 PM PDT 24
Finished Apr 02 01:11:09 PM PDT 24
Peak memory 248296 kb
Host smart-3aa030c5-2d9b-4144-931d-8f10ec2dc6a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830488302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.1830488302
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.3830811226
Short name T493
Test name
Test status
Simulation time 1698537393 ps
CPU time 47.95 seconds
Started Apr 02 01:02:07 PM PDT 24
Finished Apr 02 01:02:55 PM PDT 24
Peak memory 255968 kb
Host smart-05f5019b-2839-4b33-b3ff-4c58d953e05e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38308
11226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.3830811226
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.1521437191
Short name T84
Test name
Test status
Simulation time 213397463 ps
CPU time 16.9 seconds
Started Apr 02 01:02:09 PM PDT 24
Finished Apr 02 01:02:26 PM PDT 24
Peak memory 254476 kb
Host smart-db8733c5-c19b-4ecd-8c4c-d81bb5f30607
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15214
37191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.1521437191
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.3955816243
Short name T445
Test name
Test status
Simulation time 598940485 ps
CPU time 10.78 seconds
Started Apr 02 01:02:08 PM PDT 24
Finished Apr 02 01:02:19 PM PDT 24
Peak memory 248836 kb
Host smart-dc9f7268-16cc-4f04-ba81-08127b1696be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39558
16243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.3955816243
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.23979166
Short name T481
Test name
Test status
Simulation time 8001005723 ps
CPU time 75.18 seconds
Started Apr 02 01:02:11 PM PDT 24
Finished Apr 02 01:03:26 PM PDT 24
Peak memory 248700 kb
Host smart-2686e0b5-f704-4175-8914-2ee6aae4ce42
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23979166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_hand
ler_stress_all.23979166
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.482077117
Short name T526
Test name
Test status
Simulation time 405976108566 ps
CPU time 2020.36 seconds
Started Apr 02 01:02:11 PM PDT 24
Finished Apr 02 01:35:51 PM PDT 24
Peak memory 283204 kb
Host smart-fa076b5c-cb7c-49bd-aa50-9706de20f8bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482077117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.482077117
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.3554271389
Short name T514
Test name
Test status
Simulation time 4626128135 ps
CPU time 57.39 seconds
Started Apr 02 01:02:09 PM PDT 24
Finished Apr 02 01:03:07 PM PDT 24
Peak memory 256932 kb
Host smart-20e7bf83-fc0b-471f-a8e2-49ed44abf907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35542
71389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.3554271389
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.3378571221
Short name T457
Test name
Test status
Simulation time 1206726676 ps
CPU time 27.58 seconds
Started Apr 02 01:02:09 PM PDT 24
Finished Apr 02 01:02:37 PM PDT 24
Peak memory 255608 kb
Host smart-c42907b6-5e13-4e7b-8630-faa9a5d66495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33785
71221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.3378571221
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.2705656403
Short name T706
Test name
Test status
Simulation time 81673384790 ps
CPU time 2480.37 seconds
Started Apr 02 01:02:13 PM PDT 24
Finished Apr 02 01:43:34 PM PDT 24
Peak memory 288328 kb
Host smart-83a19726-834a-4b35-b957-3fd65015b214
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705656403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.2705656403
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.3502056790
Short name T276
Test name
Test status
Simulation time 15250820603 ps
CPU time 1071.66 seconds
Started Apr 02 01:02:13 PM PDT 24
Finished Apr 02 01:20:05 PM PDT 24
Peak memory 273556 kb
Host smart-c5749766-6ca6-405f-a524-30ec8046bf9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502056790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.3502056790
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.1959102600
Short name T311
Test name
Test status
Simulation time 89701054446 ps
CPU time 245.77 seconds
Started Apr 02 01:02:16 PM PDT 24
Finished Apr 02 01:06:22 PM PDT 24
Peak memory 247724 kb
Host smart-8801b5d4-7c69-4efb-a13c-d5ae64e6c2bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959102600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.1959102600
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.4198610775
Short name T177
Test name
Test status
Simulation time 1618033200 ps
CPU time 26.19 seconds
Started Apr 02 01:02:10 PM PDT 24
Finished Apr 02 01:02:37 PM PDT 24
Peak memory 256064 kb
Host smart-b96daec9-608b-4355-b335-31619502e2aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41986
10775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.4198610775
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.3495431581
Short name T282
Test name
Test status
Simulation time 713206888 ps
CPU time 33.31 seconds
Started Apr 02 01:02:10 PM PDT 24
Finished Apr 02 01:02:44 PM PDT 24
Peak memory 256172 kb
Host smart-3abe9e42-7d6f-41cb-b000-cdf7bd0e3052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34954
31581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.3495431581
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.3354434035
Short name T263
Test name
Test status
Simulation time 612536442 ps
CPU time 29.62 seconds
Started Apr 02 01:02:08 PM PDT 24
Finished Apr 02 01:02:38 PM PDT 24
Peak memory 255816 kb
Host smart-350d8e23-912d-42d7-ac5c-f6a006c0ffc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33544
34035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.3354434035
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.2357991701
Short name T644
Test name
Test status
Simulation time 70805843 ps
CPU time 5.72 seconds
Started Apr 02 01:02:10 PM PDT 24
Finished Apr 02 01:02:16 PM PDT 24
Peak memory 240572 kb
Host smart-b3401aef-9121-4812-988d-022759735605
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23579
91701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.2357991701
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.3263620563
Short name T675
Test name
Test status
Simulation time 1580889971 ps
CPU time 149.59 seconds
Started Apr 02 01:02:14 PM PDT 24
Finished Apr 02 01:04:44 PM PDT 24
Peak memory 256940 kb
Host smart-2b42c690-ba4b-4596-822d-9cab228c9a0f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263620563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.3263620563
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.3974038018
Short name T714
Test name
Test status
Simulation time 26210890674 ps
CPU time 2903.71 seconds
Started Apr 02 01:02:14 PM PDT 24
Finished Apr 02 01:50:38 PM PDT 24
Peak memory 322764 kb
Host smart-6822a4ee-a058-43d4-939c-847a22a05d14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974038018 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.3974038018
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.1948562907
Short name T66
Test name
Test status
Simulation time 18711310917 ps
CPU time 1215.6 seconds
Started Apr 02 01:02:19 PM PDT 24
Finished Apr 02 01:22:35 PM PDT 24
Peak memory 273024 kb
Host smart-a1ba30f8-c8bf-4e66-bb57-702d362acc9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948562907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.1948562907
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.3676532719
Short name T386
Test name
Test status
Simulation time 2293145800 ps
CPU time 136.32 seconds
Started Apr 02 01:02:15 PM PDT 24
Finished Apr 02 01:04:32 PM PDT 24
Peak memory 248888 kb
Host smart-6c3fb324-946d-4d6b-921d-4618fdb7f656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36765
32719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.3676532719
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.1950922332
Short name T518
Test name
Test status
Simulation time 950894031 ps
CPU time 23.25 seconds
Started Apr 02 01:02:15 PM PDT 24
Finished Apr 02 01:02:38 PM PDT 24
Peak memory 255628 kb
Host smart-2759fc53-8687-4e26-ae2f-0b9281388a05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19509
22332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.1950922332
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.3970872696
Short name T330
Test name
Test status
Simulation time 55740433455 ps
CPU time 1251.99 seconds
Started Apr 02 01:02:19 PM PDT 24
Finished Apr 02 01:23:11 PM PDT 24
Peak memory 273568 kb
Host smart-03611bed-ec90-424f-b5e2-4e84cf168e2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970872696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.3970872696
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.3315552313
Short name T522
Test name
Test status
Simulation time 30332002336 ps
CPU time 1636.29 seconds
Started Apr 02 01:02:19 PM PDT 24
Finished Apr 02 01:29:36 PM PDT 24
Peak memory 289564 kb
Host smart-afbedab0-bc93-42b2-b8c1-3bb085872745
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315552313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.3315552313
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.4187900047
Short name T10
Test name
Test status
Simulation time 5817174230 ps
CPU time 240.65 seconds
Started Apr 02 01:02:19 PM PDT 24
Finished Apr 02 01:06:20 PM PDT 24
Peak memory 247120 kb
Host smart-0578abcb-c2c1-48c7-9eed-62bd93de2570
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187900047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.4187900047
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.3153613468
Short name T443
Test name
Test status
Simulation time 2378836914 ps
CPU time 39.62 seconds
Started Apr 02 01:02:14 PM PDT 24
Finished Apr 02 01:02:54 PM PDT 24
Peak memory 248948 kb
Host smart-157e1517-b358-40a4-aa8a-4f13e88b02b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31536
13468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.3153613468
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.4035329933
Short name T366
Test name
Test status
Simulation time 365754842 ps
CPU time 17.21 seconds
Started Apr 02 01:02:15 PM PDT 24
Finished Apr 02 01:02:32 PM PDT 24
Peak memory 256452 kb
Host smart-5b8ff9b2-1aba-4a93-9677-270c486dc8b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40353
29933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.4035329933
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.1372384315
Short name T50
Test name
Test status
Simulation time 60883163 ps
CPU time 7.68 seconds
Started Apr 02 01:02:13 PM PDT 24
Finished Apr 02 01:02:22 PM PDT 24
Peak memory 252636 kb
Host smart-e2508b0a-fa7a-421f-ae10-ffbcf73bb0fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13723
84315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.1372384315
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.385425996
Short name T561
Test name
Test status
Simulation time 6406901943 ps
CPU time 29.88 seconds
Started Apr 02 01:02:22 PM PDT 24
Finished Apr 02 01:02:52 PM PDT 24
Peak memory 249020 kb
Host smart-50e9c7fe-ff9d-4472-9d25-864a469865c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38542
5996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.385425996
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.2510203114
Short name T478
Test name
Test status
Simulation time 222019985305 ps
CPU time 2874.37 seconds
Started Apr 02 01:02:18 PM PDT 24
Finished Apr 02 01:50:14 PM PDT 24
Peak memory 305908 kb
Host smart-23af2535-e132-4b3d-a127-490c56d880d6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510203114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.2510203114
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.2148258540
Short name T529
Test name
Test status
Simulation time 14111303108 ps
CPU time 127.04 seconds
Started Apr 02 01:02:19 PM PDT 24
Finished Apr 02 01:04:26 PM PDT 24
Peak memory 256284 kb
Host smart-0be2a792-5a02-46e8-bb1e-18aa56e3c7c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21482
58540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.2148258540
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.2583314137
Short name T470
Test name
Test status
Simulation time 72831042 ps
CPU time 5.7 seconds
Started Apr 02 01:02:22 PM PDT 24
Finished Apr 02 01:02:28 PM PDT 24
Peak memory 253632 kb
Host smart-52cbe2f5-14fb-4d2c-81c0-40670f1ef94d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25833
14137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.2583314137
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.3923043454
Short name T603
Test name
Test status
Simulation time 20889856669 ps
CPU time 1536.89 seconds
Started Apr 02 01:02:22 PM PDT 24
Finished Apr 02 01:27:59 PM PDT 24
Peak memory 289256 kb
Host smart-df48aeb0-d8e0-49ab-8d5a-a919fb3fe0d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923043454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.3923043454
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.3064840262
Short name T615
Test name
Test status
Simulation time 8221694394 ps
CPU time 723.91 seconds
Started Apr 02 01:02:20 PM PDT 24
Finished Apr 02 01:14:24 PM PDT 24
Peak memory 265392 kb
Host smart-efdd2483-ccce-43a6-96f7-f45a62b5e6e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064840262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3064840262
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.3350623102
Short name T307
Test name
Test status
Simulation time 25729434315 ps
CPU time 267.06 seconds
Started Apr 02 01:02:22 PM PDT 24
Finished Apr 02 01:06:50 PM PDT 24
Peak memory 247212 kb
Host smart-7c1a703b-81f9-4a62-954b-447c09643c79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350623102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.3350623102
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.2202255382
Short name T546
Test name
Test status
Simulation time 287574139 ps
CPU time 23.56 seconds
Started Apr 02 01:02:18 PM PDT 24
Finished Apr 02 01:02:42 PM PDT 24
Peak memory 255152 kb
Host smart-7a204806-cb6e-48f4-86d8-61ec259e285e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22022
55382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.2202255382
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.640552238
Short name T580
Test name
Test status
Simulation time 332171401 ps
CPU time 36.57 seconds
Started Apr 02 01:02:19 PM PDT 24
Finished Apr 02 01:02:56 PM PDT 24
Peak memory 249188 kb
Host smart-d05d8298-5c3e-4c20-aa62-308f56a77196
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64055
2238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.640552238
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.2127055800
Short name T250
Test name
Test status
Simulation time 98293867 ps
CPU time 13.86 seconds
Started Apr 02 01:02:22 PM PDT 24
Finished Apr 02 01:02:36 PM PDT 24
Peak memory 248832 kb
Host smart-0bdc0cc5-b832-4b05-99dc-4fdd1287b550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21270
55800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.2127055800
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.1651475374
Short name T76
Test name
Test status
Simulation time 72950582 ps
CPU time 9.47 seconds
Started Apr 02 01:02:18 PM PDT 24
Finished Apr 02 01:02:28 PM PDT 24
Peak memory 248828 kb
Host smart-0b46f9be-8be9-4742-9bf2-59509644e326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16514
75374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.1651475374
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.4148622626
Short name T438
Test name
Test status
Simulation time 29197476856 ps
CPU time 822.94 seconds
Started Apr 02 01:02:22 PM PDT 24
Finished Apr 02 01:16:05 PM PDT 24
Peak memory 273784 kb
Host smart-8ff0206a-6f8e-4a8c-9f17-cca04093e943
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148622626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.4148622626
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.30467613
Short name T88
Test name
Test status
Simulation time 504441575590 ps
CPU time 4064.45 seconds
Started Apr 02 01:02:25 PM PDT 24
Finished Apr 02 02:10:11 PM PDT 24
Peak memory 298212 kb
Host smart-a26d095d-750e-428f-bacc-7ead365abe6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30467613 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.30467613
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.2641469766
Short name T283
Test name
Test status
Simulation time 38203589282 ps
CPU time 1210.08 seconds
Started Apr 02 01:02:25 PM PDT 24
Finished Apr 02 01:22:36 PM PDT 24
Peak memory 273572 kb
Host smart-8fd77c7c-8a91-4243-b633-ee7ce61ba388
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641469766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.2641469766
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.4026011354
Short name T472
Test name
Test status
Simulation time 2654711010 ps
CPU time 90.39 seconds
Started Apr 02 01:02:25 PM PDT 24
Finished Apr 02 01:03:56 PM PDT 24
Peak memory 248876 kb
Host smart-c66b12c1-f163-411f-9bff-81a473f479bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40260
11354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.4026011354
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.21285611
Short name T55
Test name
Test status
Simulation time 2538334946 ps
CPU time 81.37 seconds
Started Apr 02 01:02:19 PM PDT 24
Finished Apr 02 01:03:41 PM PDT 24
Peak memory 255304 kb
Host smart-c7a16c32-92f2-4805-aa3e-4550e2f73d98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21285
611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.21285611
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.911286934
Short name T340
Test name
Test status
Simulation time 10792936153 ps
CPU time 845.44 seconds
Started Apr 02 01:02:27 PM PDT 24
Finished Apr 02 01:16:33 PM PDT 24
Peak memory 265312 kb
Host smart-81b95ec9-5e1a-4d4c-8f48-feb48cf2dc33
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911286934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.911286934
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2476376529
Short name T483
Test name
Test status
Simulation time 199966485520 ps
CPU time 2879.82 seconds
Started Apr 02 01:02:25 PM PDT 24
Finished Apr 02 01:50:26 PM PDT 24
Peak memory 286372 kb
Host smart-f6a86a22-e33d-4e66-abd4-c3d5f07bd25d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476376529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2476376529
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.2156025037
Short name T312
Test name
Test status
Simulation time 11521611604 ps
CPU time 268.74 seconds
Started Apr 02 01:02:26 PM PDT 24
Finished Apr 02 01:06:55 PM PDT 24
Peak memory 248064 kb
Host smart-e7f83f1d-8ce6-4905-a487-68006e823df2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156025037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.2156025037
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.550806916
Short name T65
Test name
Test status
Simulation time 298018941 ps
CPU time 10.71 seconds
Started Apr 02 01:02:20 PM PDT 24
Finished Apr 02 01:02:31 PM PDT 24
Peak memory 248888 kb
Host smart-048b64e9-c656-446d-9473-6a2110bd3006
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55080
6916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.550806916
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.598308969
Short name T596
Test name
Test status
Simulation time 2683175346 ps
CPU time 48.15 seconds
Started Apr 02 01:02:25 PM PDT 24
Finished Apr 02 01:03:14 PM PDT 24
Peak memory 255668 kb
Host smart-c5ebc741-67e1-4118-8226-849a4f28f440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59830
8969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.598308969
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.3810364805
Short name T571
Test name
Test status
Simulation time 684177305 ps
CPU time 41.91 seconds
Started Apr 02 01:02:25 PM PDT 24
Finished Apr 02 01:03:07 PM PDT 24
Peak memory 254708 kb
Host smart-57172f86-d58d-44a1-a080-cf5b4213f832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38103
64805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.3810364805
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.2831208354
Short name T418
Test name
Test status
Simulation time 886061681 ps
CPU time 15.27 seconds
Started Apr 02 01:02:27 PM PDT 24
Finished Apr 02 01:02:42 PM PDT 24
Peak memory 248900 kb
Host smart-ab37e82a-1a3b-4ec0-bad8-54ac9bb96b4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28312
08354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.2831208354
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.1871040330
Short name T53
Test name
Test status
Simulation time 69282364082 ps
CPU time 4126.69 seconds
Started Apr 02 01:02:24 PM PDT 24
Finished Apr 02 02:11:11 PM PDT 24
Peak memory 306084 kb
Host smart-6747f44f-af5e-4924-9680-53e7f457997a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871040330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.1871040330
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.728447065
Short name T27
Test name
Test status
Simulation time 207148800467 ps
CPU time 1507.91 seconds
Started Apr 02 01:02:23 PM PDT 24
Finished Apr 02 01:27:31 PM PDT 24
Peak memory 289688 kb
Host smart-5d89f418-65bf-4e72-883a-b3df839b6833
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728447065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.728447065
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.3504595904
Short name T38
Test name
Test status
Simulation time 1796286445 ps
CPU time 127.89 seconds
Started Apr 02 01:02:27 PM PDT 24
Finished Apr 02 01:04:35 PM PDT 24
Peak memory 256972 kb
Host smart-c8414e39-22ac-4d55-8150-984672d8b075
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35045
95904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.3504595904
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.3160631183
Short name T612
Test name
Test status
Simulation time 839571503 ps
CPU time 33.07 seconds
Started Apr 02 01:02:25 PM PDT 24
Finished Apr 02 01:02:58 PM PDT 24
Peak memory 255536 kb
Host smart-324de4b8-71c3-4b7c-9760-2c43abb2849d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31606
31183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.3160631183
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.3275385214
Short name T542
Test name
Test status
Simulation time 76179824813 ps
CPU time 1578.16 seconds
Started Apr 02 01:02:23 PM PDT 24
Finished Apr 02 01:28:42 PM PDT 24
Peak memory 289428 kb
Host smart-617ef32c-ec12-4d2e-aef9-32273a01f6bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275385214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.3275385214
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.1742592096
Short name T599
Test name
Test status
Simulation time 193339857243 ps
CPU time 2185.88 seconds
Started Apr 02 01:02:24 PM PDT 24
Finished Apr 02 01:38:50 PM PDT 24
Peak memory 281784 kb
Host smart-a4cf2d39-6094-4577-89cb-8b45b295f344
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742592096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.1742592096
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.2179149342
Short name T324
Test name
Test status
Simulation time 33211677704 ps
CPU time 366.11 seconds
Started Apr 02 01:02:26 PM PDT 24
Finished Apr 02 01:08:32 PM PDT 24
Peak memory 247796 kb
Host smart-eed3c4fd-8aa6-4ddf-ba93-5d3aa632d4dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179149342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.2179149342
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.570127768
Short name T397
Test name
Test status
Simulation time 287273612 ps
CPU time 5.18 seconds
Started Apr 02 01:02:25 PM PDT 24
Finished Apr 02 01:02:30 PM PDT 24
Peak memory 240644 kb
Host smart-73965774-51fb-41d0-af68-4510dd70be6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57012
7768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.570127768
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.2548608385
Short name T477
Test name
Test status
Simulation time 1145588755 ps
CPU time 6.68 seconds
Started Apr 02 01:02:25 PM PDT 24
Finished Apr 02 01:02:32 PM PDT 24
Peak memory 238948 kb
Host smart-4e0b09cd-6ca5-4cda-bce1-b9b150f615df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25486
08385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.2548608385
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.1099798657
Short name T253
Test name
Test status
Simulation time 3300629188 ps
CPU time 45.58 seconds
Started Apr 02 01:02:24 PM PDT 24
Finished Apr 02 01:03:10 PM PDT 24
Peak memory 256172 kb
Host smart-c13359ad-6710-4bca-b9a7-99cca458dcf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10997
98657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.1099798657
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.4287897904
Short name T537
Test name
Test status
Simulation time 154961771 ps
CPU time 3.5 seconds
Started Apr 02 01:02:24 PM PDT 24
Finished Apr 02 01:02:28 PM PDT 24
Peak memory 240724 kb
Host smart-1e40e296-6de7-41d9-90ce-d4f55d33fdce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42878
97904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.4287897904
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.2760115969
Short name T56
Test name
Test status
Simulation time 280895612 ps
CPU time 26.49 seconds
Started Apr 02 01:02:23 PM PDT 24
Finished Apr 02 01:02:50 PM PDT 24
Peak memory 256304 kb
Host smart-3c16f8ec-a3b1-4692-bc5b-3750b3de9d06
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760115969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.2760115969
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.871111006
Short name T212
Test name
Test status
Simulation time 153368125 ps
CPU time 3.71 seconds
Started Apr 02 01:00:51 PM PDT 24
Finished Apr 02 01:00:58 PM PDT 24
Peak memory 249100 kb
Host smart-0e8d6c1c-26f3-49e3-a39d-87c82589e731
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=871111006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.871111006
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.1102336203
Short name T447
Test name
Test status
Simulation time 282618545955 ps
CPU time 2262.62 seconds
Started Apr 02 01:00:44 PM PDT 24
Finished Apr 02 01:38:27 PM PDT 24
Peak memory 285980 kb
Host smart-dfbaf9f8-e6d6-42b9-943c-fba3395e3991
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102336203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.1102336203
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.714628348
Short name T359
Test name
Test status
Simulation time 12857091652 ps
CPU time 101.24 seconds
Started Apr 02 01:01:11 PM PDT 24
Finished Apr 02 01:02:58 PM PDT 24
Peak memory 256540 kb
Host smart-1ec1ab8f-5c8f-4416-a729-adc2099f218d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71462
8348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.714628348
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.2441042881
Short name T236
Test name
Test status
Simulation time 134658951 ps
CPU time 3.44 seconds
Started Apr 02 01:01:08 PM PDT 24
Finished Apr 02 01:01:17 PM PDT 24
Peak memory 240528 kb
Host smart-34ce1c60-c6a6-480e-8da9-5d05813c10b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24410
42881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.2441042881
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.2758900239
Short name T697
Test name
Test status
Simulation time 41440481325 ps
CPU time 2272.53 seconds
Started Apr 02 01:00:59 PM PDT 24
Finished Apr 02 01:38:53 PM PDT 24
Peak memory 289048 kb
Host smart-60752760-762e-4b95-8690-9f5be3636790
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758900239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2758900239
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.1563969795
Short name T454
Test name
Test status
Simulation time 61679962487 ps
CPU time 1114.26 seconds
Started Apr 02 01:01:03 PM PDT 24
Finished Apr 02 01:19:39 PM PDT 24
Peak memory 272872 kb
Host smart-d22f1a16-7e99-46c5-aa7a-3270ebedabae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563969795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.1563969795
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.245940479
Short name T568
Test name
Test status
Simulation time 46788960004 ps
CPU time 451.3 seconds
Started Apr 02 01:00:51 PM PDT 24
Finished Apr 02 01:08:25 PM PDT 24
Peak memory 247936 kb
Host smart-e00795cf-8abf-4d34-9ea7-7bc3411d82ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245940479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.245940479
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.1233277191
Short name T450
Test name
Test status
Simulation time 1177899527 ps
CPU time 37.43 seconds
Started Apr 02 01:01:08 PM PDT 24
Finished Apr 02 01:01:51 PM PDT 24
Peak memory 248688 kb
Host smart-4b1d082d-bdef-4986-b503-63cb062f6351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12332
77191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1233277191
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.2689881572
Short name T286
Test name
Test status
Simulation time 62581045 ps
CPU time 4.54 seconds
Started Apr 02 01:00:39 PM PDT 24
Finished Apr 02 01:00:43 PM PDT 24
Peak memory 239216 kb
Host smart-b1c16438-9d71-4791-9a24-e0db3e505dae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26898
81572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.2689881572
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.1176752565
Short name T465
Test name
Test status
Simulation time 355659158 ps
CPU time 24.69 seconds
Started Apr 02 01:00:49 PM PDT 24
Finished Apr 02 01:01:15 PM PDT 24
Peak memory 255836 kb
Host smart-6f4804b8-a559-4953-aaf1-3b1a76fbcc12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11767
52565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.1176752565
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.1174334999
Short name T34
Test name
Test status
Simulation time 1115862774 ps
CPU time 38.75 seconds
Started Apr 02 01:00:51 PM PDT 24
Finished Apr 02 01:01:33 PM PDT 24
Peak memory 248872 kb
Host smart-8bacd88a-4b05-4c82-ac8c-1087558b8db8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11743
34999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.1174334999
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.4256545294
Short name T480
Test name
Test status
Simulation time 1260147844 ps
CPU time 78.2 seconds
Started Apr 02 01:00:45 PM PDT 24
Finished Apr 02 01:02:04 PM PDT 24
Peak memory 248888 kb
Host smart-bdd563d3-7030-4fe8-9b9f-fa5fa6ed9245
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256545294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.4256545294
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.2817558271
Short name T205
Test name
Test status
Simulation time 176948632 ps
CPU time 4.19 seconds
Started Apr 02 01:00:58 PM PDT 24
Finished Apr 02 01:01:03 PM PDT 24
Peak memory 249152 kb
Host smart-f94a2709-44fa-48ca-bdcb-3f644eab87cb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2817558271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.2817558271
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2512393708
Short name T484
Test name
Test status
Simulation time 32398418080 ps
CPU time 1894.25 seconds
Started Apr 02 01:00:53 PM PDT 24
Finished Apr 02 01:32:31 PM PDT 24
Peak memory 272820 kb
Host smart-a7292c80-b635-4722-a3c7-089fc204c9e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512393708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2512393708
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.3040798795
Short name T503
Test name
Test status
Simulation time 510952322 ps
CPU time 21.02 seconds
Started Apr 02 01:00:46 PM PDT 24
Finished Apr 02 01:01:08 PM PDT 24
Peak memory 240636 kb
Host smart-c2563f48-767b-4893-bf1e-c93e54d18a67
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3040798795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.3040798795
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.3284813787
Short name T578
Test name
Test status
Simulation time 3894921709 ps
CPU time 13.32 seconds
Started Apr 02 01:00:55 PM PDT 24
Finished Apr 02 01:01:10 PM PDT 24
Peak memory 254300 kb
Host smart-80ea7c62-c6a2-4e56-a9c7-9716ff6d4417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32848
13787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.3284813787
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.2961129798
Short name T566
Test name
Test status
Simulation time 396018480 ps
CPU time 6.27 seconds
Started Apr 02 01:00:50 PM PDT 24
Finished Apr 02 01:00:58 PM PDT 24
Peak memory 247408 kb
Host smart-750f9b7b-d96c-4d26-8cc7-f1e7b19756f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29611
29798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.2961129798
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.37683421
Short name T319
Test name
Test status
Simulation time 37236033257 ps
CPU time 2034.98 seconds
Started Apr 02 01:00:52 PM PDT 24
Finished Apr 02 01:34:51 PM PDT 24
Peak memory 282968 kb
Host smart-555f9204-ac7c-457a-a03f-a59ac68c0078
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37683421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.37683421
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.520540586
Short name T79
Test name
Test status
Simulation time 111612930522 ps
CPU time 1719.99 seconds
Started Apr 02 01:00:47 PM PDT 24
Finished Apr 02 01:29:27 PM PDT 24
Peak memory 273312 kb
Host smart-cb661ce0-3a9a-4186-be69-0df233457153
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520540586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.520540586
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.3298151267
Short name T524
Test name
Test status
Simulation time 593376158 ps
CPU time 14.01 seconds
Started Apr 02 01:00:47 PM PDT 24
Finished Apr 02 01:01:01 PM PDT 24
Peak memory 248800 kb
Host smart-20a6d0fc-9b59-4bdc-a00c-12631ba7489c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32981
51267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3298151267
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.2614118093
Short name T235
Test name
Test status
Simulation time 5449920499 ps
CPU time 17.6 seconds
Started Apr 02 01:00:49 PM PDT 24
Finished Apr 02 01:01:09 PM PDT 24
Peak memory 253880 kb
Host smart-4398b6a6-0c7e-462c-b306-c3c107f0507d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26141
18093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.2614118093
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.2737180071
Short name T710
Test name
Test status
Simulation time 3688963631 ps
CPU time 65.86 seconds
Started Apr 02 01:00:49 PM PDT 24
Finished Apr 02 01:01:56 PM PDT 24
Peak memory 255644 kb
Host smart-09e6b9e0-8220-4204-b97e-df2c0f49b9d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27371
80071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.2737180071
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.1719201650
Short name T33
Test name
Test status
Simulation time 874684544 ps
CPU time 4.04 seconds
Started Apr 02 01:00:51 PM PDT 24
Finished Apr 02 01:00:58 PM PDT 24
Peak memory 240608 kb
Host smart-342f2bb0-42e6-4ef4-843e-ecfe74410516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17192
01650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.1719201650
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.3003149731
Short name T257
Test name
Test status
Simulation time 60074015996 ps
CPU time 1451.52 seconds
Started Apr 02 01:00:52 PM PDT 24
Finished Apr 02 01:25:08 PM PDT 24
Peak memory 288896 kb
Host smart-7dc1a103-4b6e-4785-bea0-6763322411cf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003149731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.3003149731
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.2808043677
Short name T49
Test name
Test status
Simulation time 535938744884 ps
CPU time 5295.71 seconds
Started Apr 02 01:00:56 PM PDT 24
Finished Apr 02 02:29:15 PM PDT 24
Peak memory 321528 kb
Host smart-ed0e70c7-5fc9-443e-89b7-eebd143ebaf1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808043677 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.2808043677
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.3089522935
Short name T215
Test name
Test status
Simulation time 44197949 ps
CPU time 2.52 seconds
Started Apr 02 01:00:59 PM PDT 24
Finished Apr 02 01:01:06 PM PDT 24
Peak memory 249092 kb
Host smart-fc2b8ce4-bcb1-4c72-94fc-e5f68476d604
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3089522935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.3089522935
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.1391028375
Short name T659
Test name
Test status
Simulation time 20185154642 ps
CPU time 1463.88 seconds
Started Apr 02 01:00:47 PM PDT 24
Finished Apr 02 01:25:12 PM PDT 24
Peak memory 269376 kb
Host smart-fb6af6df-5061-4db6-9397-204c761a78f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391028375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.1391028375
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.3841855042
Short name T602
Test name
Test status
Simulation time 4000772011 ps
CPU time 48.35 seconds
Started Apr 02 01:00:47 PM PDT 24
Finished Apr 02 01:01:36 PM PDT 24
Peak memory 240556 kb
Host smart-260bdac8-0623-4a5a-a9d1-687f729c52e1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3841855042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.3841855042
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.1389063205
Short name T36
Test name
Test status
Simulation time 8624545241 ps
CPU time 111.02 seconds
Started Apr 02 01:00:50 PM PDT 24
Finished Apr 02 01:02:42 PM PDT 24
Peak memory 257148 kb
Host smart-c2e0c523-7ae3-4c53-93ad-4f0466733e55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13890
63205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.1389063205
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.3740166612
Short name T375
Test name
Test status
Simulation time 1021682095 ps
CPU time 14.1 seconds
Started Apr 02 01:00:52 PM PDT 24
Finished Apr 02 01:01:10 PM PDT 24
Peak memory 248872 kb
Host smart-edf9a325-3870-4b6c-91a4-2b1675781eec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37401
66612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.3740166612
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.2284905229
Short name T333
Test name
Test status
Simulation time 19844535896 ps
CPU time 1837.92 seconds
Started Apr 02 01:00:57 PM PDT 24
Finished Apr 02 01:31:37 PM PDT 24
Peak memory 281772 kb
Host smart-d703c8bd-4e65-4fe9-a845-f448fab7ba86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284905229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.2284905229
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.2607118101
Short name T667
Test name
Test status
Simulation time 14731271680 ps
CPU time 1201.8 seconds
Started Apr 02 01:00:54 PM PDT 24
Finished Apr 02 01:20:58 PM PDT 24
Peak memory 281792 kb
Host smart-4242408d-c9dc-4622-863e-c244fae9b6ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607118101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.2607118101
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.1349820638
Short name T572
Test name
Test status
Simulation time 7826891714 ps
CPU time 332.57 seconds
Started Apr 02 01:01:01 PM PDT 24
Finished Apr 02 01:06:37 PM PDT 24
Peak memory 247856 kb
Host smart-18d984c5-60d6-4be0-aed9-bb65f3eef3c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349820638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.1349820638
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.157376087
Short name T371
Test name
Test status
Simulation time 75574969 ps
CPU time 4.69 seconds
Started Apr 02 01:01:07 PM PDT 24
Finished Apr 02 01:01:15 PM PDT 24
Peak memory 240680 kb
Host smart-de7d6e8c-f041-4ce6-ad0f-59954ca61622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15737
6087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.157376087
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.1588053211
Short name T414
Test name
Test status
Simulation time 310448902 ps
CPU time 27.55 seconds
Started Apr 02 01:01:08 PM PDT 24
Finished Apr 02 01:01:41 PM PDT 24
Peak memory 247668 kb
Host smart-0233b634-d39d-41aa-9d19-ccb49a1b507f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15880
53211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.1588053211
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.672962138
Short name T607
Test name
Test status
Simulation time 2490747761 ps
CPU time 41.31 seconds
Started Apr 02 01:01:02 PM PDT 24
Finished Apr 02 01:01:46 PM PDT 24
Peak memory 256068 kb
Host smart-04103912-4f4f-46c6-ae62-6ae34c811534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67296
2138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.672962138
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.1422428523
Short name T519
Test name
Test status
Simulation time 22035188 ps
CPU time 3.15 seconds
Started Apr 02 01:00:52 PM PDT 24
Finished Apr 02 01:00:59 PM PDT 24
Peak memory 240708 kb
Host smart-22782ddc-39e6-4095-afe8-8dcf7884b02d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14224
28523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.1422428523
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.2534064066
Short name T209
Test name
Test status
Simulation time 35713512 ps
CPU time 3.24 seconds
Started Apr 02 01:01:05 PM PDT 24
Finished Apr 02 01:01:11 PM PDT 24
Peak memory 249048 kb
Host smart-adb38d5c-21b5-4327-be6d-7291c84fe633
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2534064066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.2534064066
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.2351601976
Short name T74
Test name
Test status
Simulation time 50835628058 ps
CPU time 2862.75 seconds
Started Apr 02 01:01:17 PM PDT 24
Finished Apr 02 01:49:02 PM PDT 24
Peak memory 287236 kb
Host smart-e1cfb505-aebc-4762-91c3-62d2597a7a93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351601976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.2351601976
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.4042045484
Short name T385
Test name
Test status
Simulation time 243971114 ps
CPU time 14.98 seconds
Started Apr 02 01:00:55 PM PDT 24
Finished Apr 02 01:01:12 PM PDT 24
Peak memory 248872 kb
Host smart-97ad34ae-7752-4220-8698-3ca51631acb4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4042045484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.4042045484
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.4081791670
Short name T364
Test name
Test status
Simulation time 947838699 ps
CPU time 19.19 seconds
Started Apr 02 01:01:11 PM PDT 24
Finished Apr 02 01:01:36 PM PDT 24
Peak memory 256372 kb
Host smart-d7f3b9c8-b403-426d-b01f-cd359f5ab62a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40817
91670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.4081791670
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.3564165678
Short name T555
Test name
Test status
Simulation time 3426674122 ps
CPU time 58.35 seconds
Started Apr 02 01:00:52 PM PDT 24
Finished Apr 02 01:01:55 PM PDT 24
Peak memory 248840 kb
Host smart-4809f0a8-fc8c-4569-a4f2-b6f32576611d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35641
65678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3564165678
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.1059084333
Short name T295
Test name
Test status
Simulation time 128189459583 ps
CPU time 1756.75 seconds
Started Apr 02 01:01:06 PM PDT 24
Finished Apr 02 01:30:27 PM PDT 24
Peak memory 267376 kb
Host smart-61e4593f-d338-4e07-8650-393ae47a1637
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059084333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.1059084333
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.3989037802
Short name T621
Test name
Test status
Simulation time 167890756408 ps
CPU time 2387.13 seconds
Started Apr 02 01:00:51 PM PDT 24
Finished Apr 02 01:40:41 PM PDT 24
Peak memory 281788 kb
Host smart-e93bc32e-0916-41fa-b648-d116c1cf0b65
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989037802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.3989037802
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.3723637870
Short name T302
Test name
Test status
Simulation time 33249610901 ps
CPU time 368.4 seconds
Started Apr 02 01:01:08 PM PDT 24
Finished Apr 02 01:07:22 PM PDT 24
Peak memory 247936 kb
Host smart-53f97dbc-8979-4424-809c-7f046c54eb5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723637870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.3723637870
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.348028450
Short name T516
Test name
Test status
Simulation time 1179482815 ps
CPU time 26.92 seconds
Started Apr 02 01:00:52 PM PDT 24
Finished Apr 02 01:01:23 PM PDT 24
Peak memory 256068 kb
Host smart-dcbf1105-e14a-4fa1-9f37-ebc4735f78e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34802
8450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.348028450
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.2352401586
Short name T284
Test name
Test status
Simulation time 1024046700 ps
CPU time 35.7 seconds
Started Apr 02 01:01:05 PM PDT 24
Finished Apr 02 01:01:43 PM PDT 24
Peak memory 248752 kb
Host smart-76cdb078-ecba-40a3-853e-59d5705f9c38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23524
01586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.2352401586
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.828834798
Short name T556
Test name
Test status
Simulation time 779268231 ps
CPU time 45.4 seconds
Started Apr 02 01:01:05 PM PDT 24
Finished Apr 02 01:01:53 PM PDT 24
Peak memory 248876 kb
Host smart-e7a23420-5b4d-493f-976d-4df66d97953d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82883
4798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.828834798
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.2930038155
Short name T379
Test name
Test status
Simulation time 1310993599 ps
CPU time 23.49 seconds
Started Apr 02 01:01:29 PM PDT 24
Finished Apr 02 01:01:52 PM PDT 24
Peak memory 248788 kb
Host smart-b2085cd3-8c54-4f4b-8e86-62506490c954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29300
38155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.2930038155
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.2227099481
Short name T272
Test name
Test status
Simulation time 11407404390 ps
CPU time 730.93 seconds
Started Apr 02 01:01:15 PM PDT 24
Finished Apr 02 01:13:30 PM PDT 24
Peak memory 265408 kb
Host smart-489cd303-cefb-4973-81c7-bc8301abe4a1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227099481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.2227099481
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.771943929
Short name T208
Test name
Test status
Simulation time 34430203 ps
CPU time 2.3 seconds
Started Apr 02 01:00:56 PM PDT 24
Finished Apr 02 01:01:01 PM PDT 24
Peak memory 249044 kb
Host smart-122c8de5-6d1c-4efc-bf70-d4145d31bb77
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=771943929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.771943929
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.1564823319
Short name T513
Test name
Test status
Simulation time 77026545062 ps
CPU time 2592.81 seconds
Started Apr 02 01:01:09 PM PDT 24
Finished Apr 02 01:44:29 PM PDT 24
Peak memory 288904 kb
Host smart-d54a0879-eea5-4f74-8734-b6bbb6d94fdd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564823319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.1564823319
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.2227610228
Short name T576
Test name
Test status
Simulation time 826125142 ps
CPU time 36.46 seconds
Started Apr 02 01:00:55 PM PDT 24
Finished Apr 02 01:01:34 PM PDT 24
Peak memory 240696 kb
Host smart-d473b524-50c3-4312-bdca-919bcf9cf19c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2227610228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.2227610228
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.2711636354
Short name T372
Test name
Test status
Simulation time 3643420405 ps
CPU time 211.16 seconds
Started Apr 02 01:01:05 PM PDT 24
Finished Apr 02 01:04:40 PM PDT 24
Peak memory 256756 kb
Host smart-c5e4193a-0247-402c-af80-b91c23d9ebca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27116
36354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.2711636354
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.2342987539
Short name T394
Test name
Test status
Simulation time 427054208 ps
CPU time 7.23 seconds
Started Apr 02 01:00:51 PM PDT 24
Finished Apr 02 01:01:01 PM PDT 24
Peak memory 251032 kb
Host smart-c0c122d0-0b1a-4204-816d-ef8f25d2b48b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23429
87539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.2342987539
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.2755399716
Short name T101
Test name
Test status
Simulation time 18879725762 ps
CPU time 1501.29 seconds
Started Apr 02 01:01:13 PM PDT 24
Finished Apr 02 01:26:19 PM PDT 24
Peak memory 288888 kb
Host smart-918f47de-6f6d-41da-b148-7e52b2ba0246
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755399716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.2755399716
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.2505779943
Short name T234
Test name
Test status
Simulation time 257291609749 ps
CPU time 2782.62 seconds
Started Apr 02 01:00:51 PM PDT 24
Finished Apr 02 01:47:17 PM PDT 24
Peak memory 281780 kb
Host smart-59ff919c-96e9-4b25-9b53-5b6f8c1d5faf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505779943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2505779943
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.4104287497
Short name T515
Test name
Test status
Simulation time 28775262928 ps
CPU time 297.66 seconds
Started Apr 02 01:01:10 PM PDT 24
Finished Apr 02 01:06:14 PM PDT 24
Peak memory 248088 kb
Host smart-729b56b8-0b63-47a8-ae3c-a85371e72d1d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104287497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.4104287497
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.1532393267
Short name T567
Test name
Test status
Simulation time 33561011 ps
CPU time 4.04 seconds
Started Apr 02 01:00:54 PM PDT 24
Finished Apr 02 01:01:00 PM PDT 24
Peak memory 240700 kb
Host smart-20e734ac-8cb2-405e-9af4-9fd42d104769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15323
93267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.1532393267
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.2701117086
Short name T626
Test name
Test status
Simulation time 249686022 ps
CPU time 21.83 seconds
Started Apr 02 01:01:13 PM PDT 24
Finished Apr 02 01:01:40 PM PDT 24
Peak memory 248896 kb
Host smart-26bf8445-6825-466e-a617-095322202ee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27011
17086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.2701117086
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.3462304992
Short name T377
Test name
Test status
Simulation time 515509943 ps
CPU time 26.77 seconds
Started Apr 02 01:00:55 PM PDT 24
Finished Apr 02 01:01:23 PM PDT 24
Peak memory 247652 kb
Host smart-16a64e86-6601-4aed-a32f-ba2b37b3f5bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34623
04992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.3462304992
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.4095404783
Short name T512
Test name
Test status
Simulation time 1163793503 ps
CPU time 19.25 seconds
Started Apr 02 01:01:11 PM PDT 24
Finished Apr 02 01:01:36 PM PDT 24
Peak memory 255040 kb
Host smart-553ec867-d34e-4f33-973f-cc0ecc4fb413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40954
04783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.4095404783
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.2870005984
Short name T680
Test name
Test status
Simulation time 43859724842 ps
CPU time 2799.01 seconds
Started Apr 02 01:01:09 PM PDT 24
Finished Apr 02 01:47:55 PM PDT 24
Peak memory 289204 kb
Host smart-af89b11a-b67c-4aae-9b75-466dbfccfb6e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870005984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.2870005984
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.507428743
Short name T655
Test name
Test status
Simulation time 186978839050 ps
CPU time 4029.89 seconds
Started Apr 02 01:00:53 PM PDT 24
Finished Apr 02 02:08:07 PM PDT 24
Peak memory 306276 kb
Host smart-6e6820ca-67ba-4290-9e74-ac51b86cca95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507428743 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.507428743
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%