Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	99196	1			T1	465		T3	16		T4	3504
class_i[0x1]	43296	1			T3	9		T4	181		T56	19
class_i[0x2]	48143	1			T3	3		T4	13		T6	13
class_i[0x3]	62916	1			T1	801		T4	630		T5	962

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	62049	1			T1	169		T3	4		T4	1246
alert[0x1]	63934	1			T1	159		T3	3		T4	1288
alert[0x2]	63383	1			T1	240		T3	8		T4	943
alert[0x3]	64185	1			T1	698		T3	13		T4	851

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

253289

1

T1

1266

T3

17

T4

4328

esc_ping_fail

262

1

T3

11

T35

6

T36

10

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	61979	1			T1	169		T3	2		T4	1246
esc_integrity_fail	alert[0x1]	63865	1			T1	159		T3	2		T4	1288
esc_integrity_fail	alert[0x2]	63320	1			T1	240		T3	4		T4	943
esc_integrity_fail	alert[0x3]	64125	1			T1	698		T3	9		T4	851
esc_ping_fail	alert[0x0]	70	1			T3	2		T35	4		T36	4
esc_ping_fail	alert[0x1]	69	1			T3	1		T35	1		T36	3
esc_ping_fail	alert[0x2]	63	1			T3	4		T36	1		T302	4
esc_ping_fail	alert[0x3]	60	1			T3	4		T35	1		T36	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	99118	1			T1	465		T3	16		T4	3504
esc_integrity_fail	class_i[0x1]	43217	1			T4	181		T56	19		T6	3480
esc_integrity_fail	class_i[0x2]	48066	1			T3	1		T4	13		T6	13
esc_integrity_fail	class_i[0x3]	62888	1			T1	801		T4	630		T5	962
esc_ping_fail	class_i[0x0]	78	1			T35	6		T242	2		T319	1
esc_ping_fail	class_i[0x1]	79	1			T3	9		T36	10		T324	4
esc_ping_fail	class_i[0x2]	77	1			T3	2		T302	8		T306	3
esc_ping_fail	class_i[0x3]	28	1			T319	1		T306	1		T310	1