Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	6	34	85.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	6	34	85.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	61	1			T4	2		T5	1		T11	1
class_index[0x1]	45	1			T4	1		T11	1		T14	1
class_index[0x2]	65	1			T82	1		T44	1		T45	1
class_index[0x3]	49	1			T4	1		T27	1		T63	2

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	94	1			T5	1		T11	1		T14	1
intr_timeout_cnt[1]	43	1			T4	1		T11	1		T44	2
intr_timeout_cnt[2]	21	1			T4	2		T85	1		T27	1
intr_timeout_cnt[3]	14	1			T88	1		T119	1		T251	1
intr_timeout_cnt[4]	11	1			T87	1		T112	1		T93	1
intr_timeout_cnt[5]	7	1			T27	1		T64	1		T93	1
intr_timeout_cnt[6]	10	1			T82	1		T88	1		T112	1
intr_timeout_cnt[7]	9	1			T27	1		T93	1		T94	2
intr_timeout_cnt[8]	7	1			T68	1		T230	1		T252	1
intr_timeout_cnt[9]	4	1			T4	1		T253	1		T254	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	6	34	85.00	6

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[8]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[5] , intr_timeout_cnt[6] , intr_timeout_cnt[7]]	--	--	3
[class_index[0x1]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[5]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	27	1			T5	1		T64	1		T91	1
class_index[0x0]	intr_timeout_cnt[1]	9	1			T11	1		T92	1		T191	1
class_index[0x0]	intr_timeout_cnt[2]	10	1			T4	2		T85	1		T63	2
class_index[0x0]	intr_timeout_cnt[3]	4	1			T119	1		T72	1		T255	1
class_index[0x0]	intr_timeout_cnt[4]	1	1			T256	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[5]	4	1			T27	1		T108	1		T257	1
class_index[0x0]	intr_timeout_cnt[6]	2	1			T88	1		T258	1		-	-
class_index[0x0]	intr_timeout_cnt[7]	3	1			T93	1		T94	1		T232	1
class_index[0x0]	intr_timeout_cnt[9]	1	1			T259	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	24	1			T11	1		T14	1		T63	1
class_index[0x1]	intr_timeout_cnt[1]	13	1			T4	1		T44	1		T27	1
class_index[0x1]	intr_timeout_cnt[2]	1	1			T27	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[3]	2	1			T254	1		T260	1		-	-
class_index[0x1]	intr_timeout_cnt[4]	4	1			T93	1		T232	1		T103	1
class_index[0x1]	intr_timeout_cnt[8]	1	1			T261	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	30	1			T27	1		T77	1		T63	3
class_index[0x2]	intr_timeout_cnt[1]	12	1			T44	1		T45	1		T262	1
class_index[0x2]	intr_timeout_cnt[2]	2	1			T263	1		T264	1		-	-
class_index[0x2]	intr_timeout_cnt[3]	5	1			T251	1		T33	1		T265	2
class_index[0x2]	intr_timeout_cnt[4]	4	1			T87	1		T112	1		T247	2
class_index[0x2]	intr_timeout_cnt[6]	4	1			T82	1		T71	1		T266	1
class_index[0x2]	intr_timeout_cnt[7]	2	1			T27	1		T94	1		-	-
class_index[0x2]	intr_timeout_cnt[8]	5	1			T68	1		T230	1		T256	1
class_index[0x2]	intr_timeout_cnt[9]	1	1			T253	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	13	1			T27	1		T63	1		T112	1
class_index[0x3]	intr_timeout_cnt[1]	9	1			T63	1		T123	1		T101	1
class_index[0x3]	intr_timeout_cnt[2]	8	1			T88	1		T71	1		T267	3
class_index[0x3]	intr_timeout_cnt[3]	3	1			T88	1		T33	1		T268	1
class_index[0x3]	intr_timeout_cnt[4]	2	1			T185	1		T110	1		-	-
class_index[0x3]	intr_timeout_cnt[5]	3	1			T64	1		T93	1		T72	1
class_index[0x3]	intr_timeout_cnt[6]	4	1			T112	1		T94	1		T108	1
class_index[0x3]	intr_timeout_cnt[7]	4	1			T72	1		T269	1		T270	1
class_index[0x3]	intr_timeout_cnt[8]	1	1			T252	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	2	1			T4	1		T254	1		-	-