Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	330064	1			T1	612		T2	41		T3	61
all_values[1]	330064	1			T1	612		T2	41		T3	61
all_values[2]	330064	1			T1	612		T2	41		T3	61
all_values[3]	330064	1			T1	612		T2	41		T3	61

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

656570

1

T1

1316

T2

76

T4

4878

auto[1]

663686

1

T1

1132

T2

88

T3

244

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

789686

1

T1

1224

T2

144

T3

206

auto[1]

530570

1

T1

1224

T2

20

T3

38

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	96068	1			T1	163		T2	6		T4	628
all_values[0]	auto[0]	auto[1]	68387	1			T1	164		T2	6		T4	613
all_values[0]	auto[1]	auto[0]	96945	1			T1	143		T2	15		T3	51
all_values[0]	auto[1]	auto[1]	68664	1			T1	142		T2	14		T3	10
all_values[1]	auto[0]	auto[0]	98202	1			T1	178		T2	20		T4	741
all_values[1]	auto[0]	auto[1]	65717	1			T1	165		T4	450		T7	10
all_values[1]	auto[1]	auto[0]	100062	1			T1	133		T2	21		T3	51
all_values[1]	auto[1]	auto[1]	66083	1			T1	136		T3	10		T4	460
all_values[2]	auto[0]	auto[0]	98473	1			T1	158		T2	20		T4	856
all_values[2]	auto[0]	auto[1]	65481	1			T1	158		T4	384		T7	6
all_values[2]	auto[1]	auto[0]	100113	1			T1	151		T2	21		T3	55
all_values[2]	auto[1]	auto[1]	65997	1			T1	145		T3	6		T4	368
all_values[3]	auto[0]	auto[0]	99337	1			T1	163		T2	24		T4	732
all_values[3]	auto[0]	auto[1]	64905	1			T1	167		T4	474		T7	11
all_values[3]	auto[1]	auto[0]	100486	1			T1	135		T2	17		T3	49
all_values[3]	auto[1]	auto[1]	65336	1			T1	147		T3	12		T4	473