Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	330064	1			T1	612		T2	41		T3	61
all_pins[1]	330064	1			T1	612		T2	41		T3	61
all_pins[2]	330064	1			T1	612		T2	41		T3	61
all_pins[3]	330064	1			T1	612		T2	41		T3	61

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1054176	1			T1	1878		T2	150		T3	206
values[0x1]	266080	1			T1	570		T2	14		T3	38
transitions[0x0=>0x1]	176236	1			T1	371		T2	13		T3	30
transitions[0x1=>0x0]	176495	1			T1	371		T2	14		T3	30

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	261400	1			T1	470		T2	27		T3	51
all_pins[0]	values[0x1]	68664	1			T1	142		T2	14		T3	10
all_pins[0]	transitions[0x0=>0x1]	68047	1			T1	136		T2	13		T3	10
all_pins[0]	transitions[0x1=>0x0]	64978	1			T1	141		T3	12		T4	466
all_pins[1]	values[0x0]	263981	1			T1	476		T2	41		T3	51
all_pins[1]	values[0x1]	66083	1			T1	136		T3	10		T4	460
all_pins[1]	transitions[0x0=>0x1]	36460	1			T1	78		T3	2		T4	245
all_pins[1]	transitions[0x1=>0x0]	39041	1			T1	84		T2	14		T3	2
all_pins[2]	values[0x0]	264067	1			T1	467		T2	41		T3	55
all_pins[2]	values[0x1]	65997	1			T1	145		T3	6		T4	368
all_pins[2]	transitions[0x0=>0x1]	36244	1			T1	81		T3	6		T4	220
all_pins[2]	transitions[0x1=>0x0]	36330	1			T1	72		T3	10		T4	312
all_pins[3]	values[0x0]	264728	1			T1	465		T2	41		T3	49
all_pins[3]	values[0x1]	65336	1			T1	147		T3	12		T4	473
all_pins[3]	transitions[0x0=>0x1]	35485	1			T1	76		T3	12		T4	312
all_pins[3]	transitions[0x1=>0x0]	36146	1			T1	74		T3	6		T4	207