Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	272	1			T167	7		T169	4		T243	7
all_values[1]	272	1			T167	7		T169	4		T243	7
all_values[2]	272	1			T167	7		T169	4		T243	7
all_values[3]	272	1			T167	7		T169	4		T243	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

575

1

T167

10

T169

11

T243

16

auto[1]

513

1

T167

18

T169

5

T243

12

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

415

1

T167

16

T169

7

T243

7

auto[1]

673

1

T167

12

T169

9

T243

21

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

633

1

T167

18

T169

11

T243

14

auto[1]

455

1

T167

10

T169

5

T243

14

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

46

1

T169

2

T243

1

T244

2

all_values[0]

auto[0]

auto[0]

auto[1]

25

1

T347

1

T348

1

T349

1

all_values[0]

auto[0]

auto[1]

auto[0]

43

1

T167

5

T169

2

T244

1

all_values[0]

auto[0]

auto[1]

auto[1]

32

1

T243

1

T350

1

T351

1

all_values[0]

auto[1]

auto[0]

auto[1]

64

1

T167

2

T243

2

T244

1

all_values[0]

auto[1]

auto[1]

auto[1]

62

1

T243

3

T244

3

T351

1

all_values[1]

auto[0]

auto[0]

auto[0]

63

1

T167

2

T243

2

T244

2

all_values[1]

auto[0]

auto[0]

auto[1]

36

1

T169

2

T243

1

T350

1

all_values[1]

auto[0]

auto[1]

auto[0]

46

1

T244

1

T348

1

T352

1

all_values[1]

auto[0]

auto[1]

auto[1]

25

1

T167

2

T243

1

T350

1

all_values[1]

auto[1]

auto[0]

auto[1]

61

1

T167

1

T169

2

T244

1

all_values[1]

auto[1]

auto[1]

auto[1]

41

1

T167

2

T243

3

T244

3

all_values[2]

auto[0]

auto[0]

auto[0]

53

1

T167

1

T169

1

T243

1

all_values[2]

auto[0]

auto[0]

auto[1]

24

1

T243

2

T351

1

T347

1

all_values[2]

auto[0]

auto[1]

auto[0]

45

1

T167

3

T169

2

T243

1

all_values[2]

auto[0]

auto[1]

auto[1]

30

1

T350

2

T351

1

T353

1

all_values[2]

auto[1]

auto[0]

auto[1]

64

1

T167

2

T169

1

T243

2

all_values[2]

auto[1]

auto[1]

auto[1]

56

1

T167

1

T243

1

T244

1

all_values[3]

auto[0]

auto[0]

auto[0]

66

1

T167

2

T243

2

T244

5

all_values[3]

auto[0]

auto[0]

auto[1]

22

1

T169

1

T243

2

T350

2

all_values[3]

auto[0]

auto[1]

auto[0]

53

1

T167

3

T244

2

T350

2

all_values[3]

auto[0]

auto[1]

auto[1]

24

1

T169

1

T347

3

T354

1

all_values[3]

auto[1]

auto[0]

auto[1]

51

1

T169

2

T243

1

T350

1

all_values[3]

auto[1]

auto[1]

auto[1]

56

1

T167

2

T243

2

T350

2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal