Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	86479	1			T4	243		T6	212		T5	567
accum_cnt_1000	218977	1			T1	203		T4	1915		T15	10
accum_cnt_100	29854	1			T1	118		T2	12		T4	740
accum_cnt_50	58448	1			T1	106		T2	11		T4	491
accum_cnt_10	168358	1			T1	70		T2	7		T3	20
accum_cnt_0	372006	1			T1	1379		T2	94		T3	152

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	243750	1			T1	469		T2	31		T3	43
class_index[0x1]	243750	1			T1	469		T2	31		T3	43
class_index[0x2]	243750	1			T1	469		T2	31		T3	43
class_index[0x3]	243750	1			T1	469		T2	31		T3	43

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	23776	1			T4	243		T5	280		T42	179
class_index[0x0]	accum_cnt_1000	59103	1			T1	4		T4	512		T5	1419
class_index[0x0]	accum_cnt_100	9827	1			T1	43		T2	12		T4	202
class_index[0x0]	accum_cnt_50	17974	1			T1	27		T2	11		T4	183
class_index[0x0]	accum_cnt_10	40627	1			T1	15		T2	7		T3	20
class_index[0x0]	accum_cnt_0	80736	1			T1	380		T2	1		T3	23
class_index[0x1]	accum_cnt_2000	20423	1			T42	243		T11	402		T44	658
class_index[0x1]	accum_cnt_1000	60024	1			T4	799		T15	8		T37	775
class_index[0x1]	accum_cnt_100	7741	1			T4	102		T15	16		T37	164
class_index[0x1]	accum_cnt_50	12931	1			T4	87		T7	11		T8	15
class_index[0x1]	accum_cnt_10	34790	1			T1	2		T4	244		T7	10
class_index[0x1]	accum_cnt_0	100162	1			T1	467		T2	31		T3	43
class_index[0x2]	accum_cnt_2000	18953	1			T6	51		T14	96		T49	490
class_index[0x2]	accum_cnt_1000	44502	1			T1	172		T4	444		T6	864
class_index[0x2]	accum_cnt_100	6242	1			T1	49		T4	315		T56	15
class_index[0x2]	accum_cnt_50	16577	1			T1	51		T4	104		T7	8
class_index[0x2]	accum_cnt_10	41392	1			T1	28		T4	436		T7	10
class_index[0x2]	accum_cnt_0	105165	1			T1	169		T2	31		T3	43
class_index[0x3]	accum_cnt_2000	23327	1			T6	161		T5	287		T38	192
class_index[0x3]	accum_cnt_1000	55348	1			T1	27		T4	160		T15	2
class_index[0x3]	accum_cnt_100	6044	1			T1	26		T4	121		T15	22
class_index[0x3]	accum_cnt_50	10966	1			T1	28		T4	117		T7	11
class_index[0x3]	accum_cnt_10	51549	1			T1	25		T4	1116		T7	4
class_index[0x3]	accum_cnt_0	85943	1			T1	363		T2	31		T3	43