Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	8187	1			T14	4634		T49	3		T53	31
alert[0x1]	2973	1			T56	12		T35	1		T14	9
alert[0x2]	7165	1			T4	19		T45	5		T17	2
alert[0x3]	3920	1			T3	1		T5	9		T11	956
alert[0x4]	15867	1			T1	6		T4	11		T11	189
alert[0x5]	5802	1			T4	133		T5	1		T47	1
alert[0x6]	7275	1			T4	6		T56	2		T6	9
alert[0x7]	3413	1			T41	603		T297	3		T66	8
alert[0x8]	12019	1			T5	951		T11	204		T14	564
alert[0x9]	3193	1			T4	156		T11	66		T14	740
alert[0xa]	6571	1			T1	1		T3	1		T4	58
alert[0xb]	3088	1			T11	3		T35	1		T14	7
alert[0xc]	12058	1			T3	2		T4	42		T5	41
alert[0xd]	4648	1			T3	1		T56	3		T11	135
alert[0xe]	2990	1			T1	3		T3	1		T56	1
alert[0xf]	6038	1			T4	43		T11	184		T14	15
alert[0x10]	2804	1			T3	2		T5	53		T35	1
alert[0x11]	6626	1			T5	36		T11	15		T45	436
alert[0x12]	3857	1			T4	25		T56	18		T5	237
alert[0x13]	3832	1			T4	2		T56	2		T75	1
alert[0x14]	9544	1			T37	1		T11	15		T75	1
alert[0x15]	5000	1			T5	129		T11	28		T36	1
alert[0x16]	4171	1			T3	1		T5	270		T75	9
alert[0x17]	4080	1			T4	35		T11	50		T36	1
alert[0x18]	2930	1			T1	5		T4	7		T6	7
alert[0x19]	4091	1			T3	1		T4	1		T5	20
alert[0x1a]	13740	1			T4	282		T35	1		T27	325
alert[0x1b]	5993	1			T45	211		T17	3		T63	28
alert[0x1c]	5228	1			T3	1		T5	96		T11	13
alert[0x1d]	6170	1			T4	225		T5	394		T14	100
alert[0x1e]	2426	1			T1	2		T49	1		T45	39
alert[0x1f]	4122	1			T1	1		T4	48		T56	29
alert[0x20]	5271	1			T3	1		T51	1		T36	1
alert[0x21]	4271	1			T51	1		T45	85		T27	151
alert[0x22]	9517	1			T5	71		T11	4		T83	1
alert[0x23]	12293	1			T3	1		T4	1		T11	7
alert[0x24]	3039	1			T5	1		T35	1		T45	80
alert[0x25]	9066	1			T4	58		T5	13		T41	41
alert[0x26]	8185	1			T45	24		T27	7		T41	5
alert[0x27]	4201	1			T3	1		T11	102		T17	1
alert[0x28]	2650	1			T4	77		T11	136		T75	2
alert[0x29]	3773	1			T4	47		T5	91		T14	16
alert[0x2a]	3354	1			T45	50		T27	222		T17	4
alert[0x2b]	2900	1			T75	7		T242	1		T27	304
alert[0x2c]	3595	1			T11	240		T47	1		T87	2
alert[0x2d]	2849	1			T56	1		T11	10		T27	17
alert[0x2e]	12505	1			T11	1307		T27	6		T87	5
alert[0x2f]	9319	1			T3	1		T4	7		T6	17
alert[0x30]	4886	1			T3	1		T4	23		T11	222
alert[0x31]	6091	1			T1	1		T4	2		T5	97
alert[0x32]	7831	1			T3	1		T5	4		T11	3884
alert[0x33]	3871	1			T36	1		T45	230		T27	5
alert[0x34]	4741	1			T1	1		T242	1		T27	1416
alert[0x35]	5945	1			T1	3		T56	1		T11	7
alert[0x36]	13535	1			T1	9		T3	1		T75	7
alert[0x37]	10665	1			T1	3		T5	164		T44	5
alert[0x38]	4820	1			T56	10		T27	82		T41	10
alert[0x39]	10780	1			T14	10		T75	12		T45	145
alert[0x3a]	4643	1			T35	1		T36	1		T49	2
alert[0x3b]	6808	1			T5	219		T27	630		T53	25
alert[0x3c]	4022	1			T1	1		T3	1		T5	171
alert[0x3d]	6425	1			T4	81		T6	2		T5	1
alert[0x3e]	4097	1			T35	1		T14	99		T36	1
alert[0x3f]	4521	1			T56	2		T6	4		T11	55
alert[0x40]	2980	1			T1	10		T4	2		T45	33

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	76776	1			T3	2		T4	917		T56	1
class_i[0x1]	83826	1			T1	46		T3	1		T4	446
class_i[0x2]	150866	1			T3	4		T56	78		T37	1
class_i[0x3]	81802	1			T3	12		T4	28		T5	3930

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

392585

1

T1

46

T4

1391

T56

81

alert_ping_fail

685

1

T3

19

T37

1

T51

3

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	8183	1			T14	4634		T49	3		T53	31
alert_integrity_fail	alert[0x1]	2957	1			T56	12		T14	9		T83	4
alert_integrity_fail	alert[0x2]	7155	1			T4	19		T45	5		T17	2
alert_integrity_fail	alert[0x3]	3908	1			T5	9		T11	956		T27	9
alert_integrity_fail	alert[0x4]	15858	1			T1	6		T4	11		T11	189
alert_integrity_fail	alert[0x5]	5791	1			T4	133		T5	1		T27	28
alert_integrity_fail	alert[0x6]	7262	1			T4	6		T56	2		T6	9
alert_integrity_fail	alert[0x7]	3404	1			T41	603		T297	3		T66	8
alert_integrity_fail	alert[0x8]	12011	1			T5	951		T11	204		T14	564
alert_integrity_fail	alert[0x9]	3184	1			T4	156		T11	66		T14	740
alert_integrity_fail	alert[0xa]	6556	1			T1	1		T4	58		T5	162
alert_integrity_fail	alert[0xb]	3079	1			T11	3		T14	7		T82	1
alert_integrity_fail	alert[0xc]	12046	1			T4	42		T5	41		T14	8
alert_integrity_fail	alert[0xd]	4637	1			T56	3		T11	135		T45	518
alert_integrity_fail	alert[0xe]	2980	1			T1	3		T56	1		T11	49
alert_integrity_fail	alert[0xf]	6033	1			T4	43		T11	184		T14	15
alert_integrity_fail	alert[0x10]	2784	1			T5	53		T27	77		T63	41
alert_integrity_fail	alert[0x11]	6620	1			T5	36		T11	15		T45	436
alert_integrity_fail	alert[0x12]	3844	1			T4	25		T56	18		T5	237
alert_integrity_fail	alert[0x13]	3823	1			T4	2		T56	2		T75	1
alert_integrity_fail	alert[0x14]	9535	1			T11	15		T75	1		T45	77
alert_integrity_fail	alert[0x15]	4990	1			T5	129		T11	28		T41	160
alert_integrity_fail	alert[0x16]	4162	1			T5	270		T75	9		T45	19
alert_integrity_fail	alert[0x17]	4074	1			T4	35		T11	50		T27	40
alert_integrity_fail	alert[0x18]	2915	1			T1	5		T4	7		T6	7
alert_integrity_fail	alert[0x19]	4079	1			T4	1		T5	20		T14	29
alert_integrity_fail	alert[0x1a]	13731	1			T4	282		T27	325		T64	1997
alert_integrity_fail	alert[0x1b]	5978	1			T45	211		T17	3		T63	28
alert_integrity_fail	alert[0x1c]	5216	1			T5	96		T11	13		T14	19
alert_integrity_fail	alert[0x1d]	6163	1			T4	225		T5	394		T14	100
alert_integrity_fail	alert[0x1e]	2418	1			T1	2		T49	1		T45	39
alert_integrity_fail	alert[0x1f]	4112	1			T1	1		T4	48		T56	29
alert_integrity_fail	alert[0x20]	5257	1			T27	25		T41	85		T53	33
alert_integrity_fail	alert[0x21]	4260	1			T45	85		T27	151		T63	53
alert_integrity_fail	alert[0x22]	9501	1			T5	71		T11	4		T83	1
alert_integrity_fail	alert[0x23]	12283	1			T4	1		T11	7		T45	2259
alert_integrity_fail	alert[0x24]	3027	1			T5	1		T45	80		T63	233
alert_integrity_fail	alert[0x25]	9059	1			T4	58		T5	13		T41	41
alert_integrity_fail	alert[0x26]	8176	1			T45	24		T27	7		T41	5
alert_integrity_fail	alert[0x27]	4190	1			T11	102		T17	1		T53	12
alert_integrity_fail	alert[0x28]	2634	1			T4	77		T11	136		T75	2
alert_integrity_fail	alert[0x29]	3762	1			T4	47		T5	91		T14	16
alert_integrity_fail	alert[0x2a]	3346	1			T45	50		T27	222		T17	4
alert_integrity_fail	alert[0x2b]	2891	1			T75	7		T27	304		T17	1
alert_integrity_fail	alert[0x2c]	3575	1			T11	240		T87	2		T298	1
alert_integrity_fail	alert[0x2d]	2835	1			T56	1		T11	10		T27	17
alert_integrity_fail	alert[0x2e]	12490	1			T11	1307		T27	6		T87	5
alert_integrity_fail	alert[0x2f]	9310	1			T4	7		T6	17		T75	4
alert_integrity_fail	alert[0x30]	4876	1			T4	23		T11	222		T14	16
alert_integrity_fail	alert[0x31]	6083	1			T1	1		T4	2		T5	97
alert_integrity_fail	alert[0x32]	7819	1			T5	4		T11	3884		T27	19
alert_integrity_fail	alert[0x33]	3857	1			T45	230		T27	5		T41	48
alert_integrity_fail	alert[0x34]	4728	1			T1	1		T27	1416		T87	2
alert_integrity_fail	alert[0x35]	5934	1			T1	3		T56	1		T11	7
alert_integrity_fail	alert[0x36]	13525	1			T1	9		T75	7		T83	2
alert_integrity_fail	alert[0x37]	10655	1			T1	3		T5	164		T44	5
alert_integrity_fail	alert[0x38]	4811	1			T56	10		T27	82		T41	10
alert_integrity_fail	alert[0x39]	10775	1			T14	10		T75	12		T45	145
alert_integrity_fail	alert[0x3a]	4632	1			T49	2		T41	36		T16	185
alert_integrity_fail	alert[0x3b]	6800	1			T5	219		T27	630		T53	25
alert_integrity_fail	alert[0x3c]	4015	1			T1	1		T5	171		T63	22
alert_integrity_fail	alert[0x3d]	6416	1			T4	81		T6	2		T5	1
alert_integrity_fail	alert[0x3e]	4084	1			T14	99		T27	53		T53	7
alert_integrity_fail	alert[0x3f]	4519	1			T56	2		T6	4		T11	55
alert_integrity_fail	alert[0x40]	2972	1			T1	10		T4	2		T45	33
alert_ping_fail	alert[0x0]	4	1			T299	1		T300	1		T301	1
alert_ping_fail	alert[0x1]	16	1			T35	1		T36	1		T302	1
alert_ping_fail	alert[0x2]	10	1			T303	1		T304	1		T305	1
alert_ping_fail	alert[0x3]	12	1			T3	1		T306	1		T277	1
alert_ping_fail	alert[0x4]	9	1			T36	2		T307	1		T300	1
alert_ping_fail	alert[0x5]	11	1			T47	1		T308	1		T306	1
alert_ping_fail	alert[0x6]	13	1			T35	1		T36	1		T303	1
alert_ping_fail	alert[0x7]	9	1			T309	2		T310	1		T311	1
alert_ping_fail	alert[0x8]	8	1			T312	2		T313	1		T314	1
alert_ping_fail	alert[0x9]	9	1			T315	1		T316	1		T300	1
alert_ping_fail	alert[0xa]	15	1			T3	1		T35	1		T296	1
alert_ping_fail	alert[0xb]	9	1			T35	1		T242	1		T317	1
alert_ping_fail	alert[0xc]	12	1			T3	2		T36	1		T302	1
alert_ping_fail	alert[0xd]	11	1			T3	1		T302	2		T310	1
alert_ping_fail	alert[0xe]	10	1			T3	1		T299	1		T316	1
alert_ping_fail	alert[0xf]	5	1			T36	1		T299	1		T318	1
alert_ping_fail	alert[0x10]	20	1			T3	2		T35	1		T36	1
alert_ping_fail	alert[0x11]	6	1			T302	1		T299	1		T228	1
alert_ping_fail	alert[0x12]	13	1			T302	1		T306	1		T310	1
alert_ping_fail	alert[0x13]	9	1			T319	1		T304	1		T109	1
alert_ping_fail	alert[0x14]	9	1			T37	1		T316	1		T309	1
alert_ping_fail	alert[0x15]	10	1			T36	1		T302	1		T306	1
alert_ping_fail	alert[0x16]	9	1			T3	1		T48	1		T237	2
alert_ping_fail	alert[0x17]	6	1			T36	1		T320	2		T321	1
alert_ping_fail	alert[0x18]	15	1			T35	1		T36	1		T302	1
alert_ping_fail	alert[0x19]	12	1			T3	1		T302	1		T319	1
alert_ping_fail	alert[0x1a]	9	1			T35	1		T302	1		T322	1
alert_ping_fail	alert[0x1b]	15	1			T302	2		T319	1		T316	1
alert_ping_fail	alert[0x1c]	12	1			T3	1		T51	1		T306	1
alert_ping_fail	alert[0x1d]	7	1			T322	1		T228	2		T323	1
alert_ping_fail	alert[0x1e]	8	1			T302	2		T322	1		T276	1
alert_ping_fail	alert[0x1f]	10	1			T35	1		T302	1		T229	1
alert_ping_fail	alert[0x20]	14	1			T3	1		T51	1		T36	1
alert_ping_fail	alert[0x21]	11	1			T51	1		T324	1		T315	1
alert_ping_fail	alert[0x22]	16	1			T242	1		T299	1		T316	1
alert_ping_fail	alert[0x23]	10	1			T3	1		T325	1		T315	1
alert_ping_fail	alert[0x24]	12	1			T35	1		T242	1		T302	1
alert_ping_fail	alert[0x25]	7	1			T305	1		T326	2		T327	1
alert_ping_fail	alert[0x26]	9	1			T328	1		T322	1		T329	1
alert_ping_fail	alert[0x27]	11	1			T3	1		T302	1		T317	2
alert_ping_fail	alert[0x28]	16	1			T36	1		T317	1		T328	1
alert_ping_fail	alert[0x29]	11	1			T36	2		T306	1		T324	1
alert_ping_fail	alert[0x2a]	8	1			T306	1		T317	1		T300	1
alert_ping_fail	alert[0x2b]	9	1			T242	1		T319	1		T299	1
alert_ping_fail	alert[0x2c]	20	1			T47	1		T302	1		T330	1
alert_ping_fail	alert[0x2d]	14	1			T319	1		T306	1		T315	1
alert_ping_fail	alert[0x2e]	15	1			T315	1		T316	1		T312	3
alert_ping_fail	alert[0x2f]	9	1			T3	1		T306	1		T312	1
alert_ping_fail	alert[0x30]	10	1			T3	1		T310	1		T307	1
alert_ping_fail	alert[0x31]	8	1			T277	1		T329	1		T304	1
alert_ping_fail	alert[0x32]	12	1			T3	1		T303	1		T324	1
alert_ping_fail	alert[0x33]	14	1			T36	1		T306	1		T316	1
alert_ping_fail	alert[0x34]	13	1			T242	1		T302	1		T306	2
alert_ping_fail	alert[0x35]	11	1			T35	1		T36	1		T242	1
alert_ping_fail	alert[0x36]	10	1			T3	1		T325	1		T310	1
alert_ping_fail	alert[0x37]	10	1			T316	1		T322	1		T277	1
alert_ping_fail	alert[0x38]	9	1			T306	1		T325	1		T229	1
alert_ping_fail	alert[0x39]	5	1			T307	1		T300	1		T311	1
alert_ping_fail	alert[0x3a]	11	1			T35	1		T36	1		T328	1
alert_ping_fail	alert[0x3b]	8	1			T303	1		T277	1		T229	1
alert_ping_fail	alert[0x3c]	7	1			T3	1		T325	1		T299	1
alert_ping_fail	alert[0x3d]	9	1			T35	1		T36	1		T306	1
alert_ping_fail	alert[0x3e]	13	1			T35	1		T36	1		T302	2
alert_ping_fail	alert[0x3f]	2	1			T307	1		T331	1		-	-
alert_ping_fail	alert[0x40]	8	1			T306	1		T315	1		T314	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	76630	1			T4	917		T56	1		T6	35
alert_integrity_fail	class_i[0x1]	83650	1			T1	46		T4	446		T56	2
alert_integrity_fail	class_i[0x2]	150703	1			T56	78		T5	190		T11	55
alert_integrity_fail	class_i[0x3]	81602	1			T4	28		T5	3930		T82	2
alert_ping_fail	class_i[0x0]	146	1			T3	2		T36	1		T242	1
alert_ping_fail	class_i[0x1]	176	1			T3	1		T35	13		T36	2
alert_ping_fail	class_i[0x2]	163	1			T3	4		T37	1		T51	3
alert_ping_fail	class_i[0x3]	200	1			T3	12		T36	16		T302	22