Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.64 99.86 98.50 89.82 91.94 99.81 97.13 99.44


Total test records in report: 823
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T769 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.51885436 Apr 28 01:21:21 PM PDT 24 Apr 28 01:21:23 PM PDT 24 24201626 ps
T770 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.893625051 Apr 28 01:22:09 PM PDT 24 Apr 28 01:22:11 PM PDT 24 7290827 ps
T771 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.1138225974 Apr 28 01:20:54 PM PDT 24 Apr 28 01:20:57 PM PDT 24 31071886 ps
T772 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.2958166739 Apr 28 01:21:39 PM PDT 24 Apr 28 01:21:43 PM PDT 24 64645906 ps
T153 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3527634666 Apr 28 01:21:38 PM PDT 24 Apr 28 01:29:20 PM PDT 24 14566281770 ps
T171 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.790235857 Apr 28 01:20:59 PM PDT 24 Apr 28 01:22:04 PM PDT 24 3545785233 ps
T773 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.121400867 Apr 28 01:20:58 PM PDT 24 Apr 28 01:21:03 PM PDT 24 93763858 ps
T774 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3577115579 Apr 28 01:22:12 PM PDT 24 Apr 28 01:22:13 PM PDT 24 7795457 ps
T158 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.751128429 Apr 28 01:22:02 PM PDT 24 Apr 28 01:25:05 PM PDT 24 6617607395 ps
T154 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3631053681 Apr 28 01:21:18 PM PDT 24 Apr 28 01:23:22 PM PDT 24 1537871414 ps
T775 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.4007527062 Apr 28 01:21:20 PM PDT 24 Apr 28 01:21:23 PM PDT 24 23867724 ps
T776 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.106433002 Apr 28 01:21:48 PM PDT 24 Apr 28 01:21:56 PM PDT 24 414955937 ps
T777 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1002595916 Apr 28 01:22:03 PM PDT 24 Apr 28 01:22:05 PM PDT 24 7254930 ps
T778 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.2835427977 Apr 28 01:20:57 PM PDT 24 Apr 28 01:21:06 PM PDT 24 299157177 ps
T779 /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2954758430 Apr 28 01:21:29 PM PDT 24 Apr 28 01:21:34 PM PDT 24 178231103 ps
T780 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2521877526 Apr 28 01:21:34 PM PDT 24 Apr 28 01:21:35 PM PDT 24 15995498 ps
T179 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1812772035 Apr 28 01:22:02 PM PDT 24 Apr 28 01:22:05 PM PDT 24 34988090 ps
T149 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.266041635 Apr 28 01:21:48 PM PDT 24 Apr 28 01:32:07 PM PDT 24 4629128195 ps
T159 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1297859558 Apr 28 01:21:39 PM PDT 24 Apr 28 01:33:37 PM PDT 24 86490064328 ps
T781 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1527082365 Apr 28 01:21:45 PM PDT 24 Apr 28 01:21:51 PM PDT 24 659071052 ps
T782 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.333658715 Apr 28 01:21:02 PM PDT 24 Apr 28 01:24:05 PM PDT 24 6805937131 ps
T783 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2915550861 Apr 28 01:20:49 PM PDT 24 Apr 28 01:21:00 PM PDT 24 758008133 ps
T784 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.2818447819 Apr 28 01:21:30 PM PDT 24 Apr 28 01:21:41 PM PDT 24 389281179 ps
T155 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2825532560 Apr 28 01:21:52 PM PDT 24 Apr 28 01:26:53 PM PDT 24 16734431587 ps
T785 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.3961012881 Apr 28 01:22:15 PM PDT 24 Apr 28 01:22:17 PM PDT 24 7604947 ps
T786 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2295741658 Apr 28 01:21:48 PM PDT 24 Apr 28 01:21:53 PM PDT 24 110175521 ps
T787 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1300781095 Apr 28 01:21:31 PM PDT 24 Apr 28 01:21:40 PM PDT 24 903652096 ps
T170 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.4031765796 Apr 28 01:20:45 PM PDT 24 Apr 28 01:20:49 PM PDT 24 100579721 ps
T788 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.3044012966 Apr 28 01:21:24 PM PDT 24 Apr 28 01:21:42 PM PDT 24 927340348 ps
T157 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.135997997 Apr 28 01:21:00 PM PDT 24 Apr 28 01:23:30 PM PDT 24 3284486581 ps
T789 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.3702741799 Apr 28 01:21:24 PM PDT 24 Apr 28 01:24:29 PM PDT 24 1653025498 ps
T790 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.399916495 Apr 28 01:22:03 PM PDT 24 Apr 28 01:22:14 PM PDT 24 97839468 ps
T184 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2334552918 Apr 28 01:21:47 PM PDT 24 Apr 28 01:21:50 PM PDT 24 63272248 ps
T362 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1678042953 Apr 28 01:21:15 PM PDT 24 Apr 28 01:30:43 PM PDT 24 27096839892 ps
T791 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3984866361 Apr 28 01:21:44 PM PDT 24 Apr 28 01:28:54 PM PDT 24 6881428416 ps
T792 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.2400867302 Apr 28 01:21:00 PM PDT 24 Apr 28 01:21:43 PM PDT 24 2856712300 ps
T793 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.195508483 Apr 28 01:21:22 PM PDT 24 Apr 28 01:21:24 PM PDT 24 7497661 ps
T794 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1849669570 Apr 28 01:22:06 PM PDT 24 Apr 28 01:22:08 PM PDT 24 8598418 ps
T160 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2110015020 Apr 28 01:21:00 PM PDT 24 Apr 28 01:28:07 PM PDT 24 28550101988 ps
T795 /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.3866859509 Apr 28 01:22:13 PM PDT 24 Apr 28 01:22:15 PM PDT 24 15507783 ps
T156 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3321577832 Apr 28 01:21:30 PM PDT 24 Apr 28 01:26:16 PM PDT 24 18080980341 ps
T796 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3054726618 Apr 28 01:21:45 PM PDT 24 Apr 28 01:21:46 PM PDT 24 15176150 ps
T797 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3364904918 Apr 28 01:21:58 PM PDT 24 Apr 28 01:22:03 PM PDT 24 54402230 ps
T798 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.2515177894 Apr 28 01:21:26 PM PDT 24 Apr 28 01:21:32 PM PDT 24 33812506 ps
T799 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3647476421 Apr 28 01:21:58 PM PDT 24 Apr 28 01:22:04 PM PDT 24 65798430 ps
T800 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3110846831 Apr 28 01:21:18 PM PDT 24 Apr 28 01:21:33 PM PDT 24 1503915380 ps
T801 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.2058109107 Apr 28 01:22:15 PM PDT 24 Apr 28 01:22:17 PM PDT 24 31212843 ps
T802 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.2341819162 Apr 28 01:21:32 PM PDT 24 Apr 28 01:21:39 PM PDT 24 87346085 ps
T803 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2545955364 Apr 28 01:21:38 PM PDT 24 Apr 28 01:21:41 PM PDT 24 14290844 ps
T804 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.103909747 Apr 28 01:21:55 PM PDT 24 Apr 28 01:21:57 PM PDT 24 6496613 ps
T163 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.1966373673 Apr 28 01:22:03 PM PDT 24 Apr 28 01:31:39 PM PDT 24 4623540941 ps
T805 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3249168849 Apr 28 01:22:13 PM PDT 24 Apr 28 01:22:15 PM PDT 24 11258447 ps
T162 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3770221207 Apr 28 01:21:36 PM PDT 24 Apr 28 01:38:51 PM PDT 24 17463384126 ps
T182 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.627376871 Apr 28 01:22:00 PM PDT 24 Apr 28 01:23:20 PM PDT 24 5389533575 ps
T806 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.2020379068 Apr 28 01:21:48 PM PDT 24 Apr 28 01:21:55 PM PDT 24 94189028 ps
T807 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1349418985 Apr 28 01:21:44 PM PDT 24 Apr 28 01:21:56 PM PDT 24 309416429 ps
T808 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.2496581170 Apr 28 01:21:50 PM PDT 24 Apr 28 01:21:55 PM PDT 24 49814950 ps
T809 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.701718266 Apr 28 01:21:11 PM PDT 24 Apr 28 01:21:13 PM PDT 24 7454094 ps
T810 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.4279899165 Apr 28 01:22:08 PM PDT 24 Apr 28 01:22:10 PM PDT 24 10249961 ps
T161 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3251939935 Apr 28 01:20:54 PM PDT 24 Apr 28 01:23:08 PM PDT 24 10238409374 ps
T811 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1384194857 Apr 28 01:21:24 PM PDT 24 Apr 28 01:21:26 PM PDT 24 14768233 ps
T812 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.3070575361 Apr 28 01:21:18 PM PDT 24 Apr 28 01:21:29 PM PDT 24 620209245 ps
T813 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3577486377 Apr 28 01:21:48 PM PDT 24 Apr 28 01:22:05 PM PDT 24 4172660251 ps
T814 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.3100031107 Apr 28 01:21:40 PM PDT 24 Apr 28 01:21:44 PM PDT 24 66710089 ps
T815 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.4051057700 Apr 28 01:22:05 PM PDT 24 Apr 28 01:22:10 PM PDT 24 38604777 ps
T816 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1319371648 Apr 28 01:21:53 PM PDT 24 Apr 28 01:21:55 PM PDT 24 16439089 ps
T817 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.1981184733 Apr 28 01:22:09 PM PDT 24 Apr 28 01:22:11 PM PDT 24 9346822 ps
T818 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3836492976 Apr 28 01:20:46 PM PDT 24 Apr 28 01:21:05 PM PDT 24 305611261 ps
T819 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2708887082 Apr 28 01:21:37 PM PDT 24 Apr 28 01:22:11 PM PDT 24 7108791541 ps
T820 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.3458452121 Apr 28 01:20:55 PM PDT 24 Apr 28 01:20:59 PM PDT 24 158907707 ps
T821 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.2908510271 Apr 28 01:21:21 PM PDT 24 Apr 28 01:21:23 PM PDT 24 11355596 ps
T822 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.1498524439 Apr 28 01:21:34 PM PDT 24 Apr 28 01:21:46 PM PDT 24 163416226 ps
T823 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2919921971 Apr 28 01:21:02 PM PDT 24 Apr 28 01:21:06 PM PDT 24 21949254 ps

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.3080237931
Short name T4
Test name
Test status
Simulation time 79431245956 ps
CPU time 5155.98 seconds
Started Apr 28 04:19:29 PM PDT 24
Finished Apr 28 05:45:26 PM PDT 24
Peak memory 321920 kb
Host smart-66fac06c-b789-4e07-8782-df638f78a01f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080237931 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.3080237931
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.3060195624
Short name T11
Test name
Test status
Simulation time 233751425232 ps
CPU time 2532.15 seconds
Started Apr 28 04:18:55 PM PDT 24
Finished Apr 28 05:01:08 PM PDT 24
Peak memory 285604 kb
Host smart-e388d011-4aa5-4c49-8a18-e1f46de33a31
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060195624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.3060195624
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.1103938005
Short name T193
Test name
Test status
Simulation time 194864606 ps
CPU time 5.13 seconds
Started Apr 28 01:21:21 PM PDT 24
Finished Apr 28 01:21:26 PM PDT 24
Peak memory 237080 kb
Host smart-3f5ec9fa-bd47-4019-91d1-e6221cfa19bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1103938005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.1103938005
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.1289732111
Short name T16
Test name
Test status
Simulation time 170050214905 ps
CPU time 2655.73 seconds
Started Apr 28 04:21:45 PM PDT 24
Finished Apr 28 05:06:02 PM PDT 24
Peak memory 305384 kb
Host smart-33ab4684-4f8b-432e-869e-b3eff04a3f40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289732111 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.1289732111
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3225943365
Short name T132
Test name
Test status
Simulation time 5196061339 ps
CPU time 771.45 seconds
Started Apr 28 01:21:25 PM PDT 24
Finished Apr 28 01:34:16 PM PDT 24
Peak memory 265504 kb
Host smart-7edd00ef-1531-49cd-8d2a-a4e078656860
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225943365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.3225943365
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.242226918
Short name T99
Test name
Test status
Simulation time 31755223545 ps
CPU time 1678.75 seconds
Started Apr 28 04:17:46 PM PDT 24
Finished Apr 28 04:45:46 PM PDT 24
Peak memory 289124 kb
Host smart-7f633c35-f34d-411f-8c58-966925035b34
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242226918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_han
dler_stress_all.242226918
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.1328242144
Short name T27
Test name
Test status
Simulation time 111816878217 ps
CPU time 3023.23 seconds
Started Apr 28 04:17:28 PM PDT 24
Finished Apr 28 05:07:52 PM PDT 24
Peak memory 288840 kb
Host smart-ce219318-0c08-4301-832a-ff51a1265493
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328242144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.1328242144
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.430289517
Short name T102
Test name
Test status
Simulation time 6002683800 ps
CPU time 818.94 seconds
Started Apr 28 04:17:09 PM PDT 24
Finished Apr 28 04:30:48 PM PDT 24
Peak memory 273316 kb
Host smart-a9cfb7e8-77bc-48f5-bf67-25ebb159cb01
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430289517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.430289517
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.3021306562
Short name T37
Test name
Test status
Simulation time 205489917300 ps
CPU time 2887.7 seconds
Started Apr 28 04:08:24 PM PDT 24
Finished Apr 28 04:56:32 PM PDT 24
Peak memory 282580 kb
Host smart-e9005125-35cf-4aec-8924-c2702cd31cbd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021306562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.3021306562
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.387870461
Short name T131
Test name
Test status
Simulation time 18209405365 ps
CPU time 297.13 seconds
Started Apr 28 01:21:26 PM PDT 24
Finished Apr 28 01:26:23 PM PDT 24
Peak memory 265644 kb
Host smart-1ed12ded-7de9-4323-8b80-b2a99517fb13
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=387870461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_error
s.387870461
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2056851569
Short name T133
Test name
Test status
Simulation time 28549919003 ps
CPU time 1012.8 seconds
Started Apr 28 01:21:39 PM PDT 24
Finished Apr 28 01:38:33 PM PDT 24
Peak memory 273092 kb
Host smart-4872e221-e322-48ad-9fc8-a5810f7a5f5c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056851569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.2056851569
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.4044768886
Short name T42
Test name
Test status
Simulation time 56717787418 ps
CPU time 1758.75 seconds
Started Apr 28 04:21:50 PM PDT 24
Finished Apr 28 04:51:09 PM PDT 24
Peak memory 268272 kb
Host smart-e9ecd953-ee55-4cbb-9790-39dab80ead55
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044768886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.4044768886
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.1827677787
Short name T109
Test name
Test status
Simulation time 12541762774 ps
CPU time 478.35 seconds
Started Apr 28 04:24:09 PM PDT 24
Finished Apr 28 04:32:07 PM PDT 24
Peak memory 248232 kb
Host smart-71261a3a-6f12-48c1-b472-0474c0085781
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827677787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.1827677787
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.3176736805
Short name T44
Test name
Test status
Simulation time 155095823311 ps
CPU time 3825.11 seconds
Started Apr 28 04:15:11 PM PDT 24
Finished Apr 28 05:18:57 PM PDT 24
Peak memory 298752 kb
Host smart-03c0a202-9969-449d-88ef-7655eb3b628b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176736805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.3176736805
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.3312961578
Short name T117
Test name
Test status
Simulation time 11460007353 ps
CPU time 1408.52 seconds
Started Apr 28 04:13:42 PM PDT 24
Finished Apr 28 04:37:11 PM PDT 24
Peak memory 282484 kb
Host smart-9242b829-a6ca-4d9c-a019-cbd891e55fd0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312961578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.3312961578
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1626114268
Short name T134
Test name
Test status
Simulation time 31683170328 ps
CPU time 294.19 seconds
Started Apr 28 01:22:00 PM PDT 24
Finished Apr 28 01:26:54 PM PDT 24
Peak memory 265692 kb
Host smart-0935c763-3adb-400b-9c6e-c4838a1e3b90
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1626114268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.1626114268
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.1169480678
Short name T60
Test name
Test status
Simulation time 2541866859 ps
CPU time 36.95 seconds
Started Apr 28 04:24:45 PM PDT 24
Finished Apr 28 04:25:22 PM PDT 24
Peak memory 256076 kb
Host smart-87f169bf-7a24-49d5-a331-d9255596f7b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11694
80678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.1169480678
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.2820926529
Short name T3
Test name
Test status
Simulation time 49902951311 ps
CPU time 444.45 seconds
Started Apr 28 04:22:28 PM PDT 24
Finished Apr 28 04:29:52 PM PDT 24
Peak memory 248128 kb
Host smart-716ed973-4153-451f-a61f-cd03c738b7bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820926529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2820926529
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3166152786
Short name T127
Test name
Test status
Simulation time 24989379030 ps
CPU time 955.54 seconds
Started Apr 28 01:21:21 PM PDT 24
Finished Apr 28 01:37:17 PM PDT 24
Peak memory 273820 kb
Host smart-7fe62e7b-bd40-4a38-b60e-7d1540630252
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166152786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.3166152786
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.4154168383
Short name T351
Test name
Test status
Simulation time 13376771 ps
CPU time 1.42 seconds
Started Apr 28 01:22:15 PM PDT 24
Finished Apr 28 01:22:17 PM PDT 24
Peak memory 237264 kb
Host smart-15659615-4b5b-41e5-9742-eb09274e9fac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4154168383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.4154168383
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.1130667099
Short name T323
Test name
Test status
Simulation time 38852939571 ps
CPU time 2227.26 seconds
Started Apr 28 04:23:11 PM PDT 24
Finished Apr 28 05:00:19 PM PDT 24
Peak memory 287888 kb
Host smart-995edbc6-7948-43bc-9f28-748657237e81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130667099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.1130667099
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.2225021977
Short name T126
Test name
Test status
Simulation time 3835947592 ps
CPU time 270.15 seconds
Started Apr 28 01:21:38 PM PDT 24
Finished Apr 28 01:26:10 PM PDT 24
Peak memory 265588 kb
Host smart-6b391f31-f49f-4ad6-b209-a3a1bc3355ce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2225021977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.2225021977
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3116057935
Short name T166
Test name
Test status
Simulation time 341557517 ps
CPU time 35.32 seconds
Started Apr 28 01:21:38 PM PDT 24
Finished Apr 28 01:22:15 PM PDT 24
Peak memory 248824 kb
Host smart-5e0f7639-ecac-440c-9733-ad0113e6ee4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3116057935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.3116057935
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1612851056
Short name T152
Test name
Test status
Simulation time 4317741825 ps
CPU time 608.75 seconds
Started Apr 28 01:21:54 PM PDT 24
Finished Apr 28 01:32:03 PM PDT 24
Peak memory 265572 kb
Host smart-a9a10645-4935-4467-88fe-9acd74a28b64
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612851056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.1612851056
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.2198033591
Short name T334
Test name
Test status
Simulation time 183495274829 ps
CPU time 2899.3 seconds
Started Apr 28 04:17:10 PM PDT 24
Finished Apr 28 05:05:29 PM PDT 24
Peak memory 288776 kb
Host smart-5fa92aec-4c4f-469c-86dd-d611ddb0763e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198033591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.2198033591
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.2915672516
Short name T93
Test name
Test status
Simulation time 52834201637 ps
CPU time 3212.69 seconds
Started Apr 28 04:20:18 PM PDT 24
Finished Apr 28 05:13:51 PM PDT 24
Peak memory 306020 kb
Host smart-6952ef02-1509-498c-b67a-f61292ccda5d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915672516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.2915672516
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.2523902933
Short name T301
Test name
Test status
Simulation time 56775900048 ps
CPU time 598.07 seconds
Started Apr 28 04:23:43 PM PDT 24
Finished Apr 28 04:33:41 PM PDT 24
Peak memory 248732 kb
Host smart-77638bd6-d43d-4eef-ad23-d30b9827a66e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523902933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.2523902933
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.2395294104
Short name T14
Test name
Test status
Simulation time 447974535507 ps
CPU time 9857.79 seconds
Started Apr 28 04:24:54 PM PDT 24
Finished Apr 28 07:09:13 PM PDT 24
Peak memory 388888 kb
Host smart-c461ede0-46ea-498a-be45-c03737073f28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395294104 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.2395294104
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.3464346850
Short name T555
Test name
Test status
Simulation time 135946357596 ps
CPU time 500.5 seconds
Started Apr 28 04:22:51 PM PDT 24
Finished Apr 28 04:31:12 PM PDT 24
Peak memory 248772 kb
Host smart-5ba05769-13be-4f18-be58-0bd70169cfe4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464346850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.3464346850
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2825532560
Short name T155
Test name
Test status
Simulation time 16734431587 ps
CPU time 300.29 seconds
Started Apr 28 01:21:52 PM PDT 24
Finished Apr 28 01:26:53 PM PDT 24
Peak memory 265520 kb
Host smart-5f6294b4-c035-4adf-b0bb-d5f4b6188067
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2825532560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.2825532560
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.3074779518
Short name T342
Test name
Test status
Simulation time 141403175163 ps
CPU time 2305.22 seconds
Started Apr 28 04:17:26 PM PDT 24
Finished Apr 28 04:55:52 PM PDT 24
Peak memory 272608 kb
Host smart-10fefbe6-07cd-41ef-90ca-fe044249cbc2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074779518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.3074779518
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.18558039
Short name T276
Test name
Test status
Simulation time 75587819297 ps
CPU time 2300.23 seconds
Started Apr 28 04:20:18 PM PDT 24
Finished Apr 28 04:58:39 PM PDT 24
Peak memory 272740 kb
Host smart-cf9715ec-985c-4ef4-9bb0-d080712d8149
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18558039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.18558039
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.1441976236
Short name T101
Test name
Test status
Simulation time 200383826252 ps
CPU time 4209.89 seconds
Started Apr 28 04:23:53 PM PDT 24
Finished Apr 28 05:34:03 PM PDT 24
Peak memory 322256 kb
Host smart-e42d0ed2-f500-4608-aec0-cc40d952582b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441976236 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.1441976236
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2716801167
Short name T148
Test name
Test status
Simulation time 4391061618 ps
CPU time 513.62 seconds
Started Apr 28 01:20:46 PM PDT 24
Finished Apr 28 01:29:20 PM PDT 24
Peak memory 273252 kb
Host smart-e1444972-08ed-4526-85e8-f5580b8556a7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716801167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.2716801167
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.3559801776
Short name T71
Test name
Test status
Simulation time 173925896063 ps
CPU time 4688.37 seconds
Started Apr 28 04:17:05 PM PDT 24
Finished Apr 28 05:35:14 PM PDT 24
Peak memory 338404 kb
Host smart-856a7b22-fbca-48d8-b962-194c1db5147d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559801776 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.3559801776
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.71210416
Short name T23
Test name
Test status
Simulation time 188057073018 ps
CPU time 2993.92 seconds
Started Apr 28 04:21:08 PM PDT 24
Finished Apr 28 05:11:02 PM PDT 24
Peak memory 300888 kb
Host smart-a7b8cbcc-2422-432b-a480-dc549a2a8d3d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71210416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_hand
ler_stress_all.71210416
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.277892538
Short name T128
Test name
Test status
Simulation time 9859232798 ps
CPU time 146.84 seconds
Started Apr 28 01:21:48 PM PDT 24
Finished Apr 28 01:24:15 PM PDT 24
Peak memory 265584 kb
Host smart-dd165d05-282d-4abb-812d-48cce546eadf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=277892538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_erro
rs.277892538
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.1136702667
Short name T353
Test name
Test status
Simulation time 12527574 ps
CPU time 1.31 seconds
Started Apr 28 01:21:00 PM PDT 24
Finished Apr 28 01:21:02 PM PDT 24
Peak memory 237164 kb
Host smart-23a0424d-4e89-4891-97bf-4163ddddb056
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1136702667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.1136702667
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.3335532885
Short name T307
Test name
Test status
Simulation time 8488780786 ps
CPU time 372.03 seconds
Started Apr 28 04:17:20 PM PDT 24
Finished Apr 28 04:23:33 PM PDT 24
Peak memory 248240 kb
Host smart-85b3361a-cbaa-47b6-b780-ab7cd348d170
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335532885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3335532885
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.1323303449
Short name T51
Test name
Test status
Simulation time 289647764086 ps
CPU time 2286.62 seconds
Started Apr 28 04:10:08 PM PDT 24
Finished Apr 28 04:48:16 PM PDT 24
Peak memory 272424 kb
Host smart-bf062eae-cd12-4937-83b4-cfb40cc5cc49
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323303449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.1323303449
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.1985216773
Short name T256
Test name
Test status
Simulation time 1231394433 ps
CPU time 31.42 seconds
Started Apr 28 04:22:22 PM PDT 24
Finished Apr 28 04:22:54 PM PDT 24
Peak memory 248664 kb
Host smart-100bca5f-4874-400b-aab0-eaf0bdb126f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19852
16773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.1985216773
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.2536646248
Short name T268
Test name
Test status
Simulation time 271081042 ps
CPU time 20.41 seconds
Started Apr 28 04:23:11 PM PDT 24
Finished Apr 28 04:23:32 PM PDT 24
Peak memory 248692 kb
Host smart-6f3490c1-cee3-4242-9b83-5c7d90f2e194
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25366
46248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.2536646248
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.4096400292
Short name T110
Test name
Test status
Simulation time 37615222293 ps
CPU time 2386.97 seconds
Started Apr 28 04:17:45 PM PDT 24
Finished Apr 28 04:57:33 PM PDT 24
Peak memory 305708 kb
Host smart-73e2bf1f-79d2-4c7c-8f17-c29dec4794b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096400292 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.4096400292
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.4140292277
Short name T146
Test name
Test status
Simulation time 3063592726 ps
CPU time 95.86 seconds
Started Apr 28 01:20:44 PM PDT 24
Finished Apr 28 01:22:21 PM PDT 24
Peak memory 257376 kb
Host smart-dfbac930-f708-4c95-8581-6cc60b318ea4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4140292277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.4140292277
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.2734579487
Short name T358
Test name
Test status
Simulation time 133917594 ps
CPU time 10.24 seconds
Started Apr 28 01:20:55 PM PDT 24
Finished Apr 28 01:21:05 PM PDT 24
Peak memory 251492 kb
Host smart-f7ca8952-2b12-41cb-9346-67da5376ef74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734579487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.2734579487
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.3534410709
Short name T703
Test name
Test status
Simulation time 36902067522 ps
CPU time 494.84 seconds
Started Apr 28 04:15:48 PM PDT 24
Finished Apr 28 04:24:03 PM PDT 24
Peak memory 247940 kb
Host smart-5a2645e7-62e4-481f-a54d-6edc3f89450d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534410709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3534410709
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.3891375022
Short name T47
Test name
Test status
Simulation time 53546466749 ps
CPU time 2899.27 seconds
Started Apr 28 04:18:53 PM PDT 24
Finished Apr 28 05:07:13 PM PDT 24
Peak memory 289016 kb
Host smart-fe20c742-30b8-42a6-9763-9bdb20004bac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891375022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.3891375022
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.1114270824
Short name T87
Test name
Test status
Simulation time 45935071223 ps
CPU time 517.83 seconds
Started Apr 28 04:22:27 PM PDT 24
Finished Apr 28 04:31:05 PM PDT 24
Peak memory 265180 kb
Host smart-1f3820d9-2cdc-4c11-b2d6-5e2f19877cfa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114270824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.1114270824
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3631053681
Short name T154
Test name
Test status
Simulation time 1537871414 ps
CPU time 123.41 seconds
Started Apr 28 01:21:18 PM PDT 24
Finished Apr 28 01:23:22 PM PDT 24
Peak memory 268272 kb
Host smart-58882e85-254f-46f3-ac54-a156ff9bf098
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3631053681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.3631053681
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.210396416
Short name T9
Test name
Test status
Simulation time 185924349309 ps
CPU time 2543.8 seconds
Started Apr 28 04:19:40 PM PDT 24
Finished Apr 28 05:02:05 PM PDT 24
Peak memory 285228 kb
Host smart-d814f0b9-df0b-46f3-b951-0e6685c250a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210396416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.210396416
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.4206478603
Short name T216
Test name
Test status
Simulation time 85725124 ps
CPU time 3.7 seconds
Started Apr 28 04:08:43 PM PDT 24
Finished Apr 28 04:08:48 PM PDT 24
Peak memory 248892 kb
Host smart-cdd2cb6a-44de-4e78-860a-c34014d3ed85
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4206478603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.4206478603
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.2451261924
Short name T217
Test name
Test status
Simulation time 140828008 ps
CPU time 3.48 seconds
Started Apr 28 04:09:28 PM PDT 24
Finished Apr 28 04:09:32 PM PDT 24
Peak memory 248892 kb
Host smart-ec0484d6-a7d1-48a9-92d3-9a57f61bca3b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2451261924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.2451261924
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.2806442731
Short name T214
Test name
Test status
Simulation time 63505507 ps
CPU time 2.87 seconds
Started Apr 28 04:16:06 PM PDT 24
Finished Apr 28 04:16:09 PM PDT 24
Peak memory 248896 kb
Host smart-42aaa985-b9ed-47ab-a49f-48f91d012af4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2806442731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.2806442731
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.97574261
Short name T207
Test name
Test status
Simulation time 37966358 ps
CPU time 3.71 seconds
Started Apr 28 04:15:14 PM PDT 24
Finished Apr 28 04:15:18 PM PDT 24
Peak memory 248896 kb
Host smart-002d1e5d-4c50-4528-a5d2-2b1c758cc350
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=97574261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.97574261
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.2321547407
Short name T169
Test name
Test status
Simulation time 10351181 ps
CPU time 1.21 seconds
Started Apr 28 01:21:42 PM PDT 24
Finished Apr 28 01:21:44 PM PDT 24
Peak memory 237248 kb
Host smart-42b19b84-2797-422d-889d-3a85425567aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2321547407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.2321547407
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.1180256019
Short name T340
Test name
Test status
Simulation time 35807342959 ps
CPU time 2263.29 seconds
Started Apr 28 04:09:15 PM PDT 24
Finished Apr 28 04:46:59 PM PDT 24
Peak memory 288636 kb
Host smart-38c2d495-d55b-4364-befc-1cacb1057805
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180256019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.1180256019
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.3458590518
Short name T263
Test name
Test status
Simulation time 86289313871 ps
CPU time 2548.38 seconds
Started Apr 28 04:16:27 PM PDT 24
Finished Apr 28 04:58:56 PM PDT 24
Peak memory 289560 kb
Host smart-08c2dba4-c818-4918-8832-45c0341ec7d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458590518 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.3458590518
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.4188224821
Short name T294
Test name
Test status
Simulation time 412841963 ps
CPU time 34.97 seconds
Started Apr 28 04:17:10 PM PDT 24
Finished Apr 28 04:17:46 PM PDT 24
Peak memory 248692 kb
Host smart-2e236d9e-8cc7-44cc-88c7-29d0806be40e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41882
24821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.4188224821
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.2394809179
Short name T260
Test name
Test status
Simulation time 178820301123 ps
CPU time 4221.05 seconds
Started Apr 28 04:18:54 PM PDT 24
Finished Apr 28 05:29:16 PM PDT 24
Peak memory 322156 kb
Host smart-e1e90c41-3ac3-4ec5-9507-3b248942539f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394809179 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.2394809179
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.3419327423
Short name T259
Test name
Test status
Simulation time 1167648719 ps
CPU time 49.98 seconds
Started Apr 28 04:19:15 PM PDT 24
Finished Apr 28 04:20:05 PM PDT 24
Peak memory 255788 kb
Host smart-04700d88-04eb-4d48-9231-b6861008b2d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34193
27423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.3419327423
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.2969348661
Short name T659
Test name
Test status
Simulation time 10875496710 ps
CPU time 458.18 seconds
Started Apr 28 04:21:04 PM PDT 24
Finished Apr 28 04:28:43 PM PDT 24
Peak memory 247948 kb
Host smart-70d8bfef-3f66-42c3-96de-99e885af856a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969348661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.2969348661
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.4027341822
Short name T176
Test name
Test status
Simulation time 113398668 ps
CPU time 4.16 seconds
Started Apr 28 01:21:20 PM PDT 24
Finished Apr 28 01:21:25 PM PDT 24
Peak memory 237140 kb
Host smart-8bc8fbd5-7348-405d-9c76-c3b62181d4f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4027341822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.4027341822
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.2392201224
Short name T34
Test name
Test status
Simulation time 108357330547 ps
CPU time 2129.71 seconds
Started Apr 28 04:16:42 PM PDT 24
Finished Apr 28 04:52:12 PM PDT 24
Peak memory 298004 kb
Host smart-e89c6ac3-53d3-4697-9739-d759630b46d6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392201224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.2392201224
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.106242607
Short name T20
Test name
Test status
Simulation time 39826376604 ps
CPU time 3916.17 seconds
Started Apr 28 04:21:37 PM PDT 24
Finished Apr 28 05:26:53 PM PDT 24
Peak memory 336900 kb
Host smart-90510ba0-2db3-4d91-aed4-796dec03e85a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106242607 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.106242607
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.3507469211
Short name T26
Test name
Test status
Simulation time 356832737786 ps
CPU time 5634.76 seconds
Started Apr 28 04:13:13 PM PDT 24
Finished Apr 28 05:47:09 PM PDT 24
Peak memory 321572 kb
Host smart-e8415c62-0ae8-4eff-bdfe-f1d9c0150417
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507469211 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.3507469211
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.266041635
Short name T149
Test name
Test status
Simulation time 4629128195 ps
CPU time 618.53 seconds
Started Apr 28 01:21:48 PM PDT 24
Finished Apr 28 01:32:07 PM PDT 24
Peak memory 265572 kb
Host smart-74ff2ad5-a74b-4ae5-aa09-6f96ae26105f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266041635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.266041635
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.2174016940
Short name T337
Test name
Test status
Simulation time 58708592617 ps
CPU time 3324.6 seconds
Started Apr 28 04:16:00 PM PDT 24
Finished Apr 28 05:11:25 PM PDT 24
Peak memory 288768 kb
Host smart-0a1132f9-f140-435c-9a4b-45f999e616f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174016940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.2174016940
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.1379550264
Short name T299
Test name
Test status
Simulation time 10630746297 ps
CPU time 435.62 seconds
Started Apr 28 04:17:10 PM PDT 24
Finished Apr 28 04:24:26 PM PDT 24
Peak memory 247920 kb
Host smart-5b02842f-ebf9-4404-98ca-3e8785212c95
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379550264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.1379550264
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.3388967170
Short name T280
Test name
Test status
Simulation time 78690772007 ps
CPU time 1595.13 seconds
Started Apr 28 04:17:11 PM PDT 24
Finished Apr 28 04:43:46 PM PDT 24
Peak memory 289716 kb
Host smart-a1341582-9be9-44c1-916b-002b03ce9875
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388967170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.3388967170
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.1524912886
Short name T246
Test name
Test status
Simulation time 74044645384 ps
CPU time 1260.53 seconds
Started Apr 28 04:17:10 PM PDT 24
Finished Apr 28 04:38:10 PM PDT 24
Peak memory 281696 kb
Host smart-41aad48a-f1bb-48e0-a0a6-b485cabf1c83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524912886 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.1524912886
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.2559241139
Short name T277
Test name
Test status
Simulation time 26651373459 ps
CPU time 184.01 seconds
Started Apr 28 04:18:06 PM PDT 24
Finished Apr 28 04:21:10 PM PDT 24
Peak memory 248120 kb
Host smart-653d7546-a3e1-4e5d-91f8-4c2687695d16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559241139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.2559241139
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.4098808453
Short name T258
Test name
Test status
Simulation time 751882193 ps
CPU time 28.07 seconds
Started Apr 28 04:18:03 PM PDT 24
Finished Apr 28 04:18:31 PM PDT 24
Peak memory 256904 kb
Host smart-18c9fe52-7d42-41a0-baac-69a94adf0dc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40988
08453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.4098808453
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.3753655820
Short name T278
Test name
Test status
Simulation time 2760669685 ps
CPU time 158.81 seconds
Started Apr 28 04:19:03 PM PDT 24
Finished Apr 28 04:21:42 PM PDT 24
Peak memory 256980 kb
Host smart-4ab7dd00-d612-47bf-980d-f836ebd0e0d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37536
55820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.3753655820
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.3169061996
Short name T185
Test name
Test status
Simulation time 169765751728 ps
CPU time 4062.48 seconds
Started Apr 28 04:20:00 PM PDT 24
Finished Apr 28 05:27:43 PM PDT 24
Peak memory 321552 kb
Host smart-857ef0b2-183e-4262-936d-79b6a702da03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169061996 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.3169061996
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.443610856
Short name T279
Test name
Test status
Simulation time 1223845753 ps
CPU time 21.93 seconds
Started Apr 28 04:10:55 PM PDT 24
Finished Apr 28 04:11:17 PM PDT 24
Peak memory 247356 kb
Host smart-69f29029-07e3-42ab-8dad-5affc76294ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44361
0856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.443610856
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.2620563334
Short name T94
Test name
Test status
Simulation time 149567019294 ps
CPU time 2395.28 seconds
Started Apr 28 04:21:34 PM PDT 24
Finished Apr 28 05:01:30 PM PDT 24
Peak memory 289248 kb
Host smart-53d8fe7f-8640-4408-8a5b-6fd33efe25d6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620563334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.2620563334
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.2161878054
Short name T261
Test name
Test status
Simulation time 4082757839 ps
CPU time 35.22 seconds
Started Apr 28 04:11:52 PM PDT 24
Finished Apr 28 04:12:27 PM PDT 24
Peak memory 248804 kb
Host smart-126178e3-922a-4411-945e-41b8db660d49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21618
78054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.2161878054
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.1085301681
Short name T292
Test name
Test status
Simulation time 117162087 ps
CPU time 13.17 seconds
Started Apr 28 04:22:53 PM PDT 24
Finished Apr 28 04:23:07 PM PDT 24
Peak memory 248696 kb
Host smart-a5bf8c7d-5f78-454f-8b8f-956748b54b13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10853
01681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.1085301681
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.3108181625
Short name T252
Test name
Test status
Simulation time 25349800108 ps
CPU time 778.73 seconds
Started Apr 28 04:24:24 PM PDT 24
Finished Apr 28 04:37:23 PM PDT 24
Peak memory 267988 kb
Host smart-bfad6162-675a-40e5-9f86-6ea3f724fc73
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108181625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.3108181625
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.1913789344
Short name T253
Test name
Test status
Simulation time 2245665496 ps
CPU time 38.94 seconds
Started Apr 28 04:15:26 PM PDT 24
Finished Apr 28 04:16:05 PM PDT 24
Peak memory 255648 kb
Host smart-c48231b9-3a4b-468a-9d37-3608654b23aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19137
89344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.1913789344
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3321577832
Short name T156
Test name
Test status
Simulation time 18080980341 ps
CPU time 285.57 seconds
Started Apr 28 01:21:30 PM PDT 24
Finished Apr 28 01:26:16 PM PDT 24
Peak memory 265664 kb
Host smart-b15ec995-682f-4762-80f1-6407c860fd8f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3321577832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.3321577832
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.790235857
Short name T171
Test name
Test status
Simulation time 3545785233 ps
CPU time 64.95 seconds
Started Apr 28 01:20:59 PM PDT 24
Finished Apr 28 01:22:04 PM PDT 24
Peak memory 238440 kb
Host smart-0670f3af-4279-4ad7-a36b-cb655fbb0706
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=790235857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.790235857
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.4031765796
Short name T170
Test name
Test status
Simulation time 100579721 ps
CPU time 2.78 seconds
Started Apr 28 01:20:45 PM PDT 24
Finished Apr 28 01:20:49 PM PDT 24
Peak memory 237348 kb
Host smart-943a6b65-dac1-4b01-b223-987f409a602d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4031765796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.4031765796
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3619770562
Short name T164
Test name
Test status
Simulation time 87400162 ps
CPU time 4.72 seconds
Started Apr 28 01:21:29 PM PDT 24
Finished Apr 28 01:21:34 PM PDT 24
Peak memory 237280 kb
Host smart-00146575-fc4b-4ab4-9c87-c4f3fcecfba0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3619770562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.3619770562
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.918772691
Short name T173
Test name
Test status
Simulation time 33450803 ps
CPU time 2.99 seconds
Started Apr 28 01:21:34 PM PDT 24
Finished Apr 28 01:21:38 PM PDT 24
Peak memory 237552 kb
Host smart-6881b9a8-6312-4c3e-a4c6-23fcad499f2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=918772691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.918772691
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.968648467
Short name T145
Test name
Test status
Simulation time 9357078193 ps
CPU time 269.6 seconds
Started Apr 28 01:20:59 PM PDT 24
Finished Apr 28 01:25:29 PM PDT 24
Peak memory 265664 kb
Host smart-f706de11-515c-4eb3-b043-f7a33c1ccfaf
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968648467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.968648467
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3246990408
Short name T177
Test name
Test status
Simulation time 484617119 ps
CPU time 31.63 seconds
Started Apr 28 01:21:39 PM PDT 24
Finished Apr 28 01:22:11 PM PDT 24
Peak memory 240748 kb
Host smart-53e68a57-250b-4cdf-af6a-649f44d2fdc6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3246990408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3246990408
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.504678320
Short name T165
Test name
Test status
Simulation time 58956380 ps
CPU time 3.76 seconds
Started Apr 28 01:21:43 PM PDT 24
Finished Apr 28 01:21:47 PM PDT 24
Peak memory 237092 kb
Host smart-c9572b58-d653-4619-85f4-8b6dae1b82a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=504678320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.504678320
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.3027794483
Short name T175
Test name
Test status
Simulation time 482406337 ps
CPU time 37.45 seconds
Started Apr 28 01:21:57 PM PDT 24
Finished Apr 28 01:22:35 PM PDT 24
Peak memory 239916 kb
Host smart-44917b72-d16d-41b5-95cc-9376172b8cd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3027794483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.3027794483
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.265332979
Short name T174
Test name
Test status
Simulation time 261780349 ps
CPU time 2.77 seconds
Started Apr 28 01:21:38 PM PDT 24
Finished Apr 28 01:21:41 PM PDT 24
Peak memory 237144 kb
Host smart-e17c0508-4012-411d-842c-a0d18a6f396f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=265332979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.265332979
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1011440811
Short name T172
Test name
Test status
Simulation time 172793277 ps
CPU time 2.87 seconds
Started Apr 28 01:21:48 PM PDT 24
Finished Apr 28 01:21:52 PM PDT 24
Peak memory 237088 kb
Host smart-ec5ec07a-8891-404d-9e1e-78221b6bc239
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1011440811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1011440811
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2334552918
Short name T184
Test name
Test status
Simulation time 63272248 ps
CPU time 2.74 seconds
Started Apr 28 01:21:47 PM PDT 24
Finished Apr 28 01:21:50 PM PDT 24
Peak memory 236256 kb
Host smart-c1bf7b8c-2253-46df-93ed-9c26367868d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2334552918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.2334552918
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.627376871
Short name T182
Test name
Test status
Simulation time 5389533575 ps
CPU time 79.71 seconds
Started Apr 28 01:22:00 PM PDT 24
Finished Apr 28 01:23:20 PM PDT 24
Peak memory 249044 kb
Host smart-09bbf618-4269-4486-ad95-6bb06ea78541
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=627376871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.627376871
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1812772035
Short name T179
Test name
Test status
Simulation time 34988090 ps
CPU time 2.84 seconds
Started Apr 28 01:22:02 PM PDT 24
Finished Apr 28 01:22:05 PM PDT 24
Peak memory 237248 kb
Host smart-d37bacba-711a-4167-9195-1bbea46735f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1812772035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.1812772035
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.1474341674
Short name T59
Test name
Test status
Simulation time 94040080212 ps
CPU time 1508.33 seconds
Started Apr 28 04:18:14 PM PDT 24
Finished Apr 28 04:43:23 PM PDT 24
Peak memory 265136 kb
Host smart-8e777da2-9ac5-47ba-91a0-566b6b4a631a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474341674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.1474341674
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3903832997
Short name T763
Test name
Test status
Simulation time 1938005110 ps
CPU time 110.92 seconds
Started Apr 28 01:20:49 PM PDT 24
Finished Apr 28 01:22:40 PM PDT 24
Peak memory 240620 kb
Host smart-86d15f75-ecac-4369-ae80-554c329d357f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3903832997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.3903832997
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1696405646
Short name T730
Test name
Test status
Simulation time 8886039223 ps
CPU time 226.15 seconds
Started Apr 28 01:20:51 PM PDT 24
Finished Apr 28 01:24:38 PM PDT 24
Peak memory 240780 kb
Host smart-051f71b0-5283-4a2c-a4b3-4fe5415b6d9a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1696405646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.1696405646
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2915550861
Short name T783
Test name
Test status
Simulation time 758008133 ps
CPU time 9.94 seconds
Started Apr 28 01:20:49 PM PDT 24
Finished Apr 28 01:21:00 PM PDT 24
Peak memory 240588 kb
Host smart-fe0fc553-092c-467b-a1e1-d42379b23b0b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2915550861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2915550861
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.664419195
Short name T180
Test name
Test status
Simulation time 126607385 ps
CPU time 3.09 seconds
Started Apr 28 01:20:49 PM PDT 24
Finished Apr 28 01:20:52 PM PDT 24
Peak memory 239876 kb
Host smart-4d29c5a9-b8b8-4382-83d2-264ad6ed52e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=664419195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.664419195
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.1276320533
Short name T349
Test name
Test status
Simulation time 9454720 ps
CPU time 1.3 seconds
Started Apr 28 01:20:44 PM PDT 24
Finished Apr 28 01:20:46 PM PDT 24
Peak memory 235172 kb
Host smart-3577625d-96c5-42e6-9281-135d8a7397d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1276320533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.1276320533
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3802669446
Short name T716
Test name
Test status
Simulation time 682846100 ps
CPU time 38.6 seconds
Started Apr 28 01:20:54 PM PDT 24
Finished Apr 28 01:21:33 PM PDT 24
Peak memory 245440 kb
Host smart-1891784f-f73d-4cc6-add5-548cb5699fb8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3802669446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.3802669446
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3836492976
Short name T818
Test name
Test status
Simulation time 305611261 ps
CPU time 17.84 seconds
Started Apr 28 01:20:46 PM PDT 24
Finished Apr 28 01:21:05 PM PDT 24
Peak memory 249024 kb
Host smart-a33c4df3-23d4-4d3a-a876-6588168f95b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3836492976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3836492976
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.921679705
Short name T751
Test name
Test status
Simulation time 4142079607 ps
CPU time 133.03 seconds
Started Apr 28 01:21:00 PM PDT 24
Finished Apr 28 01:23:14 PM PDT 24
Peak memory 240700 kb
Host smart-79c9cccd-aa82-4dfb-8661-b6bbd805d8e2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=921679705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.921679705
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3632812383
Short name T360
Test name
Test status
Simulation time 12556260528 ps
CPU time 163.19 seconds
Started Apr 28 01:21:00 PM PDT 24
Finished Apr 28 01:23:44 PM PDT 24
Peak memory 236284 kb
Host smart-cb0e580a-0c2a-47cd-8eb2-0e7419b4bae5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3632812383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.3632812383
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.3458452121
Short name T820
Test name
Test status
Simulation time 158907707 ps
CPU time 3.46 seconds
Started Apr 28 01:20:55 PM PDT 24
Finished Apr 28 01:20:59 PM PDT 24
Peak memory 240680 kb
Host smart-67afbd53-be2e-4d5f-bc28-651696a08133
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3458452121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.3458452121
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3772165158
Short name T715
Test name
Test status
Simulation time 64184268 ps
CPU time 5.07 seconds
Started Apr 28 01:20:57 PM PDT 24
Finished Apr 28 01:21:02 PM PDT 24
Peak memory 242732 kb
Host smart-801a82b2-6505-4fdc-ae2b-8c8ba12643ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772165158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.3772165158
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.121400867
Short name T773
Test name
Test status
Simulation time 93763858 ps
CPU time 4.47 seconds
Started Apr 28 01:20:58 PM PDT 24
Finished Apr 28 01:21:03 PM PDT 24
Peak memory 237068 kb
Host smart-d709e09f-c673-4157-a5ea-e95974bce73e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=121400867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.121400867
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.1138225974
Short name T771
Test name
Test status
Simulation time 31071886 ps
CPU time 2.25 seconds
Started Apr 28 01:20:54 PM PDT 24
Finished Apr 28 01:20:57 PM PDT 24
Peak memory 236224 kb
Host smart-25e45b74-98e0-49ab-890d-7efdb9cd095e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1138225974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.1138225974
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.2400867302
Short name T792
Test name
Test status
Simulation time 2856712300 ps
CPU time 42.42 seconds
Started Apr 28 01:21:00 PM PDT 24
Finished Apr 28 01:21:43 PM PDT 24
Peak memory 245464 kb
Host smart-3fa2b6e0-ca73-4252-a0e9-1f8d2eef480c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2400867302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.2400867302
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3251939935
Short name T161
Test name
Test status
Simulation time 10238409374 ps
CPU time 133.61 seconds
Started Apr 28 01:20:54 PM PDT 24
Finished Apr 28 01:23:08 PM PDT 24
Peak memory 265832 kb
Host smart-63b6d1ed-10e6-4d7b-b484-4c13ab7a8c58
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3251939935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.3251939935
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.3882598407
Short name T707
Test name
Test status
Simulation time 902340789 ps
CPU time 27.22 seconds
Started Apr 28 01:20:54 PM PDT 24
Finished Apr 28 01:21:21 PM PDT 24
Peak memory 248624 kb
Host smart-ece3cac9-b94e-455c-a7bd-064cda83beb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3882598407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.3882598407
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.174388062
Short name T272
Test name
Test status
Simulation time 549694282 ps
CPU time 34.28 seconds
Started Apr 28 01:20:54 PM PDT 24
Finished Apr 28 01:21:28 PM PDT 24
Peak memory 237380 kb
Host smart-5be92bd7-fa6b-4c77-914c-19ea9b2ff9f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=174388062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.174388062
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2632762157
Short name T361
Test name
Test status
Simulation time 109150868 ps
CPU time 4.86 seconds
Started Apr 28 01:21:35 PM PDT 24
Finished Apr 28 01:21:40 PM PDT 24
Peak memory 240128 kb
Host smart-c40649d7-cd7d-4f32-944a-d78ff33b6ce6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632762157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.2632762157
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3139713458
Short name T723
Test name
Test status
Simulation time 59927889 ps
CPU time 4.42 seconds
Started Apr 28 01:21:30 PM PDT 24
Finished Apr 28 01:21:35 PM PDT 24
Peak memory 236212 kb
Host smart-8be7b872-0830-4c63-8947-d3f72aa1be86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3139713458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.3139713458
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.4180386856
Short name T767
Test name
Test status
Simulation time 12455841 ps
CPU time 1.2 seconds
Started Apr 28 01:21:28 PM PDT 24
Finished Apr 28 01:21:30 PM PDT 24
Peak memory 237212 kb
Host smart-536f5660-6e24-422f-8ab0-ac9fce35304d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4180386856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.4180386856
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.915584387
Short name T764
Test name
Test status
Simulation time 522585503 ps
CPU time 35.43 seconds
Started Apr 28 01:21:30 PM PDT 24
Finished Apr 28 01:22:06 PM PDT 24
Peak memory 248916 kb
Host smart-3d1971b4-1d26-471d-b63e-9e0e2698c5da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=915584387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_out
standing.915584387
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3527634666
Short name T153
Test name
Test status
Simulation time 14566281770 ps
CPU time 460.81 seconds
Started Apr 28 01:21:38 PM PDT 24
Finished Apr 28 01:29:20 PM PDT 24
Peak memory 269336 kb
Host smart-596ab9ef-b49f-4a2d-a9a4-c922f19f6797
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527634666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.3527634666
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.2341819162
Short name T802
Test name
Test status
Simulation time 87346085 ps
CPU time 6.01 seconds
Started Apr 28 01:21:32 PM PDT 24
Finished Apr 28 01:21:39 PM PDT 24
Peak memory 248956 kb
Host smart-3adf8509-194e-4954-88e5-0eedc11569b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2341819162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.2341819162
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2458357077
Short name T740
Test name
Test status
Simulation time 491498205 ps
CPU time 10.45 seconds
Started Apr 28 01:21:38 PM PDT 24
Finished Apr 28 01:21:50 PM PDT 24
Peak memory 251196 kb
Host smart-fe6d6c25-08fe-46f5-93de-2fe80dcc9876
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458357077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.2458357077
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.3204271205
Short name T731
Test name
Test status
Simulation time 59159863 ps
CPU time 4.7 seconds
Started Apr 28 01:21:34 PM PDT 24
Finished Apr 28 01:21:40 PM PDT 24
Peak memory 237072 kb
Host smart-38c99686-92d4-48c5-8e65-4e143d8f287c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3204271205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.3204271205
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2521877526
Short name T780
Test name
Test status
Simulation time 15995498 ps
CPU time 1.28 seconds
Started Apr 28 01:21:34 PM PDT 24
Finished Apr 28 01:21:35 PM PDT 24
Peak memory 237236 kb
Host smart-81c7822f-3dc4-4617-a6f5-6837de18dd18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2521877526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.2521877526
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.632832382
Short name T195
Test name
Test status
Simulation time 301396605 ps
CPU time 17.94 seconds
Started Apr 28 01:21:34 PM PDT 24
Finished Apr 28 01:21:52 PM PDT 24
Peak memory 244372 kb
Host smart-235509ae-f23d-4c75-9a08-a8676e194036
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=632832382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_out
standing.632832382
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3601006439
Short name T138
Test name
Test status
Simulation time 1556503638 ps
CPU time 83.78 seconds
Started Apr 28 01:21:33 PM PDT 24
Finished Apr 28 01:22:57 PM PDT 24
Peak memory 257300 kb
Host smart-d7f81acc-1b06-4334-837a-54e7a78dced1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3601006439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.3601006439
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3770221207
Short name T162
Test name
Test status
Simulation time 17463384126 ps
CPU time 1034.64 seconds
Started Apr 28 01:21:36 PM PDT 24
Finished Apr 28 01:38:51 PM PDT 24
Peak memory 265656 kb
Host smart-123a478a-5c06-40b8-80bd-6b3bed299d1e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770221207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.3770221207
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.1498524439
Short name T822
Test name
Test status
Simulation time 163416226 ps
CPU time 11.13 seconds
Started Apr 28 01:21:34 PM PDT 24
Finished Apr 28 01:21:46 PM PDT 24
Peak memory 248536 kb
Host smart-9e728416-2867-408e-b2bb-0721a2034e69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1498524439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.1498524439
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3041050212
Short name T357
Test name
Test status
Simulation time 215826257 ps
CPU time 4.81 seconds
Started Apr 28 01:21:41 PM PDT 24
Finished Apr 28 01:21:46 PM PDT 24
Peak memory 239620 kb
Host smart-25ce595b-ff3f-463d-ab93-3d95cb5ee28c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041050212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.3041050212
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.3100031107
Short name T814
Test name
Test status
Simulation time 66710089 ps
CPU time 3.13 seconds
Started Apr 28 01:21:40 PM PDT 24
Finished Apr 28 01:21:44 PM PDT 24
Peak memory 237104 kb
Host smart-201b969e-6ff7-4b5f-b839-fd388ace844e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3100031107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.3100031107
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3054726618
Short name T796
Test name
Test status
Simulation time 15176150 ps
CPU time 1.25 seconds
Started Apr 28 01:21:45 PM PDT 24
Finished Apr 28 01:21:46 PM PDT 24
Peak memory 236316 kb
Host smart-8219aa77-0cc1-4b01-909f-0642bd16906e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3054726618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.3054726618
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1349418985
Short name T807
Test name
Test status
Simulation time 309416429 ps
CPU time 11.78 seconds
Started Apr 28 01:21:44 PM PDT 24
Finished Apr 28 01:21:56 PM PDT 24
Peak memory 245428 kb
Host smart-16285243-9403-4619-a6eb-45fd012c7929
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1349418985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.1349418985
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2495536162
Short name T142
Test name
Test status
Simulation time 37966991504 ps
CPU time 305.44 seconds
Started Apr 28 01:21:38 PM PDT 24
Finished Apr 28 01:26:44 PM PDT 24
Peak memory 265668 kb
Host smart-186eac25-e018-4057-8b48-0662e81ebd2a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2495536162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.2495536162
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.1825092251
Short name T708
Test name
Test status
Simulation time 58579910 ps
CPU time 3.69 seconds
Started Apr 28 01:21:37 PM PDT 24
Finished Apr 28 01:21:42 PM PDT 24
Peak memory 249940 kb
Host smart-2ccc262a-4156-4c68-b305-972932d035ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1825092251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.1825092251
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.116556079
Short name T355
Test name
Test status
Simulation time 222768061 ps
CPU time 7.92 seconds
Started Apr 28 01:21:38 PM PDT 24
Finished Apr 28 01:21:46 PM PDT 24
Peak memory 249020 kb
Host smart-7c60921d-0dae-4c9d-9d43-7e7b79796d16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116556079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.alert_handler_csr_mem_rw_with_rand_reset.116556079
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.2958166739
Short name T772
Test name
Test status
Simulation time 64645906 ps
CPU time 2.96 seconds
Started Apr 28 01:21:39 PM PDT 24
Finished Apr 28 01:21:43 PM PDT 24
Peak memory 237060 kb
Host smart-2e91e43d-c330-4252-820a-291af68fe6b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2958166739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.2958166739
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.800759482
Short name T347
Test name
Test status
Simulation time 61264336 ps
CPU time 1.31 seconds
Started Apr 28 01:21:39 PM PDT 24
Finished Apr 28 01:21:41 PM PDT 24
Peak memory 236312 kb
Host smart-a8f83c29-09ba-4265-b5a2-91f0d8188664
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=800759482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.800759482
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2708887082
Short name T819
Test name
Test status
Simulation time 7108791541 ps
CPU time 33.3 seconds
Started Apr 28 01:21:37 PM PDT 24
Finished Apr 28 01:22:11 PM PDT 24
Peak memory 244428 kb
Host smart-e0c2a76d-b182-44c1-b07a-defc369ed644
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2708887082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.2708887082
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3705878262
Short name T129
Test name
Test status
Simulation time 2193864693 ps
CPU time 136.02 seconds
Started Apr 28 01:21:45 PM PDT 24
Finished Apr 28 01:24:01 PM PDT 24
Peak memory 265760 kb
Host smart-586bdea0-c66f-4c06-8a22-6d9a8f1d53f7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3705878262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.3705878262
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3984866361
Short name T791
Test name
Test status
Simulation time 6881428416 ps
CPU time 430.02 seconds
Started Apr 28 01:21:44 PM PDT 24
Finished Apr 28 01:28:54 PM PDT 24
Peak memory 265676 kb
Host smart-710350f0-da2a-435c-b507-80abd7b3670d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984866361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.3984866361
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3572591199
Short name T736
Test name
Test status
Simulation time 360482543 ps
CPU time 10.22 seconds
Started Apr 28 01:21:41 PM PDT 24
Finished Apr 28 01:21:51 PM PDT 24
Peak memory 248928 kb
Host smart-c7819762-ea72-429c-abe9-d850c8154426
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3572591199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.3572591199
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1697225654
Short name T749
Test name
Test status
Simulation time 97189087 ps
CPU time 7.26 seconds
Started Apr 28 01:21:43 PM PDT 24
Finished Apr 28 01:21:51 PM PDT 24
Peak memory 240828 kb
Host smart-6b3c8119-4314-4c2d-857a-9e4f15b6522e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697225654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.1697225654
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.811779246
Short name T181
Test name
Test status
Simulation time 62078916 ps
CPU time 5.05 seconds
Started Apr 28 01:21:43 PM PDT 24
Finished Apr 28 01:21:48 PM PDT 24
Peak memory 237024 kb
Host smart-5844c1d5-7a50-4e1a-b5fd-9519c5606cbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=811779246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.811779246
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.1653242690
Short name T722
Test name
Test status
Simulation time 1334388251 ps
CPU time 22.85 seconds
Started Apr 28 01:21:42 PM PDT 24
Finished Apr 28 01:22:06 PM PDT 24
Peak memory 245432 kb
Host smart-2468e74f-e6ba-486a-9487-f5d49a7d6882
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1653242690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.1653242690
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1297859558
Short name T159
Test name
Test status
Simulation time 86490064328 ps
CPU time 717.62 seconds
Started Apr 28 01:21:39 PM PDT 24
Finished Apr 28 01:33:37 PM PDT 24
Peak memory 265664 kb
Host smart-cdedd89c-4359-49e3-bd35-45852a818ab4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297859558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.1297859558
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1527082365
Short name T781
Test name
Test status
Simulation time 659071052 ps
CPU time 5.45 seconds
Started Apr 28 01:21:45 PM PDT 24
Finished Apr 28 01:21:51 PM PDT 24
Peak memory 240840 kb
Host smart-27b8eb31-e01b-479c-9adf-cce7f34b0f7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1527082365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.1527082365
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2295741658
Short name T786
Test name
Test status
Simulation time 110175521 ps
CPU time 4.27 seconds
Started Apr 28 01:21:48 PM PDT 24
Finished Apr 28 01:21:53 PM PDT 24
Peak memory 239484 kb
Host smart-da2085ca-14b2-4154-985b-c7ddfab6a390
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295741658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.2295741658
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.106433002
Short name T776
Test name
Test status
Simulation time 414955937 ps
CPU time 7.55 seconds
Started Apr 28 01:21:48 PM PDT 24
Finished Apr 28 01:21:56 PM PDT 24
Peak memory 236260 kb
Host smart-1d27a8c6-5f8d-432e-949e-4a86f94308b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=106433002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.106433002
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.2304271863
Short name T243
Test name
Test status
Simulation time 15176424 ps
CPU time 1.46 seconds
Started Apr 28 01:21:50 PM PDT 24
Finished Apr 28 01:21:51 PM PDT 24
Peak memory 237244 kb
Host smart-50b99113-f253-4ab5-a0f8-545fd8773a95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2304271863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.2304271863
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3577486377
Short name T813
Test name
Test status
Simulation time 4172660251 ps
CPU time 16.52 seconds
Started Apr 28 01:21:48 PM PDT 24
Finished Apr 28 01:22:05 PM PDT 24
Peak memory 245332 kb
Host smart-fb9aeaf8-5232-4c25-b016-76ae592a215b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3577486377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.3577486377
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2239116469
Short name T137
Test name
Test status
Simulation time 9569253505 ps
CPU time 319.12 seconds
Started Apr 28 01:21:42 PM PDT 24
Finished Apr 28 01:27:02 PM PDT 24
Peak memory 265808 kb
Host smart-59c8f5d5-f4e4-4e28-b5c4-d93f8b4b623c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2239116469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.2239116469
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.2023743850
Short name T130
Test name
Test status
Simulation time 30096398075 ps
CPU time 476.15 seconds
Started Apr 28 01:21:43 PM PDT 24
Finished Apr 28 01:29:39 PM PDT 24
Peak memory 265536 kb
Host smart-53ec97ac-ec6d-4d82-a0aa-ffe3ce54c94c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023743850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.2023743850
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.2496581170
Short name T808
Test name
Test status
Simulation time 49814950 ps
CPU time 5.2 seconds
Started Apr 28 01:21:50 PM PDT 24
Finished Apr 28 01:21:55 PM PDT 24
Peak memory 252348 kb
Host smart-11ac65af-d2c6-416f-852e-45244e91405b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2496581170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.2496581170
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.4172986986
Short name T359
Test name
Test status
Simulation time 127771684 ps
CPU time 5.22 seconds
Started Apr 28 01:21:54 PM PDT 24
Finished Apr 28 01:21:59 PM PDT 24
Peak memory 239512 kb
Host smart-a7dcf70d-7995-4f8c-8cb5-ff407dc2b7f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172986986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.4172986986
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.2926096995
Short name T711
Test name
Test status
Simulation time 168123720 ps
CPU time 3.45 seconds
Started Apr 28 01:21:55 PM PDT 24
Finished Apr 28 01:21:59 PM PDT 24
Peak memory 237000 kb
Host smart-80a0bdc2-bf58-484a-b021-008f05eeafbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2926096995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.2926096995
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1319371648
Short name T816
Test name
Test status
Simulation time 16439089 ps
CPU time 1.67 seconds
Started Apr 28 01:21:53 PM PDT 24
Finished Apr 28 01:21:55 PM PDT 24
Peak memory 236320 kb
Host smart-36934c2b-1ec2-4262-bde1-16f7c04313c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1319371648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1319371648
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.919078877
Short name T250
Test name
Test status
Simulation time 2735585823 ps
CPU time 41.27 seconds
Started Apr 28 01:21:52 PM PDT 24
Finished Apr 28 01:22:33 PM PDT 24
Peak memory 245512 kb
Host smart-4ceb94d2-9e4c-493e-ac9f-048a1239967d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=919078877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_out
standing.919078877
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.2020379068
Short name T806
Test name
Test status
Simulation time 94189028 ps
CPU time 6.12 seconds
Started Apr 28 01:21:48 PM PDT 24
Finished Apr 28 01:21:55 PM PDT 24
Peak memory 249008 kb
Host smart-bc701b39-a887-481f-b0de-13520f645179
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2020379068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.2020379068
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3364904918
Short name T797
Test name
Test status
Simulation time 54402230 ps
CPU time 5.11 seconds
Started Apr 28 01:21:58 PM PDT 24
Finished Apr 28 01:22:03 PM PDT 24
Peak memory 240820 kb
Host smart-6518f638-864d-4a11-8c92-3eed2de722e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364904918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.3364904918
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3647476421
Short name T799
Test name
Test status
Simulation time 65798430 ps
CPU time 5.73 seconds
Started Apr 28 01:21:58 PM PDT 24
Finished Apr 28 01:22:04 PM PDT 24
Peak memory 240644 kb
Host smart-f60ffe32-1570-4a60-bcba-0c4c450c3cb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3647476421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.3647476421
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.103909747
Short name T804
Test name
Test status
Simulation time 6496613 ps
CPU time 1.38 seconds
Started Apr 28 01:21:55 PM PDT 24
Finished Apr 28 01:21:57 PM PDT 24
Peak memory 236308 kb
Host smart-08344db2-5288-4f2c-9d8e-a024f3420ddb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=103909747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.103909747
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.4099060423
Short name T198
Test name
Test status
Simulation time 1035638828 ps
CPU time 10.4 seconds
Started Apr 28 01:21:57 PM PDT 24
Finished Apr 28 01:22:08 PM PDT 24
Peak memory 244384 kb
Host smart-b086d761-6594-4f9f-bf72-cc2912c707d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4099060423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.4099060423
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.254814376
Short name T248
Test name
Test status
Simulation time 733372212 ps
CPU time 15.45 seconds
Started Apr 28 01:21:54 PM PDT 24
Finished Apr 28 01:22:10 PM PDT 24
Peak memory 247612 kb
Host smart-4fe2e74f-2876-413e-80e4-67b18a582e2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=254814376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.254814376
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.4051057700
Short name T815
Test name
Test status
Simulation time 38604777 ps
CPU time 5.07 seconds
Started Apr 28 01:22:05 PM PDT 24
Finished Apr 28 01:22:10 PM PDT 24
Peak memory 256504 kb
Host smart-8536ffa3-0700-40dd-8e69-0223f72d1d14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051057700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.4051057700
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.1435526627
Short name T742
Test name
Test status
Simulation time 625601281 ps
CPU time 7.52 seconds
Started Apr 28 01:22:05 PM PDT 24
Finished Apr 28 01:22:13 PM PDT 24
Peak memory 240672 kb
Host smart-7a96782f-ad28-418f-8f4c-77d68e279b29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1435526627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.1435526627
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2708290347
Short name T750
Test name
Test status
Simulation time 9877161 ps
CPU time 1.47 seconds
Started Apr 28 01:21:56 PM PDT 24
Finished Apr 28 01:21:58 PM PDT 24
Peak memory 236216 kb
Host smart-af2869ce-650c-42c0-b59e-0f59c05d7b32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2708290347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.2708290347
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.399916495
Short name T790
Test name
Test status
Simulation time 97839468 ps
CPU time 11.26 seconds
Started Apr 28 01:22:03 PM PDT 24
Finished Apr 28 01:22:14 PM PDT 24
Peak memory 249016 kb
Host smart-0ef12729-961e-4824-9e61-dde71e673eb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=399916495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_out
standing.399916495
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1040247426
Short name T139
Test name
Test status
Simulation time 9543226356 ps
CPU time 318.81 seconds
Started Apr 28 01:21:59 PM PDT 24
Finished Apr 28 01:27:18 PM PDT 24
Peak memory 265620 kb
Host smart-e286c677-1a84-4e5a-b15c-598ea6ba8281
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040247426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1040247426
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1150379651
Short name T756
Test name
Test status
Simulation time 78567199 ps
CPU time 9.63 seconds
Started Apr 28 01:22:01 PM PDT 24
Finished Apr 28 01:22:11 PM PDT 24
Peak memory 248948 kb
Host smart-d301f233-66eb-4cc6-ab79-4e31eb15591e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1150379651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.1150379651
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1395102886
Short name T714
Test name
Test status
Simulation time 58960102 ps
CPU time 5.33 seconds
Started Apr 28 01:22:08 PM PDT 24
Finished Apr 28 01:22:14 PM PDT 24
Peak memory 249020 kb
Host smart-ae61681c-ef83-4e07-ba30-dd9d8dc84c34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395102886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.1395102886
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.72355242
Short name T743
Test name
Test status
Simulation time 49281043 ps
CPU time 4.44 seconds
Started Apr 28 01:22:07 PM PDT 24
Finished Apr 28 01:22:11 PM PDT 24
Peak memory 237124 kb
Host smart-a16154cf-a225-4d7a-9cff-2f120782e643
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=72355242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.72355242
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1002595916
Short name T777
Test name
Test status
Simulation time 7254930 ps
CPU time 1.34 seconds
Started Apr 28 01:22:03 PM PDT 24
Finished Apr 28 01:22:05 PM PDT 24
Peak memory 235176 kb
Host smart-645f35a6-1ddd-443f-b741-6058edefe079
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1002595916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.1002595916
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.972321055
Short name T718
Test name
Test status
Simulation time 2015662678 ps
CPU time 32.37 seconds
Started Apr 28 01:22:06 PM PDT 24
Finished Apr 28 01:22:39 PM PDT 24
Peak memory 244532 kb
Host smart-817d6c77-dc93-4ef0-b7d8-bb514d9c5fab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=972321055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_out
standing.972321055
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.751128429
Short name T158
Test name
Test status
Simulation time 6617607395 ps
CPU time 183.1 seconds
Started Apr 28 01:22:02 PM PDT 24
Finished Apr 28 01:25:05 PM PDT 24
Peak memory 265908 kb
Host smart-057bdb77-5992-4cdc-91c9-347d2d43c9e9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=751128429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_erro
rs.751128429
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.1966373673
Short name T163
Test name
Test status
Simulation time 4623540941 ps
CPU time 575.93 seconds
Started Apr 28 01:22:03 PM PDT 24
Finished Apr 28 01:31:39 PM PDT 24
Peak memory 265704 kb
Host smart-d9c9a53a-fcb8-4f5d-a233-942c0a8c153e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966373673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.1966373673
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.2635159531
Short name T739
Test name
Test status
Simulation time 354751693 ps
CPU time 9.63 seconds
Started Apr 28 01:22:01 PM PDT 24
Finished Apr 28 01:22:11 PM PDT 24
Peak memory 249060 kb
Host smart-8a43a1e1-f3b6-42f8-a548-1d3dd510a663
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2635159531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.2635159531
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.4249892429
Short name T197
Test name
Test status
Simulation time 4260639141 ps
CPU time 140.5 seconds
Started Apr 28 01:21:02 PM PDT 24
Finished Apr 28 01:23:23 PM PDT 24
Peak memory 240748 kb
Host smart-7f1926f0-bb7a-471d-b346-8f4734c3b097
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4249892429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.4249892429
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.333658715
Short name T782
Test name
Test status
Simulation time 6805937131 ps
CPU time 182.55 seconds
Started Apr 28 01:21:02 PM PDT 24
Finished Apr 28 01:24:05 PM PDT 24
Peak memory 240652 kb
Host smart-613881bf-fbf8-4719-8877-a8cac8506666
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=333658715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.333658715
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2919921971
Short name T823
Test name
Test status
Simulation time 21949254 ps
CPU time 3.69 seconds
Started Apr 28 01:21:02 PM PDT 24
Finished Apr 28 01:21:06 PM PDT 24
Peak memory 240672 kb
Host smart-22608770-08e5-464a-853b-9054f7b70681
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2919921971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.2919921971
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2643925074
Short name T746
Test name
Test status
Simulation time 35833726 ps
CPU time 5.16 seconds
Started Apr 28 01:21:08 PM PDT 24
Finished Apr 28 01:21:14 PM PDT 24
Peak memory 241648 kb
Host smart-7cf0dab8-d318-42f7-af17-086698018569
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643925074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.2643925074
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.3302996109
Short name T726
Test name
Test status
Simulation time 183879991 ps
CPU time 7.75 seconds
Started Apr 28 01:21:02 PM PDT 24
Finished Apr 28 01:21:10 PM PDT 24
Peak memory 240620 kb
Host smart-9bfc000f-6eac-42a3-88b7-c76da7c00c36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3302996109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.3302996109
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2911084535
Short name T761
Test name
Test status
Simulation time 1812983021 ps
CPU time 36.21 seconds
Started Apr 28 01:21:01 PM PDT 24
Finished Apr 28 01:21:38 PM PDT 24
Peak memory 244432 kb
Host smart-5af06f44-3452-4c94-ade8-5f5f42216c4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2911084535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.2911084535
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.135997997
Short name T157
Test name
Test status
Simulation time 3284486581 ps
CPU time 149.28 seconds
Started Apr 28 01:21:00 PM PDT 24
Finished Apr 28 01:23:30 PM PDT 24
Peak memory 265532 kb
Host smart-fdc9ca4e-83e4-4aa0-a724-072550f94074
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=135997997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_error
s.135997997
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2110015020
Short name T160
Test name
Test status
Simulation time 28550101988 ps
CPU time 426.26 seconds
Started Apr 28 01:21:00 PM PDT 24
Finished Apr 28 01:28:07 PM PDT 24
Peak memory 273588 kb
Host smart-8313921f-ea03-4d0a-99f9-33b0f38fef83
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110015020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.2110015020
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.2835427977
Short name T778
Test name
Test status
Simulation time 299157177 ps
CPU time 8.18 seconds
Started Apr 28 01:20:57 PM PDT 24
Finished Apr 28 01:21:06 PM PDT 24
Peak memory 248684 kb
Host smart-943e60d8-7bae-4e35-92cc-617dd60729d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2835427977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.2835427977
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.1246641059
Short name T724
Test name
Test status
Simulation time 13563855 ps
CPU time 1.25 seconds
Started Apr 28 01:22:07 PM PDT 24
Finished Apr 28 01:22:09 PM PDT 24
Peak memory 236212 kb
Host smart-ed94a607-fc3e-459a-9a76-ebde3d2c717d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1246641059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.1246641059
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.893625051
Short name T770
Test name
Test status
Simulation time 7290827 ps
CPU time 1.29 seconds
Started Apr 28 01:22:09 PM PDT 24
Finished Apr 28 01:22:11 PM PDT 24
Peak memory 235100 kb
Host smart-4bad9b9a-d263-48f8-96a0-c509572465da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=893625051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.893625051
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.4279899165
Short name T810
Test name
Test status
Simulation time 10249961 ps
CPU time 1.2 seconds
Started Apr 28 01:22:08 PM PDT 24
Finished Apr 28 01:22:10 PM PDT 24
Peak memory 237124 kb
Host smart-2c3366a3-dbaf-403b-965e-76ac8c9d2800
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4279899165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.4279899165
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1302476169
Short name T768
Test name
Test status
Simulation time 17979410 ps
CPU time 1.3 seconds
Started Apr 28 01:22:08 PM PDT 24
Finished Apr 28 01:22:09 PM PDT 24
Peak memory 236288 kb
Host smart-2cab1af0-60b1-4287-8fb5-dcc6ab3fdfef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1302476169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1302476169
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1849669570
Short name T794
Test name
Test status
Simulation time 8598418 ps
CPU time 1.43 seconds
Started Apr 28 01:22:06 PM PDT 24
Finished Apr 28 01:22:08 PM PDT 24
Peak memory 235280 kb
Host smart-c6a30141-ed60-46b2-afd7-23cdd9a7da50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1849669570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.1849669570
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.58392235
Short name T745
Test name
Test status
Simulation time 10336981 ps
CPU time 1.54 seconds
Started Apr 28 01:22:07 PM PDT 24
Finished Apr 28 01:22:09 PM PDT 24
Peak memory 236344 kb
Host smart-6750b9fa-9733-4e3c-8bb3-32639a384821
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=58392235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.58392235
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.333623176
Short name T754
Test name
Test status
Simulation time 24366265 ps
CPU time 2.11 seconds
Started Apr 28 01:22:08 PM PDT 24
Finished Apr 28 01:22:11 PM PDT 24
Peak memory 237240 kb
Host smart-ed93495a-3880-4808-893b-0058108e1b06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=333623176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.333623176
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.265381128
Short name T167
Test name
Test status
Simulation time 18235727 ps
CPU time 1.24 seconds
Started Apr 28 01:22:09 PM PDT 24
Finished Apr 28 01:22:10 PM PDT 24
Peak memory 237164 kb
Host smart-75e5c7d9-d2be-4953-84f4-97e16bf3e6c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=265381128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.265381128
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.2220723652
Short name T762
Test name
Test status
Simulation time 15103153 ps
CPU time 1.44 seconds
Started Apr 28 01:22:08 PM PDT 24
Finished Apr 28 01:22:10 PM PDT 24
Peak memory 237216 kb
Host smart-b8a3b28e-1ea1-460e-be6a-3d404122c904
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2220723652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.2220723652
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.1981184733
Short name T817
Test name
Test status
Simulation time 9346822 ps
CPU time 1.25 seconds
Started Apr 28 01:22:09 PM PDT 24
Finished Apr 28 01:22:11 PM PDT 24
Peak memory 236144 kb
Host smart-d866bbe4-e4a0-4fbc-9238-1a393ed260e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1981184733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.1981184733
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3372931039
Short name T183
Test name
Test status
Simulation time 4344245736 ps
CPU time 274.98 seconds
Started Apr 28 01:21:11 PM PDT 24
Finished Apr 28 01:25:46 PM PDT 24
Peak memory 240676 kb
Host smart-c8f7cca2-8d2e-4ed7-bf19-742e9a238dd9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3372931039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.3372931039
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.2799155294
Short name T748
Test name
Test status
Simulation time 14842316059 ps
CPU time 195.77 seconds
Started Apr 28 01:21:18 PM PDT 24
Finished Apr 28 01:24:34 PM PDT 24
Peak memory 236952 kb
Host smart-b016575a-f41d-4341-82de-1ca293b1ac69
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2799155294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.2799155294
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.365802492
Short name T727
Test name
Test status
Simulation time 75494359 ps
CPU time 3.71 seconds
Started Apr 28 01:21:12 PM PDT 24
Finished Apr 28 01:21:16 PM PDT 24
Peak memory 240680 kb
Host smart-e823f018-d936-4eb2-8201-cc3df9e03f6b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=365802492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.365802492
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.4185399377
Short name T356
Test name
Test status
Simulation time 118469962 ps
CPU time 4.41 seconds
Started Apr 28 01:21:14 PM PDT 24
Finished Apr 28 01:21:19 PM PDT 24
Peak memory 240492 kb
Host smart-40499d2d-238d-44d6-a4ba-a07b248411e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185399377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.4185399377
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.3483447530
Short name T760
Test name
Test status
Simulation time 518395240 ps
CPU time 7.42 seconds
Started Apr 28 01:21:18 PM PDT 24
Finished Apr 28 01:21:26 PM PDT 24
Peak memory 236212 kb
Host smart-f4441f3f-faf8-4942-a3a8-3f5e45d76249
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3483447530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.3483447530
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.701718266
Short name T809
Test name
Test status
Simulation time 7454094 ps
CPU time 1.23 seconds
Started Apr 28 01:21:11 PM PDT 24
Finished Apr 28 01:21:13 PM PDT 24
Peak memory 235172 kb
Host smart-8a39ba6f-bde8-4d53-9a73-b41760a599aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=701718266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.701718266
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.3769025364
Short name T757
Test name
Test status
Simulation time 721642379 ps
CPU time 22.09 seconds
Started Apr 28 01:21:11 PM PDT 24
Finished Apr 28 01:21:33 PM PDT 24
Peak memory 245372 kb
Host smart-ebb1ec99-fd0e-4dda-bc35-b4b983f4e4ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3769025364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.3769025364
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.3960933351
Short name T144
Test name
Test status
Simulation time 1961192142 ps
CPU time 140.9 seconds
Started Apr 28 01:21:06 PM PDT 24
Finished Apr 28 01:23:28 PM PDT 24
Peak memory 257420 kb
Host smart-cb980d0d-5d12-4a17-95be-b9a2db33c7a4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3960933351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.3960933351
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.337732106
Short name T147
Test name
Test status
Simulation time 50588469919 ps
CPU time 922.01 seconds
Started Apr 28 01:21:07 PM PDT 24
Finished Apr 28 01:36:29 PM PDT 24
Peak memory 265640 kb
Host smart-6453e773-f571-4c58-95f6-bf398519577c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337732106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.337732106
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3110846831
Short name T800
Test name
Test status
Simulation time 1503915380 ps
CPU time 14.17 seconds
Started Apr 28 01:21:18 PM PDT 24
Finished Apr 28 01:21:33 PM PDT 24
Peak memory 248936 kb
Host smart-6f0add0f-b4d3-467d-8d2d-d36ab548b954
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3110846831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.3110846831
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.3183747408
Short name T732
Test name
Test status
Simulation time 2400511979 ps
CPU time 37.34 seconds
Started Apr 28 01:21:12 PM PDT 24
Finished Apr 28 01:21:49 PM PDT 24
Peak memory 240840 kb
Host smart-18e763a6-492b-4cdb-b079-00c05feb0d3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3183747408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.3183747408
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.1843261902
Short name T737
Test name
Test status
Simulation time 9289414 ps
CPU time 1.21 seconds
Started Apr 28 01:22:12 PM PDT 24
Finished Apr 28 01:22:14 PM PDT 24
Peak memory 237132 kb
Host smart-a4e1a675-8183-4295-af66-15427f5ff7a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1843261902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.1843261902
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3955127968
Short name T752
Test name
Test status
Simulation time 8579311 ps
CPU time 1.32 seconds
Started Apr 28 01:22:12 PM PDT 24
Finished Apr 28 01:22:14 PM PDT 24
Peak memory 236300 kb
Host smart-411b20ce-cffb-4b72-880e-490254504823
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3955127968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.3955127968
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3702857423
Short name T733
Test name
Test status
Simulation time 13469445 ps
CPU time 1.41 seconds
Started Apr 28 01:22:11 PM PDT 24
Finished Apr 28 01:22:13 PM PDT 24
Peak memory 236144 kb
Host smart-38670d51-eb72-4d90-ab71-fab4d00b9782
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3702857423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.3702857423
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.3866859509
Short name T795
Test name
Test status
Simulation time 15507783 ps
CPU time 1.63 seconds
Started Apr 28 01:22:13 PM PDT 24
Finished Apr 28 01:22:15 PM PDT 24
Peak memory 235264 kb
Host smart-ea038de0-c8f8-454e-85b6-c0b2f3a3b1da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3866859509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.3866859509
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.4209168413
Short name T352
Test name
Test status
Simulation time 31245375 ps
CPU time 1.35 seconds
Started Apr 28 01:22:12 PM PDT 24
Finished Apr 28 01:22:13 PM PDT 24
Peak memory 237188 kb
Host smart-12457d91-7d2f-452e-ad00-d14534632cab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4209168413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.4209168413
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3249168849
Short name T805
Test name
Test status
Simulation time 11258447 ps
CPU time 1.56 seconds
Started Apr 28 01:22:13 PM PDT 24
Finished Apr 28 01:22:15 PM PDT 24
Peak memory 237252 kb
Host smart-386bf3f9-d0bb-45da-b752-705b2cea1b12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3249168849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3249168849
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1982860703
Short name T758
Test name
Test status
Simulation time 7424887 ps
CPU time 1.42 seconds
Started Apr 28 01:22:10 PM PDT 24
Finished Apr 28 01:22:12 PM PDT 24
Peak memory 237232 kb
Host smart-66132778-ca0b-4b51-a2a8-7d99631f56d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1982860703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.1982860703
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3577115579
Short name T774
Test name
Test status
Simulation time 7795457 ps
CPU time 1.37 seconds
Started Apr 28 01:22:12 PM PDT 24
Finished Apr 28 01:22:13 PM PDT 24
Peak memory 237172 kb
Host smart-f0894042-5b84-4d62-aa40-eb4b5665315e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3577115579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.3577115579
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1760445513
Short name T759
Test name
Test status
Simulation time 12529167 ps
CPU time 1.29 seconds
Started Apr 28 01:22:12 PM PDT 24
Finished Apr 28 01:22:14 PM PDT 24
Peak memory 236312 kb
Host smart-a1309322-8a44-4022-ad02-5423064c003b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1760445513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.1760445513
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.647775089
Short name T734
Test name
Test status
Simulation time 16641086 ps
CPU time 1.2 seconds
Started Apr 28 01:22:11 PM PDT 24
Finished Apr 28 01:22:13 PM PDT 24
Peak memory 237264 kb
Host smart-414bdd40-281c-48f9-b68a-54026fbf41f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=647775089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.647775089
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.4285664517
Short name T713
Test name
Test status
Simulation time 12033195057 ps
CPU time 277.22 seconds
Started Apr 28 01:21:21 PM PDT 24
Finished Apr 28 01:25:58 PM PDT 24
Peak memory 240912 kb
Host smart-73e3cfac-6ba9-4174-925c-01c21105e6de
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4285664517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.4285664517
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.3702741799
Short name T789
Test name
Test status
Simulation time 1653025498 ps
CPU time 184.48 seconds
Started Apr 28 01:21:24 PM PDT 24
Finished Apr 28 01:24:29 PM PDT 24
Peak memory 237052 kb
Host smart-3ac12505-61ac-4a13-a6ff-78e6d50b86a5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3702741799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.3702741799
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.1030067926
Short name T168
Test name
Test status
Simulation time 402579124 ps
CPU time 9.02 seconds
Started Apr 28 01:21:23 PM PDT 24
Finished Apr 28 01:21:32 PM PDT 24
Peak memory 240704 kb
Host smart-52957f61-c64d-4fa6-8a0a-4767a0684094
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1030067926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.1030067926
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2608679396
Short name T738
Test name
Test status
Simulation time 91674781 ps
CPU time 6.62 seconds
Started Apr 28 01:21:22 PM PDT 24
Finished Apr 28 01:21:29 PM PDT 24
Peak memory 238992 kb
Host smart-a1e181d3-e64f-4163-b411-ddeb2b995cf6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608679396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.2608679396
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.4007527062
Short name T775
Test name
Test status
Simulation time 23867724 ps
CPU time 3.13 seconds
Started Apr 28 01:21:20 PM PDT 24
Finished Apr 28 01:21:23 PM PDT 24
Peak memory 237164 kb
Host smart-a95831b3-6f5f-42b6-bd6b-3fa9c6c825f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4007527062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.4007527062
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.51885436
Short name T769
Test name
Test status
Simulation time 24201626 ps
CPU time 1.38 seconds
Started Apr 28 01:21:21 PM PDT 24
Finished Apr 28 01:21:23 PM PDT 24
Peak memory 237156 kb
Host smart-c38e0bee-9b65-4894-8725-a88b88cbaa65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=51885436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.51885436
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3157028274
Short name T712
Test name
Test status
Simulation time 85465372 ps
CPU time 11.26 seconds
Started Apr 28 01:21:22 PM PDT 24
Finished Apr 28 01:21:34 PM PDT 24
Peak memory 245424 kb
Host smart-6dec9fbd-6888-49be-8a5b-89133eb9d153
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3157028274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.3157028274
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1678042953
Short name T362
Test name
Test status
Simulation time 27096839892 ps
CPU time 567.63 seconds
Started Apr 28 01:21:15 PM PDT 24
Finished Apr 28 01:30:43 PM PDT 24
Peak memory 272936 kb
Host smart-5d9186f0-d943-4170-a1cf-c0e340363b20
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678042953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.1678042953
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.3070575361
Short name T812
Test name
Test status
Simulation time 620209245 ps
CPU time 11.44 seconds
Started Apr 28 01:21:18 PM PDT 24
Finished Apr 28 01:21:29 PM PDT 24
Peak memory 248668 kb
Host smart-f5b2b10d-878d-4925-865b-df2d894628c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3070575361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.3070575361
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1164251997
Short name T729
Test name
Test status
Simulation time 1645797166 ps
CPU time 29.91 seconds
Started Apr 28 01:21:16 PM PDT 24
Finished Apr 28 01:21:46 PM PDT 24
Peak memory 237184 kb
Host smart-bda34a75-92c7-4302-8e72-8208ec4b2103
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1164251997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.1164251997
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.82736015
Short name T765
Test name
Test status
Simulation time 8489686 ps
CPU time 1.45 seconds
Started Apr 28 01:22:14 PM PDT 24
Finished Apr 28 01:22:16 PM PDT 24
Peak memory 237220 kb
Host smart-16d57e32-6285-499a-b029-da0102763cba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=82736015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.82736015
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3685968337
Short name T735
Test name
Test status
Simulation time 6857680 ps
CPU time 1.41 seconds
Started Apr 28 01:22:18 PM PDT 24
Finished Apr 28 01:22:19 PM PDT 24
Peak memory 236216 kb
Host smart-52f33700-ae81-42c6-98a6-c26fb73f5a10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3685968337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.3685968337
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.200369892
Short name T244
Test name
Test status
Simulation time 8633265 ps
CPU time 1.55 seconds
Started Apr 28 01:22:18 PM PDT 24
Finished Apr 28 01:22:20 PM PDT 24
Peak memory 236256 kb
Host smart-78535265-0eb3-4d60-9c7e-570079a395f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=200369892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.200369892
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.2058109107
Short name T801
Test name
Test status
Simulation time 31212843 ps
CPU time 1.52 seconds
Started Apr 28 01:22:15 PM PDT 24
Finished Apr 28 01:22:17 PM PDT 24
Peak memory 236260 kb
Host smart-3ea5e330-643d-416f-9424-d553a644bb7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2058109107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.2058109107
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.31400439
Short name T348
Test name
Test status
Simulation time 11931471 ps
CPU time 1.21 seconds
Started Apr 28 01:22:17 PM PDT 24
Finished Apr 28 01:22:19 PM PDT 24
Peak memory 237232 kb
Host smart-d3b4f4e0-441c-4dc5-ac61-cba25690c63a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=31400439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.31400439
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.1492756300
Short name T755
Test name
Test status
Simulation time 12072383 ps
CPU time 1.21 seconds
Started Apr 28 01:22:16 PM PDT 24
Finished Apr 28 01:22:18 PM PDT 24
Peak memory 235332 kb
Host smart-c90c9aee-f1d5-4a45-a9ef-4ebc063b4e04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1492756300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.1492756300
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.3961012881
Short name T785
Test name
Test status
Simulation time 7604947 ps
CPU time 1.35 seconds
Started Apr 28 01:22:15 PM PDT 24
Finished Apr 28 01:22:17 PM PDT 24
Peak memory 235316 kb
Host smart-b0bcf1b2-fe04-4815-9d7c-a06fc79c87de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3961012881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.3961012881
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2010566122
Short name T350
Test name
Test status
Simulation time 11029586 ps
CPU time 1.58 seconds
Started Apr 28 01:22:16 PM PDT 24
Finished Apr 28 01:22:18 PM PDT 24
Peak memory 236212 kb
Host smart-daaba553-7edc-4217-b315-aacd5fe5d705
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2010566122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.2010566122
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.4045427044
Short name T747
Test name
Test status
Simulation time 11535520 ps
CPU time 1.28 seconds
Started Apr 28 01:22:16 PM PDT 24
Finished Apr 28 01:22:17 PM PDT 24
Peak memory 236188 kb
Host smart-10e66681-ca40-43f4-a539-521ee1adc1a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4045427044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.4045427044
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2308009239
Short name T719
Test name
Test status
Simulation time 1603545037 ps
CPU time 11.52 seconds
Started Apr 28 01:21:21 PM PDT 24
Finished Apr 28 01:21:33 PM PDT 24
Peak memory 251252 kb
Host smart-46e6f4d0-1ab0-43dc-8e7f-d27833cd6314
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308009239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.2308009239
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.3541023160
Short name T196
Test name
Test status
Simulation time 51990127 ps
CPU time 4.18 seconds
Started Apr 28 01:21:21 PM PDT 24
Finished Apr 28 01:21:26 PM PDT 24
Peak memory 237168 kb
Host smart-106174a0-dc20-4cb5-b08d-bf4c27de5c28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3541023160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.3541023160
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.2908510271
Short name T821
Test name
Test status
Simulation time 11355596 ps
CPU time 1.25 seconds
Started Apr 28 01:21:21 PM PDT 24
Finished Apr 28 01:21:23 PM PDT 24
Peak memory 236332 kb
Host smart-78d5af84-d076-403f-873a-b9b269ec81a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2908510271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.2908510271
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.3044012966
Short name T788
Test name
Test status
Simulation time 927340348 ps
CPU time 17.69 seconds
Started Apr 28 01:21:24 PM PDT 24
Finished Apr 28 01:21:42 PM PDT 24
Peak memory 245324 kb
Host smart-d52f56ea-ac57-47ec-922c-8c2af8fe1701
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3044012966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.3044012966
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3060907591
Short name T150
Test name
Test status
Simulation time 2185880243 ps
CPU time 156.63 seconds
Started Apr 28 01:21:22 PM PDT 24
Finished Apr 28 01:23:59 PM PDT 24
Peak memory 265696 kb
Host smart-f56ce5de-b566-4aeb-b679-df9f0ca72ba1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3060907591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.3060907591
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2180796167
Short name T721
Test name
Test status
Simulation time 4140954870 ps
CPU time 17.46 seconds
Started Apr 28 01:21:20 PM PDT 24
Finished Apr 28 01:21:38 PM PDT 24
Peak memory 248360 kb
Host smart-6ae767c7-e88e-4c18-987b-f03520c7055c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2180796167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.2180796167
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.212532316
Short name T744
Test name
Test status
Simulation time 143267032 ps
CPU time 6.15 seconds
Started Apr 28 01:21:24 PM PDT 24
Finished Apr 28 01:21:31 PM PDT 24
Peak memory 236300 kb
Host smart-83878dae-18e1-4f38-8c02-d4884ced2e9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=212532316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.212532316
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3319299012
Short name T728
Test name
Test status
Simulation time 215549409 ps
CPU time 5.54 seconds
Started Apr 28 01:21:25 PM PDT 24
Finished Apr 28 01:21:31 PM PDT 24
Peak memory 239828 kb
Host smart-ea1bbbd0-5c61-4c7d-b34b-9a12fa736777
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319299012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.3319299012
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.195508483
Short name T793
Test name
Test status
Simulation time 7497661 ps
CPU time 1.31 seconds
Started Apr 28 01:21:22 PM PDT 24
Finished Apr 28 01:21:24 PM PDT 24
Peak memory 235312 kb
Host smart-c0d6c590-b8e2-496b-8fb0-ab5518536e31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=195508483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.195508483
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3453907097
Short name T766
Test name
Test status
Simulation time 165099453 ps
CPU time 21.22 seconds
Started Apr 28 01:21:25 PM PDT 24
Finished Apr 28 01:21:47 PM PDT 24
Peak memory 245452 kb
Host smart-f5607058-dd53-4b12-83df-1c538081692c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3453907097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.3453907097
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1909741320
Short name T135
Test name
Test status
Simulation time 1068931143 ps
CPU time 104.35 seconds
Started Apr 28 01:21:21 PM PDT 24
Finished Apr 28 01:23:06 PM PDT 24
Peak memory 265556 kb
Host smart-28338a47-588c-4326-aa56-bfa7d67f3006
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1909741320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.1909741320
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1908877325
Short name T140
Test name
Test status
Simulation time 23111465477 ps
CPU time 872.85 seconds
Started Apr 28 01:21:21 PM PDT 24
Finished Apr 28 01:35:54 PM PDT 24
Peak memory 265536 kb
Host smart-a8bf1584-dccd-4eda-b2f6-0c8f6a20acd9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908877325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.1908877325
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.4203185349
Short name T709
Test name
Test status
Simulation time 576015557 ps
CPU time 4.26 seconds
Started Apr 28 01:21:20 PM PDT 24
Finished Apr 28 01:21:25 PM PDT 24
Peak memory 249028 kb
Host smart-cbe75321-c6b2-48f4-93e2-93773baddac5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4203185349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.4203185349
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3389791293
Short name T717
Test name
Test status
Simulation time 193490277 ps
CPU time 6.33 seconds
Started Apr 28 01:21:26 PM PDT 24
Finished Apr 28 01:21:33 PM PDT 24
Peak memory 240696 kb
Host smart-5a7c39a0-783a-44a5-901c-cfb9583375b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389791293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.3389791293
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.2515177894
Short name T798
Test name
Test status
Simulation time 33812506 ps
CPU time 5.6 seconds
Started Apr 28 01:21:26 PM PDT 24
Finished Apr 28 01:21:32 PM PDT 24
Peak memory 237152 kb
Host smart-6bdb82da-ea1d-4a5d-89af-08b48d287983
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2515177894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.2515177894
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1384194857
Short name T811
Test name
Test status
Simulation time 14768233 ps
CPU time 1.22 seconds
Started Apr 28 01:21:24 PM PDT 24
Finished Apr 28 01:21:26 PM PDT 24
Peak memory 237248 kb
Host smart-eb1eebba-3441-4982-9f54-198d7784fb96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1384194857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.1384194857
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1204791778
Short name T725
Test name
Test status
Simulation time 603001682 ps
CPU time 34.58 seconds
Started Apr 28 01:21:26 PM PDT 24
Finished Apr 28 01:22:01 PM PDT 24
Peak memory 244532 kb
Host smart-37c4621c-058d-47bf-8890-1608f79678c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1204791778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.1204791778
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.392765603
Short name T143
Test name
Test status
Simulation time 9323093029 ps
CPU time 306.49 seconds
Started Apr 28 01:21:27 PM PDT 24
Finished Apr 28 01:26:34 PM PDT 24
Peak memory 265556 kb
Host smart-22480c5f-8578-4e41-9ce2-5498d34693c0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392765603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.392765603
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2690533271
Short name T710
Test name
Test status
Simulation time 285735600 ps
CPU time 5.46 seconds
Started Apr 28 01:21:38 PM PDT 24
Finished Apr 28 01:21:45 PM PDT 24
Peak memory 247992 kb
Host smart-028c651e-8022-4479-98a6-8f018c9a3b0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2690533271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.2690533271
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3967877087
Short name T178
Test name
Test status
Simulation time 51310977 ps
CPU time 3.82 seconds
Started Apr 28 01:21:25 PM PDT 24
Finished Apr 28 01:21:30 PM PDT 24
Peak memory 237264 kb
Host smart-338ab1c2-3566-478f-8ed2-3445641eb6d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3967877087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.3967877087
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1538928759
Short name T720
Test name
Test status
Simulation time 1824484236 ps
CPU time 9.83 seconds
Started Apr 28 01:21:30 PM PDT 24
Finished Apr 28 01:21:40 PM PDT 24
Peak memory 240820 kb
Host smart-1ec29683-1311-4ebe-bc75-3278da5a7120
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538928759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.1538928759
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.3913073301
Short name T753
Test name
Test status
Simulation time 65456845 ps
CPU time 5.58 seconds
Started Apr 28 01:21:38 PM PDT 24
Finished Apr 28 01:21:45 PM PDT 24
Peak memory 240596 kb
Host smart-ce51dcf7-aa93-46e7-b30c-fe8ce179ca7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3913073301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.3913073301
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1489183925
Short name T354
Test name
Test status
Simulation time 23947356 ps
CPU time 1.33 seconds
Started Apr 28 01:21:28 PM PDT 24
Finished Apr 28 01:21:30 PM PDT 24
Peak memory 236336 kb
Host smart-3723715f-af94-473d-b651-18e5fd9b5af2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1489183925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.1489183925
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.4135530178
Short name T194
Test name
Test status
Simulation time 415699280 ps
CPU time 10.01 seconds
Started Apr 28 01:21:31 PM PDT 24
Finished Apr 28 01:21:42 PM PDT 24
Peak memory 249000 kb
Host smart-d4618d0d-fb19-4a02-9dcb-7aa9d2669e8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4135530178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.4135530178
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.4101357406
Short name T151
Test name
Test status
Simulation time 4885301642 ps
CPU time 164.93 seconds
Started Apr 28 01:21:26 PM PDT 24
Finished Apr 28 01:24:11 PM PDT 24
Peak memory 266048 kb
Host smart-a2440e49-f114-4387-a942-b8a6cbffe1c9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4101357406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.4101357406
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1924253045
Short name T249
Test name
Test status
Simulation time 121742156 ps
CPU time 7.85 seconds
Started Apr 28 01:21:29 PM PDT 24
Finished Apr 28 01:21:37 PM PDT 24
Peak memory 248956 kb
Host smart-677850ec-33f3-43e3-b92b-828361b6567f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1924253045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.1924253045
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1300781095
Short name T787
Test name
Test status
Simulation time 903652096 ps
CPU time 9.22 seconds
Started Apr 28 01:21:31 PM PDT 24
Finished Apr 28 01:21:40 PM PDT 24
Peak memory 240828 kb
Host smart-676dc0f3-2ef7-4c84-b086-6a727ad66b09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300781095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.1300781095
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2954758430
Short name T779
Test name
Test status
Simulation time 178231103 ps
CPU time 4.46 seconds
Started Apr 28 01:21:29 PM PDT 24
Finished Apr 28 01:21:34 PM PDT 24
Peak memory 237032 kb
Host smart-e84045f4-98c5-43bf-ab14-81973f986c94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2954758430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.2954758430
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2545955364
Short name T803
Test name
Test status
Simulation time 14290844 ps
CPU time 1.67 seconds
Started Apr 28 01:21:38 PM PDT 24
Finished Apr 28 01:21:41 PM PDT 24
Peak memory 236300 kb
Host smart-fc4c5a44-95b0-4c16-8199-c68b1f7a5db4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2545955364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.2545955364
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.2510747567
Short name T741
Test name
Test status
Simulation time 1107702851 ps
CPU time 17.03 seconds
Started Apr 28 01:21:31 PM PDT 24
Finished Apr 28 01:21:49 PM PDT 24
Peak memory 244516 kb
Host smart-3b732da3-3bc6-446a-afea-0128e5e3e1b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2510747567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.2510747567
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1509661249
Short name T141
Test name
Test status
Simulation time 9238723585 ps
CPU time 151.32 seconds
Started Apr 28 01:21:31 PM PDT 24
Finished Apr 28 01:24:02 PM PDT 24
Peak memory 266368 kb
Host smart-fca242f8-3a0e-40f2-861c-32c1c91a75b1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1509661249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.1509661249
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.1327047147
Short name T136
Test name
Test status
Simulation time 4728729552 ps
CPU time 276.46 seconds
Started Apr 28 01:21:29 PM PDT 24
Finished Apr 28 01:26:06 PM PDT 24
Peak memory 265740 kb
Host smart-d4c519e7-bb15-4d99-a8f2-a67089b2757c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327047147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.1327047147
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.2818447819
Short name T784
Test name
Test status
Simulation time 389281179 ps
CPU time 10.33 seconds
Started Apr 28 01:21:30 PM PDT 24
Finished Apr 28 01:21:41 PM PDT 24
Peak memory 254416 kb
Host smart-0e2fdd18-36b1-4c13-bc18-2779a5b0ef69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2818447819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.2818447819
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.520248069
Short name T271
Test name
Test status
Simulation time 3643538914 ps
CPU time 41.64 seconds
Started Apr 28 01:21:38 PM PDT 24
Finished Apr 28 01:22:21 PM PDT 24
Peak memory 249008 kb
Host smart-a82b9e42-e4e5-48db-a20e-7ed4220f507a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=520248069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.520248069
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.76947859
Short name T586
Test name
Test status
Simulation time 81267835177 ps
CPU time 3024.45 seconds
Started Apr 28 04:08:10 PM PDT 24
Finished Apr 28 04:58:35 PM PDT 24
Peak memory 289512 kb
Host smart-ef97c183-8a89-4e8c-a2e6-630fa4cb6c4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76947859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.76947859
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.3406618049
Short name T534
Test name
Test status
Simulation time 3976245897 ps
CPU time 33.63 seconds
Started Apr 28 04:08:49 PM PDT 24
Finished Apr 28 04:09:22 PM PDT 24
Peak memory 248748 kb
Host smart-c9f8c39c-195c-400b-ab6a-5bc67b25e227
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3406618049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.3406618049
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.229750264
Short name T481
Test name
Test status
Simulation time 1602835136 ps
CPU time 103.86 seconds
Started Apr 28 04:07:38 PM PDT 24
Finished Apr 28 04:09:22 PM PDT 24
Peak memory 256808 kb
Host smart-2d8bff41-5e99-4782-ac2b-cb3e9c7d14f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22975
0264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.229750264
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.4216224969
Short name T581
Test name
Test status
Simulation time 4495677227 ps
CPU time 29.24 seconds
Started Apr 28 04:07:34 PM PDT 24
Finished Apr 28 04:08:04 PM PDT 24
Peak memory 256936 kb
Host smart-33c7a3c5-2db8-422c-8060-1bd22d22c683
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42162
24969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.4216224969
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.848710456
Short name T273
Test name
Test status
Simulation time 14464155342 ps
CPU time 796.05 seconds
Started Apr 28 04:08:43 PM PDT 24
Finished Apr 28 04:22:00 PM PDT 24
Peak memory 273348 kb
Host smart-f54e8f49-787a-4c3c-ac88-7ea03904b502
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848710456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.848710456
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.2766369488
Short name T300
Test name
Test status
Simulation time 20010940116 ps
CPU time 235.25 seconds
Started Apr 28 04:08:21 PM PDT 24
Finished Apr 28 04:12:17 PM PDT 24
Peak memory 247732 kb
Host smart-bef40ffa-4140-4eca-8d98-896c341deb98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766369488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.2766369488
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.3080035776
Short name T514
Test name
Test status
Simulation time 3716681124 ps
CPU time 59.4 seconds
Started Apr 28 04:07:30 PM PDT 24
Finished Apr 28 04:08:30 PM PDT 24
Peak memory 248696 kb
Host smart-3a9f9941-fc65-4f5f-bc89-2b036e34549d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30800
35776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.3080035776
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.241148531
Short name T406
Test name
Test status
Simulation time 1544687307 ps
CPU time 50.77 seconds
Started Apr 28 04:07:32 PM PDT 24
Finished Apr 28 04:08:23 PM PDT 24
Peak memory 248944 kb
Host smart-4eb65f89-bb2d-4857-aacb-4ffef59a4cdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24114
8531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.241148531
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.1416375192
Short name T17
Test name
Test status
Simulation time 1606220486 ps
CPU time 56.57 seconds
Started Apr 28 04:07:57 PM PDT 24
Finished Apr 28 04:08:54 PM PDT 24
Peak memory 255800 kb
Host smart-e3290dfa-c0d1-4aa9-88d8-273e209be208
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14163
75192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.1416375192
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.2135959832
Short name T547
Test name
Test status
Simulation time 633236690 ps
CPU time 6.98 seconds
Started Apr 28 04:07:28 PM PDT 24
Finished Apr 28 04:07:36 PM PDT 24
Peak memory 254536 kb
Host smart-eb1bd241-9276-4b44-9f00-0b06793b5c4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21359
59832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.2135959832
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.3992272101
Short name T504
Test name
Test status
Simulation time 52020943074 ps
CPU time 1645.89 seconds
Started Apr 28 04:08:22 PM PDT 24
Finished Apr 28 04:35:48 PM PDT 24
Peak memory 282184 kb
Host smart-7ce9a6a3-4e5b-4d2d-a05f-7870c808f2f4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992272101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.3992272101
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.3736810074
Short name T445
Test name
Test status
Simulation time 52856444161 ps
CPU time 3447.5 seconds
Started Apr 28 04:09:00 PM PDT 24
Finished Apr 28 05:06:28 PM PDT 24
Peak memory 289264 kb
Host smart-2f5e3b01-4221-4cf4-8feb-0cac08097db5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736810074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.3736810074
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.1450765573
Short name T222
Test name
Test status
Simulation time 427340094 ps
CPU time 7.87 seconds
Started Apr 28 04:09:32 PM PDT 24
Finished Apr 28 04:09:40 PM PDT 24
Peak memory 240508 kb
Host smart-d8e0badd-ea3f-40b1-ad94-c855030c70c5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1450765573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.1450765573
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.246871396
Short name T282
Test name
Test status
Simulation time 3238904742 ps
CPU time 214.43 seconds
Started Apr 28 04:08:56 PM PDT 24
Finished Apr 28 04:12:31 PM PDT 24
Peak memory 256944 kb
Host smart-00d118eb-3027-416e-8c21-83d7fe9ed5be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24687
1396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.246871396
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.837610681
Short name T84
Test name
Test status
Simulation time 501910708 ps
CPU time 19.83 seconds
Started Apr 28 04:08:54 PM PDT 24
Finished Apr 28 04:09:14 PM PDT 24
Peak memory 254396 kb
Host smart-f927eb42-58a9-4077-849b-a08c6e2ecb67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83761
0681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.837610681
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.2432397851
Short name T189
Test name
Test status
Simulation time 227787737940 ps
CPU time 3035.35 seconds
Started Apr 28 04:09:17 PM PDT 24
Finished Apr 28 04:59:53 PM PDT 24
Peak memory 287204 kb
Host smart-2fc6c8d3-078f-4a20-b7d3-92d42324d4dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432397851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.2432397851
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.387885303
Short name T309
Test name
Test status
Simulation time 37216376184 ps
CPU time 122.94 seconds
Started Apr 28 04:09:16 PM PDT 24
Finished Apr 28 04:11:19 PM PDT 24
Peak memory 247748 kb
Host smart-11c0335c-d085-4845-b966-d8e8ac4620d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387885303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.387885303
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.2296443806
Short name T611
Test name
Test status
Simulation time 8725919620 ps
CPU time 38.94 seconds
Started Apr 28 04:09:08 PM PDT 24
Finished Apr 28 04:09:48 PM PDT 24
Peak memory 248788 kb
Host smart-5c1a7373-37c2-4ef7-a741-f09eca3756db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22964
43806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.2296443806
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.2488770484
Short name T551
Test name
Test status
Simulation time 1442575013 ps
CPU time 26.52 seconds
Started Apr 28 04:08:53 PM PDT 24
Finished Apr 28 04:09:20 PM PDT 24
Peak memory 254840 kb
Host smart-743e1bef-e559-42cc-8b68-c133711b0039
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24887
70484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.2488770484
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.176887420
Short name T700
Test name
Test status
Simulation time 4727662519 ps
CPU time 46.5 seconds
Started Apr 28 04:09:01 PM PDT 24
Finished Apr 28 04:09:48 PM PDT 24
Peak memory 254520 kb
Host smart-19d49b7a-25c7-4efd-af43-9f07980cd316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17688
7420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.176887420
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.1431305765
Short name T413
Test name
Test status
Simulation time 769448025 ps
CPU time 54.05 seconds
Started Apr 28 04:09:02 PM PDT 24
Finished Apr 28 04:09:56 PM PDT 24
Peak memory 255988 kb
Host smart-74308728-a94c-4f4c-bc18-de6a5cf18790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14313
05765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.1431305765
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.484965444
Short name T577
Test name
Test status
Simulation time 119094854572 ps
CPU time 1876.41 seconds
Started Apr 28 04:09:28 PM PDT 24
Finished Apr 28 04:40:45 PM PDT 24
Peak memory 273400 kb
Host smart-7459588c-c178-4c5a-90d9-295abeeead66
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484965444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_hand
ler_stress_all.484965444
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.631549346
Short name T61
Test name
Test status
Simulation time 200231511855 ps
CPU time 3033.49 seconds
Started Apr 28 04:16:00 PM PDT 24
Finished Apr 28 05:06:34 PM PDT 24
Peak memory 289416 kb
Host smart-efacee33-0d56-4512-8151-c3f62930d41c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631549346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.631549346
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.470174341
Short name T186
Test name
Test status
Simulation time 168625426 ps
CPU time 13.07 seconds
Started Apr 28 04:16:29 PM PDT 24
Finished Apr 28 04:16:43 PM PDT 24
Peak memory 248684 kb
Host smart-8bb644bd-82e7-4c07-8a59-19b34854e947
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=470174341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.470174341
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.3726471393
Short name T231
Test name
Test status
Simulation time 12492567756 ps
CPU time 122.71 seconds
Started Apr 28 04:15:45 PM PDT 24
Finished Apr 28 04:17:49 PM PDT 24
Peak memory 256896 kb
Host smart-55fae54d-3447-4b5c-b64c-a43881aef2b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37264
71393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.3726471393
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.879488047
Short name T639
Test name
Test status
Simulation time 3656214386 ps
CPU time 49.73 seconds
Started Apr 28 04:15:38 PM PDT 24
Finished Apr 28 04:16:29 PM PDT 24
Peak memory 256968 kb
Host smart-ffe85557-f4ff-4a0f-9286-3b549a8ae1b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87948
8047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.879488047
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.1522693626
Short name T665
Test name
Test status
Simulation time 16549295635 ps
CPU time 1205.63 seconds
Started Apr 28 04:16:05 PM PDT 24
Finished Apr 28 04:36:11 PM PDT 24
Peak memory 273132 kb
Host smart-9422a758-376e-4d6a-a4a5-21746faea120
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522693626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1522693626
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.1498310674
Short name T396
Test name
Test status
Simulation time 3594739670 ps
CPU time 57.08 seconds
Started Apr 28 04:15:35 PM PDT 24
Finished Apr 28 04:16:32 PM PDT 24
Peak memory 248800 kb
Host smart-3424ab77-5f64-45ac-bf50-6691997a4660
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14983
10674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.1498310674
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.3041395164
Short name T554
Test name
Test status
Simulation time 286191892 ps
CPU time 22.59 seconds
Started Apr 28 04:15:46 PM PDT 24
Finished Apr 28 04:16:09 PM PDT 24
Peak memory 248740 kb
Host smart-7e697717-9403-4e7f-8893-6d78cabb0416
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30413
95164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.3041395164
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.2091144232
Short name T232
Test name
Test status
Simulation time 347066145 ps
CPU time 24.5 seconds
Started Apr 28 04:15:48 PM PDT 24
Finished Apr 28 04:16:13 PM PDT 24
Peak memory 248640 kb
Host smart-3c21c269-2a25-4eba-af71-f88bc7fbc462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20911
44232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.2091144232
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.745304946
Short name T386
Test name
Test status
Simulation time 473932882 ps
CPU time 9.2 seconds
Started Apr 28 04:15:36 PM PDT 24
Finished Apr 28 04:15:45 PM PDT 24
Peak memory 240524 kb
Host smart-b88067b0-eec3-4463-861c-5171dad5cd26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74530
4946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.745304946
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.1976431282
Short name T70
Test name
Test status
Simulation time 316669725354 ps
CPU time 2617.51 seconds
Started Apr 28 04:15:59 PM PDT 24
Finished Apr 28 04:59:37 PM PDT 24
Peak memory 289500 kb
Host smart-7e129cf0-f3f1-41dd-aaed-7aec87172ac0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976431282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.1976431282
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.3685843723
Short name T257
Test name
Test status
Simulation time 13309397517 ps
CPU time 1559.39 seconds
Started Apr 28 04:16:06 PM PDT 24
Finished Apr 28 04:42:06 PM PDT 24
Peak memory 289412 kb
Host smart-8f23149d-1b90-4ccc-abdd-f35d18d6b897
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685843723 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.3685843723
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.3232184674
Short name T212
Test name
Test status
Simulation time 42404584 ps
CPU time 3.97 seconds
Started Apr 28 04:16:25 PM PDT 24
Finished Apr 28 04:16:29 PM PDT 24
Peak memory 248832 kb
Host smart-ea7dee29-d894-4ff5-9bf2-116dacd2b9dc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3232184674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.3232184674
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.2456152277
Short name T633
Test name
Test status
Simulation time 20092267675 ps
CPU time 832.67 seconds
Started Apr 28 04:16:17 PM PDT 24
Finished Apr 28 04:30:10 PM PDT 24
Peak memory 273364 kb
Host smart-72ac3466-dfe6-4591-87f4-112ebf689d70
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456152277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.2456152277
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.662767393
Short name T43
Test name
Test status
Simulation time 496258885 ps
CPU time 10.63 seconds
Started Apr 28 04:16:27 PM PDT 24
Finished Apr 28 04:16:38 PM PDT 24
Peak memory 248736 kb
Host smart-83875dff-aad3-42c1-8c40-a9b0c3fa981c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=662767393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.662767393
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.820335971
Short name T190
Test name
Test status
Simulation time 7370918335 ps
CPU time 68.04 seconds
Started Apr 28 04:16:07 PM PDT 24
Finished Apr 28 04:17:15 PM PDT 24
Peak memory 248752 kb
Host smart-525c8dbc-4470-4216-ad57-8c2570562de8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82033
5971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.820335971
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.2963212220
Short name T427
Test name
Test status
Simulation time 951884740 ps
CPU time 22.71 seconds
Started Apr 28 04:16:05 PM PDT 24
Finished Apr 28 04:16:29 PM PDT 24
Peak memory 256052 kb
Host smart-b035e517-a3c1-4909-bd3c-8e45e05a3216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29632
12220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.2963212220
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.3365495154
Short name T341
Test name
Test status
Simulation time 66441194674 ps
CPU time 1262.24 seconds
Started Apr 28 04:16:13 PM PDT 24
Finished Apr 28 04:37:16 PM PDT 24
Peak memory 285924 kb
Host smart-e31b7646-504f-46f5-8b16-d46bd540cc65
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365495154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.3365495154
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.2345275182
Short name T580
Test name
Test status
Simulation time 30531118774 ps
CPU time 1307.64 seconds
Started Apr 28 04:16:31 PM PDT 24
Finished Apr 28 04:38:20 PM PDT 24
Peak memory 272144 kb
Host smart-2798844d-e477-4c26-9b6d-fbbc07f0e953
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345275182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.2345275182
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.440318569
Short name T676
Test name
Test status
Simulation time 4720086479 ps
CPU time 218.04 seconds
Started Apr 28 04:16:15 PM PDT 24
Finished Apr 28 04:19:54 PM PDT 24
Peak memory 254528 kb
Host smart-8fcc0611-d719-49e9-bc9b-6ac73c86970a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440318569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.440318569
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.3756453853
Short name T559
Test name
Test status
Simulation time 4901090198 ps
CPU time 32.18 seconds
Started Apr 28 04:16:11 PM PDT 24
Finished Apr 28 04:16:43 PM PDT 24
Peak memory 255956 kb
Host smart-adc63c4f-fff5-4fd9-a230-810573ea6bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37564
53853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.3756453853
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.3382716002
Short name T605
Test name
Test status
Simulation time 52449652 ps
CPU time 4.88 seconds
Started Apr 28 04:16:09 PM PDT 24
Finished Apr 28 04:16:14 PM PDT 24
Peak memory 248736 kb
Host smart-bebf0bc4-894d-421e-a80f-d0b14b285894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33827
16002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.3382716002
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.2562063847
Short name T377
Test name
Test status
Simulation time 3022098307 ps
CPU time 52.24 seconds
Started Apr 28 04:16:15 PM PDT 24
Finished Apr 28 04:17:08 PM PDT 24
Peak memory 248740 kb
Host smart-8156f429-8d15-4fba-8d69-9cb5a9b54254
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25620
63847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.2562063847
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.2465934658
Short name T400
Test name
Test status
Simulation time 5319444316 ps
CPU time 45.81 seconds
Started Apr 28 04:16:06 PM PDT 24
Finished Apr 28 04:16:52 PM PDT 24
Peak memory 248800 kb
Host smart-3d137c8f-5fd6-416a-8806-496b61caff7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24659
34658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.2465934658
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.3324776054
Short name T289
Test name
Test status
Simulation time 3524721735 ps
CPU time 256.51 seconds
Started Apr 28 04:16:20 PM PDT 24
Finished Apr 28 04:20:37 PM PDT 24
Peak memory 256900 kb
Host smart-65c36eee-ab0c-45fd-a2fb-1c472ecc1365
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324776054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.3324776054
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.742264555
Short name T209
Test name
Test status
Simulation time 51532332 ps
CPU time 2.4 seconds
Started Apr 28 04:16:28 PM PDT 24
Finished Apr 28 04:16:31 PM PDT 24
Peak memory 248884 kb
Host smart-fa66bca1-8133-46ee-ac8b-43a3e1018d87
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=742264555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.742264555
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.2313420329
Short name T672
Test name
Test status
Simulation time 15529638652 ps
CPU time 795.6 seconds
Started Apr 28 04:16:30 PM PDT 24
Finished Apr 28 04:29:46 PM PDT 24
Peak memory 272580 kb
Host smart-5880246b-ae49-42cf-ae26-3b327b5049a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313420329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.2313420329
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.2476377189
Short name T522
Test name
Test status
Simulation time 3865799258 ps
CPU time 11.94 seconds
Started Apr 28 04:16:29 PM PDT 24
Finished Apr 28 04:16:41 PM PDT 24
Peak memory 248832 kb
Host smart-af57e71b-43f2-4d0b-b26a-9cf5b3893272
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2476377189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.2476377189
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.2255489334
Short name T517
Test name
Test status
Simulation time 1584983084 ps
CPU time 149.72 seconds
Started Apr 28 04:16:27 PM PDT 24
Finished Apr 28 04:18:58 PM PDT 24
Peak memory 250960 kb
Host smart-ddcd3a01-3cfe-410a-83b1-ff3511117c18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22554
89334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.2255489334
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.1496105191
Short name T552
Test name
Test status
Simulation time 2940623314 ps
CPU time 34.25 seconds
Started Apr 28 04:16:23 PM PDT 24
Finished Apr 28 04:16:57 PM PDT 24
Peak memory 256180 kb
Host smart-4ca43709-432a-4484-b3d2-686c5845cc5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14961
05191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.1496105191
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.1791892245
Short name T705
Test name
Test status
Simulation time 59991326440 ps
CPU time 1373.81 seconds
Started Apr 28 04:16:26 PM PDT 24
Finished Apr 28 04:39:20 PM PDT 24
Peak memory 286284 kb
Host smart-bdf6d96e-cc55-42a4-ac12-eca7cf8ecadb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791892245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.1791892245
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.455822431
Short name T663
Test name
Test status
Simulation time 23801471860 ps
CPU time 924.03 seconds
Started Apr 28 04:16:26 PM PDT 24
Finished Apr 28 04:31:51 PM PDT 24
Peak memory 269252 kb
Host smart-f6e07926-2a4a-44fe-bb63-717fd4b0ac6c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455822431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.455822431
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.1512587091
Short name T653
Test name
Test status
Simulation time 6211381673 ps
CPU time 284.13 seconds
Started Apr 28 04:16:28 PM PDT 24
Finished Apr 28 04:21:13 PM PDT 24
Peak memory 248072 kb
Host smart-39800e2e-4412-4a5a-897f-2d4e1db949bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512587091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.1512587091
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.3864144602
Short name T440
Test name
Test status
Simulation time 2430548043 ps
CPU time 18.82 seconds
Started Apr 28 04:16:18 PM PDT 24
Finished Apr 28 04:16:37 PM PDT 24
Peak memory 248772 kb
Host smart-56f3f7ad-b4ea-4283-adbf-2c913bf0757f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38641
44602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.3864144602
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.4163009013
Short name T492
Test name
Test status
Simulation time 135191325 ps
CPU time 11.92 seconds
Started Apr 28 04:16:45 PM PDT 24
Finished Apr 28 04:16:57 PM PDT 24
Peak memory 248792 kb
Host smart-9332c995-fb63-448a-ac05-590849c2e493
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41630
09013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.4163009013
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.3195994716
Short name T444
Test name
Test status
Simulation time 381620128 ps
CPU time 17.06 seconds
Started Apr 28 04:16:20 PM PDT 24
Finished Apr 28 04:16:38 PM PDT 24
Peak memory 254360 kb
Host smart-2bf7bf74-92a5-40fc-bd32-fb51f9232e92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31959
94716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.3195994716
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.1671366096
Short name T546
Test name
Test status
Simulation time 116513107 ps
CPU time 8.44 seconds
Started Apr 28 04:16:25 PM PDT 24
Finished Apr 28 04:16:33 PM PDT 24
Peak memory 248864 kb
Host smart-5cd9df80-6f76-4aac-9db1-534e09ff7e43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16713
66096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.1671366096
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.1893939816
Short name T111
Test name
Test status
Simulation time 29105305976 ps
CPU time 1315.2 seconds
Started Apr 28 04:16:27 PM PDT 24
Finished Apr 28 04:38:23 PM PDT 24
Peak memory 288392 kb
Host smart-1f9088db-8382-40cb-bf67-7ca8d4c9c2a1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893939816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.1893939816
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.1301936831
Short name T286
Test name
Test status
Simulation time 48142257034 ps
CPU time 4807.85 seconds
Started Apr 28 04:16:27 PM PDT 24
Finished Apr 28 05:36:36 PM PDT 24
Peak memory 338952 kb
Host smart-f51e5012-f549-48ba-a5a4-d3383bf2de08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301936831 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.1301936831
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.1775266435
Short name T200
Test name
Test status
Simulation time 227762404 ps
CPU time 4.48 seconds
Started Apr 28 04:16:39 PM PDT 24
Finished Apr 28 04:16:44 PM PDT 24
Peak memory 248900 kb
Host smart-dad3b003-62f1-40b5-a953-26b449ed0abb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1775266435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.1775266435
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.2729892438
Short name T666
Test name
Test status
Simulation time 122515442687 ps
CPU time 2022.77 seconds
Started Apr 28 04:16:37 PM PDT 24
Finished Apr 28 04:50:21 PM PDT 24
Peak memory 273336 kb
Host smart-33d6d4cf-006c-479a-be6f-ad90b3e13618
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729892438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.2729892438
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.2711025079
Short name T527
Test name
Test status
Simulation time 422654835 ps
CPU time 6.84 seconds
Started Apr 28 04:16:43 PM PDT 24
Finished Apr 28 04:16:50 PM PDT 24
Peak memory 248620 kb
Host smart-158e5cad-2226-4c24-9299-11f7e5faf6a4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2711025079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.2711025079
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.3958229132
Short name T24
Test name
Test status
Simulation time 5776743493 ps
CPU time 95.53 seconds
Started Apr 28 04:16:33 PM PDT 24
Finished Apr 28 04:18:09 PM PDT 24
Peak memory 256640 kb
Host smart-733393fb-5bd7-495f-9231-a03610be424e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39582
29132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.3958229132
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.867554577
Short name T86
Test name
Test status
Simulation time 292677028 ps
CPU time 29.16 seconds
Started Apr 28 04:16:38 PM PDT 24
Finished Apr 28 04:17:08 PM PDT 24
Peak memory 248724 kb
Host smart-85c3fbf7-6b59-470e-a4bd-7e3236c6020f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86755
4577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.867554577
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.1132989201
Short name T619
Test name
Test status
Simulation time 128467815629 ps
CPU time 2110.47 seconds
Started Apr 28 04:16:41 PM PDT 24
Finished Apr 28 04:51:52 PM PDT 24
Peak memory 282552 kb
Host smart-5fe8f465-d157-445c-ae54-f25d4c3107f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132989201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.1132989201
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.655176352
Short name T604
Test name
Test status
Simulation time 34058916553 ps
CPU time 2076.42 seconds
Started Apr 28 04:17:05 PM PDT 24
Finished Apr 28 04:51:42 PM PDT 24
Peak memory 273372 kb
Host smart-3b6a7905-7b1b-4c30-a62d-dfecca9de2af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655176352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.655176352
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.1596278374
Short name T594
Test name
Test status
Simulation time 40121623764 ps
CPU time 435.18 seconds
Started Apr 28 04:16:36 PM PDT 24
Finished Apr 28 04:23:52 PM PDT 24
Peak memory 248156 kb
Host smart-613cf3f4-a1e2-47ee-a81e-697bf018d72c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596278374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.1596278374
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.326834402
Short name T500
Test name
Test status
Simulation time 3704866853 ps
CPU time 60.37 seconds
Started Apr 28 04:16:43 PM PDT 24
Finished Apr 28 04:17:44 PM PDT 24
Peak memory 248796 kb
Host smart-f1f8566a-94be-4840-900a-457c6e29a625
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32683
4402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.326834402
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.3513946606
Short name T526
Test name
Test status
Simulation time 81517805 ps
CPU time 5.48 seconds
Started Apr 28 04:16:25 PM PDT 24
Finished Apr 28 04:16:31 PM PDT 24
Peak memory 240524 kb
Host smart-22cdf3a1-0762-4a14-935b-90ba232349ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35139
46606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.3513946606
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.2826068992
Short name T696
Test name
Test status
Simulation time 861329230 ps
CPU time 34.13 seconds
Started Apr 28 04:16:50 PM PDT 24
Finished Apr 28 04:17:24 PM PDT 24
Peak memory 249064 kb
Host smart-cfef1c92-60ee-45cd-a355-55fb140eb9f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28260
68992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.2826068992
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.3036079809
Short name T615
Test name
Test status
Simulation time 259990663 ps
CPU time 7.68 seconds
Started Apr 28 04:16:28 PM PDT 24
Finished Apr 28 04:16:37 PM PDT 24
Peak memory 253808 kb
Host smart-9944ea06-8beb-4ff2-948b-bbc0108d4292
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30360
79809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.3036079809
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.784020969
Short name T29
Test name
Test status
Simulation time 306469487496 ps
CPU time 2382.92 seconds
Started Apr 28 04:16:54 PM PDT 24
Finished Apr 28 04:56:37 PM PDT 24
Peak memory 305880 kb
Host smart-98b6e365-d02e-4b8e-9915-b442a57c542e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784020969 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.784020969
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.4041240078
Short name T206
Test name
Test status
Simulation time 40927441 ps
CPU time 4.39 seconds
Started Apr 28 04:17:00 PM PDT 24
Finished Apr 28 04:17:05 PM PDT 24
Peak memory 248800 kb
Host smart-a80fc4f7-761a-48c0-946f-fe0e8a904b78
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4041240078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.4041240078
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.3186992766
Short name T473
Test name
Test status
Simulation time 8230682692 ps
CPU time 868.12 seconds
Started Apr 28 04:16:57 PM PDT 24
Finished Apr 28 04:31:26 PM PDT 24
Peak memory 272872 kb
Host smart-a53ed865-0924-43ba-9e04-d311bcc66024
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186992766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.3186992766
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.3671826370
Short name T488
Test name
Test status
Simulation time 364106032 ps
CPU time 11.26 seconds
Started Apr 28 04:16:57 PM PDT 24
Finished Apr 28 04:17:09 PM PDT 24
Peak memory 248752 kb
Host smart-c8aa9a76-5e85-4609-9dc4-05c6f2a10b06
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3671826370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.3671826370
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.1089117475
Short name T493
Test name
Test status
Simulation time 7373494114 ps
CPU time 136.03 seconds
Started Apr 28 04:17:30 PM PDT 24
Finished Apr 28 04:19:46 PM PDT 24
Peak memory 256948 kb
Host smart-c7675552-6667-4b34-8600-3df47192ce0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10891
17475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.1089117475
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.3691704072
Short name T255
Test name
Test status
Simulation time 2465947970 ps
CPU time 22.73 seconds
Started Apr 28 04:16:50 PM PDT 24
Finished Apr 28 04:17:13 PM PDT 24
Peak memory 248904 kb
Host smart-702b01d4-df00-47a7-8f23-e53c5761e4ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36917
04072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3691704072
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.2286858321
Short name T617
Test name
Test status
Simulation time 16381727201 ps
CPU time 1369.89 seconds
Started Apr 28 04:16:54 PM PDT 24
Finished Apr 28 04:39:44 PM PDT 24
Peak memory 282300 kb
Host smart-628f23aa-67f0-4902-83be-278949a0c694
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286858321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.2286858321
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.2443322061
Short name T424
Test name
Test status
Simulation time 98267393688 ps
CPU time 1532.51 seconds
Started Apr 28 04:17:05 PM PDT 24
Finished Apr 28 04:42:38 PM PDT 24
Peak memory 273236 kb
Host smart-9b429bd4-ab47-40b5-939f-9c6fdb8b5be0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443322061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.2443322061
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.3334241752
Short name T320
Test name
Test status
Simulation time 5143934716 ps
CPU time 105.99 seconds
Started Apr 28 04:17:01 PM PDT 24
Finished Apr 28 04:18:48 PM PDT 24
Peak memory 247796 kb
Host smart-f3aee6ec-b64e-465b-a1df-64403901a2e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334241752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.3334241752
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.2409318204
Short name T613
Test name
Test status
Simulation time 46160528 ps
CPU time 6.21 seconds
Started Apr 28 04:16:49 PM PDT 24
Finished Apr 28 04:16:56 PM PDT 24
Peak memory 248636 kb
Host smart-d7513efc-fc5a-40e9-bc70-3d02c530b63e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24093
18204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2409318204
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.2247025455
Short name T226
Test name
Test status
Simulation time 116140475 ps
CPU time 11.16 seconds
Started Apr 28 04:16:48 PM PDT 24
Finished Apr 28 04:16:59 PM PDT 24
Peak memory 254352 kb
Host smart-e64f7237-8d77-4a6e-8d7c-b1e47afc5ab9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22470
25455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.2247025455
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.3389171501
Short name T254
Test name
Test status
Simulation time 1808146247 ps
CPU time 33.62 seconds
Started Apr 28 04:16:57 PM PDT 24
Finished Apr 28 04:17:32 PM PDT 24
Peak memory 255648 kb
Host smart-828c8878-958f-4e8d-b271-cbfbffecde55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33891
71501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.3389171501
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.158288173
Short name T523
Test name
Test status
Simulation time 726454070 ps
CPU time 47.32 seconds
Started Apr 28 04:16:46 PM PDT 24
Finished Apr 28 04:17:33 PM PDT 24
Peak memory 255944 kb
Host smart-3d748b62-3446-4af6-90bd-14a467fa3144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15828
8173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.158288173
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.2013253107
Short name T448
Test name
Test status
Simulation time 51541562152 ps
CPU time 3402.26 seconds
Started Apr 28 04:16:55 PM PDT 24
Finished Apr 28 05:13:38 PM PDT 24
Peak memory 300844 kb
Host smart-0fb6057e-8a71-4c89-82e6-4fbb48f97ccb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013253107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.2013253107
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.325981988
Short name T204
Test name
Test status
Simulation time 41887798 ps
CPU time 3.91 seconds
Started Apr 28 04:17:13 PM PDT 24
Finished Apr 28 04:17:17 PM PDT 24
Peak memory 248908 kb
Host smart-5a7e8d0e-2341-4a05-83b4-04ed78535ef5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=325981988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.325981988
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.747846449
Short name T641
Test name
Test status
Simulation time 494874443 ps
CPU time 16.05 seconds
Started Apr 28 04:17:12 PM PDT 24
Finished Apr 28 04:17:29 PM PDT 24
Peak memory 248740 kb
Host smart-3ea251e1-37e5-4bca-92d5-8af27917e6ed
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=747846449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.747846449
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.718644403
Short name T563
Test name
Test status
Simulation time 3643978031 ps
CPU time 237.73 seconds
Started Apr 28 04:17:08 PM PDT 24
Finished Apr 28 04:21:06 PM PDT 24
Peak memory 256912 kb
Host smart-f4610bff-747a-444e-9010-ac34de6fb144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71864
4403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.718644403
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.3481592564
Short name T116
Test name
Test status
Simulation time 1925050860 ps
CPU time 61.36 seconds
Started Apr 28 04:17:03 PM PDT 24
Finished Apr 28 04:18:04 PM PDT 24
Peak memory 255448 kb
Host smart-f8043cfd-0087-463c-96d6-c5ffe643a4ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34815
92564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.3481592564
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.2661172653
Short name T531
Test name
Test status
Simulation time 108546239855 ps
CPU time 1349.38 seconds
Started Apr 28 04:17:15 PM PDT 24
Finished Apr 28 04:39:44 PM PDT 24
Peak memory 272560 kb
Host smart-47cc62df-07ea-4aa4-955e-3ed64dcf91f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661172653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.2661172653
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.1470870576
Short name T464
Test name
Test status
Simulation time 11696445688 ps
CPU time 48.41 seconds
Started Apr 28 04:17:09 PM PDT 24
Finished Apr 28 04:17:57 PM PDT 24
Peak memory 248800 kb
Host smart-1291ebd7-7843-48de-a7aa-269113ee3be3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14708
70576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.1470870576
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.1039772285
Short name T610
Test name
Test status
Simulation time 229660874 ps
CPU time 17.79 seconds
Started Apr 28 04:17:01 PM PDT 24
Finished Apr 28 04:17:20 PM PDT 24
Peak memory 255156 kb
Host smart-e9a0c997-1293-4446-8ae1-56f741b6fd78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10397
72285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.1039772285
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.2406481155
Short name T403
Test name
Test status
Simulation time 60353408 ps
CPU time 2.85 seconds
Started Apr 28 04:17:09 PM PDT 24
Finished Apr 28 04:17:12 PM PDT 24
Peak memory 240468 kb
Host smart-a9d8901d-da38-4af8-b268-a98d619ecf07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24064
81155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.2406481155
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.3530255992
Short name T434
Test name
Test status
Simulation time 516330608 ps
CPU time 34.89 seconds
Started Apr 28 04:17:02 PM PDT 24
Finished Apr 28 04:17:37 PM PDT 24
Peak memory 255460 kb
Host smart-c827627c-a0ff-4f3d-ac1e-e3804e06da88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35302
55992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.3530255992
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.1075934766
Short name T208
Test name
Test status
Simulation time 125088389 ps
CPU time 3.4 seconds
Started Apr 28 04:17:29 PM PDT 24
Finished Apr 28 04:17:33 PM PDT 24
Peak memory 248932 kb
Host smart-c45977df-dca6-43cf-9d9f-58784d4edbf7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1075934766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.1075934766
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.1054778782
Short name T38
Test name
Test status
Simulation time 48581797432 ps
CPU time 1522.32 seconds
Started Apr 28 04:17:19 PM PDT 24
Finished Apr 28 04:42:42 PM PDT 24
Peak memory 265264 kb
Host smart-821b5fcc-8cc7-4e89-97df-f2f258d21e56
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054778782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1054778782
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.1851893313
Short name T521
Test name
Test status
Simulation time 1676772490 ps
CPU time 8.71 seconds
Started Apr 28 04:17:23 PM PDT 24
Finished Apr 28 04:17:32 PM PDT 24
Peak memory 240452 kb
Host smart-d31027fe-db3c-43da-be44-4b0573d883af
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1851893313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1851893313
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.3401858642
Short name T416
Test name
Test status
Simulation time 830074834 ps
CPU time 17.87 seconds
Started Apr 28 04:17:22 PM PDT 24
Finished Apr 28 04:17:40 PM PDT 24
Peak memory 255788 kb
Host smart-b36e9eab-1296-427a-bc78-2dfc61d291f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34018
58642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.3401858642
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.3784007455
Short name T461
Test name
Test status
Simulation time 32868516 ps
CPU time 4.73 seconds
Started Apr 28 04:17:15 PM PDT 24
Finished Apr 28 04:17:20 PM PDT 24
Peak memory 240712 kb
Host smart-88414720-6824-402b-8053-9df5ba70b77f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37840
07455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.3784007455
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.2647750706
Short name T391
Test name
Test status
Simulation time 183607739260 ps
CPU time 3106.45 seconds
Started Apr 28 04:17:18 PM PDT 24
Finished Apr 28 05:09:04 PM PDT 24
Peak memory 289628 kb
Host smart-c29c547b-9750-441e-8091-47d4292bd1b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647750706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.2647750706
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.2514456864
Short name T599
Test name
Test status
Simulation time 243214945 ps
CPU time 23.82 seconds
Started Apr 28 04:17:14 PM PDT 24
Finished Apr 28 04:17:38 PM PDT 24
Peak memory 247564 kb
Host smart-6173206d-da2b-4802-b3ee-c8bd58389ba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25144
56864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.2514456864
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.261795456
Short name T455
Test name
Test status
Simulation time 57867651 ps
CPU time 7.62 seconds
Started Apr 28 04:17:24 PM PDT 24
Finished Apr 28 04:17:32 PM PDT 24
Peak memory 248680 kb
Host smart-412dd024-bee1-4bab-badd-b82df94333db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26179
5456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.261795456
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.852786498
Short name T235
Test name
Test status
Simulation time 301649445 ps
CPU time 11.87 seconds
Started Apr 28 04:17:13 PM PDT 24
Finished Apr 28 04:17:26 PM PDT 24
Peak memory 254068 kb
Host smart-d7e0e732-34ac-43c1-9c23-91293e8df512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85278
6498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.852786498
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.169456098
Short name T219
Test name
Test status
Simulation time 43985490 ps
CPU time 3.3 seconds
Started Apr 28 04:17:45 PM PDT 24
Finished Apr 28 04:17:49 PM PDT 24
Peak memory 248932 kb
Host smart-2f797813-d6e2-4066-a89b-45da8660d453
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=169456098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.169456098
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.256891379
Short name T459
Test name
Test status
Simulation time 126044162327 ps
CPU time 1940.25 seconds
Started Apr 28 04:17:35 PM PDT 24
Finished Apr 28 04:49:56 PM PDT 24
Peak memory 273352 kb
Host smart-95cf5f6f-8639-4176-8481-53eefb1801bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256891379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.256891379
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.4100634300
Short name T499
Test name
Test status
Simulation time 90982413 ps
CPU time 6.56 seconds
Started Apr 28 04:17:46 PM PDT 24
Finished Apr 28 04:17:53 PM PDT 24
Peak memory 248684 kb
Host smart-6a1256b0-3985-4741-8edf-4ddc017b238d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4100634300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.4100634300
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.3534434984
Short name T695
Test name
Test status
Simulation time 28380027557 ps
CPU time 227.3 seconds
Started Apr 28 04:17:31 PM PDT 24
Finished Apr 28 04:21:19 PM PDT 24
Peak memory 250856 kb
Host smart-98384b1a-e508-4277-89b0-6666bab8af3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35344
34984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.3534434984
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.2747210065
Short name T677
Test name
Test status
Simulation time 386526838 ps
CPU time 34.29 seconds
Started Apr 28 04:17:35 PM PDT 24
Finished Apr 28 04:18:09 PM PDT 24
Peak memory 248756 kb
Host smart-e69dad26-3773-4164-9f68-3d025a19c55f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27472
10065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.2747210065
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.1420689332
Short name T308
Test name
Test status
Simulation time 45149247707 ps
CPU time 1233.51 seconds
Started Apr 28 04:17:36 PM PDT 24
Finished Apr 28 04:38:10 PM PDT 24
Peak memory 265188 kb
Host smart-dea237c8-4ab5-4c18-aad9-121ec28faa26
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420689332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.1420689332
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.3571739513
Short name T638
Test name
Test status
Simulation time 98625776060 ps
CPU time 1813.1 seconds
Started Apr 28 04:17:40 PM PDT 24
Finished Apr 28 04:47:54 PM PDT 24
Peak memory 273356 kb
Host smart-b027c255-a623-40fc-a674-af4b909e327b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571739513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3571739513
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.3231316673
Short name T317
Test name
Test status
Simulation time 10177440576 ps
CPU time 217.82 seconds
Started Apr 28 04:17:31 PM PDT 24
Finished Apr 28 04:21:10 PM PDT 24
Peak memory 247072 kb
Host smart-79fd4272-8c50-419d-92a5-2e9a27366c7f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231316673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.3231316673
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.3545975178
Short name T365
Test name
Test status
Simulation time 1857275035 ps
CPU time 69.33 seconds
Started Apr 28 04:17:47 PM PDT 24
Finished Apr 28 04:18:56 PM PDT 24
Peak memory 249028 kb
Host smart-4dde0b63-8409-4a8b-9b0e-c00e230d8103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35459
75178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.3545975178
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.969458712
Short name T533
Test name
Test status
Simulation time 175228255 ps
CPU time 25.06 seconds
Started Apr 28 04:17:35 PM PDT 24
Finished Apr 28 04:18:01 PM PDT 24
Peak memory 248696 kb
Host smart-05dd01b5-fed1-4f7c-91b3-c910211d9dc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96945
8712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.969458712
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.3768622066
Short name T122
Test name
Test status
Simulation time 895044201 ps
CPU time 59.42 seconds
Started Apr 28 04:17:32 PM PDT 24
Finished Apr 28 04:18:32 PM PDT 24
Peak memory 248984 kb
Host smart-52d1e78c-4a33-44a4-887a-a53757de1cc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37686
22066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.3768622066
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.104133509
Short name T381
Test name
Test status
Simulation time 3206511219 ps
CPU time 17.77 seconds
Started Apr 28 04:17:51 PM PDT 24
Finished Apr 28 04:18:10 PM PDT 24
Peak memory 248772 kb
Host smart-bb8ddaac-2ded-454d-8803-c9b46ed84b91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10413
3509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.104133509
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.1448910509
Short name T213
Test name
Test status
Simulation time 120009614 ps
CPU time 3.54 seconds
Started Apr 28 04:17:54 PM PDT 24
Finished Apr 28 04:17:58 PM PDT 24
Peak memory 248872 kb
Host smart-fc7ba38b-b74f-4ec5-8487-e1bd4ff3ed0e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1448910509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.1448910509
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.2383497424
Short name T673
Test name
Test status
Simulation time 69790190505 ps
CPU time 1865.79 seconds
Started Apr 28 04:17:59 PM PDT 24
Finished Apr 28 04:49:06 PM PDT 24
Peak memory 272564 kb
Host smart-2680a9f4-6b7c-4eca-8dea-1b6e4684b0a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383497424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.2383497424
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.3918096517
Short name T476
Test name
Test status
Simulation time 646159058 ps
CPU time 8.76 seconds
Started Apr 28 04:17:53 PM PDT 24
Finished Apr 28 04:18:02 PM PDT 24
Peak memory 248712 kb
Host smart-78a6a53e-dd78-4a0d-8a80-59894d4eb3a1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3918096517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.3918096517
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.4252059298
Short name T234
Test name
Test status
Simulation time 1092686290 ps
CPU time 112.37 seconds
Started Apr 28 04:17:49 PM PDT 24
Finished Apr 28 04:19:42 PM PDT 24
Peak memory 256800 kb
Host smart-662e870d-8b90-4bec-95c3-3fdc0a858841
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42520
59298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.4252059298
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.2144202801
Short name T542
Test name
Test status
Simulation time 377851086 ps
CPU time 6.45 seconds
Started Apr 28 04:17:51 PM PDT 24
Finished Apr 28 04:17:58 PM PDT 24
Peak memory 251904 kb
Host smart-ae839e19-b854-4e24-8530-a62fbb46f85a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21442
02801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.2144202801
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.3708906883
Short name T699
Test name
Test status
Simulation time 25898029850 ps
CPU time 1923.54 seconds
Started Apr 28 04:17:53 PM PDT 24
Finished Apr 28 04:49:57 PM PDT 24
Peak memory 273308 kb
Host smart-8cd5b29e-025f-4a08-97cb-475c11b2e66c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708906883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.3708906883
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.2068795127
Short name T706
Test name
Test status
Simulation time 36296398312 ps
CPU time 1193.79 seconds
Started Apr 28 04:17:54 PM PDT 24
Finished Apr 28 04:37:48 PM PDT 24
Peak memory 273012 kb
Host smart-39e20b84-3a9b-4737-90a1-1612a7af5365
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068795127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.2068795127
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.3042384946
Short name T322
Test name
Test status
Simulation time 6309231312 ps
CPU time 278.27 seconds
Started Apr 28 04:17:59 PM PDT 24
Finished Apr 28 04:22:38 PM PDT 24
Peak memory 246872 kb
Host smart-40efe16e-aa6d-4236-ba06-1108b4b5dd19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042384946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.3042384946
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.2340147089
Short name T69
Test name
Test status
Simulation time 233611058 ps
CPU time 13.07 seconds
Started Apr 28 04:17:47 PM PDT 24
Finished Apr 28 04:18:00 PM PDT 24
Peak memory 248740 kb
Host smart-f81713b3-eafa-4297-b3e4-a8b3dc3980d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23401
47089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.2340147089
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.3050201762
Short name T408
Test name
Test status
Simulation time 1069640660 ps
CPU time 43.22 seconds
Started Apr 28 04:17:46 PM PDT 24
Finished Apr 28 04:18:30 PM PDT 24
Peak memory 248680 kb
Host smart-99c9c588-2ae4-4b5b-8c07-92da9db92d27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30502
01762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.3050201762
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.1883983690
Short name T83
Test name
Test status
Simulation time 7467577831 ps
CPU time 35.46 seconds
Started Apr 28 04:17:47 PM PDT 24
Finished Apr 28 04:18:23 PM PDT 24
Peak memory 255912 kb
Host smart-d540cf40-ac4a-4037-8141-182568e54f69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18839
83690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.1883983690
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.3874790083
Short name T443
Test name
Test status
Simulation time 4488389396 ps
CPU time 68.58 seconds
Started Apr 28 04:17:42 PM PDT 24
Finished Apr 28 04:18:50 PM PDT 24
Peak memory 249108 kb
Host smart-c905b314-9810-4fa7-90d1-8fac22308084
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38747
90083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.3874790083
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.3905057818
Short name T466
Test name
Test status
Simulation time 39301623077 ps
CPU time 1438.51 seconds
Started Apr 28 04:18:02 PM PDT 24
Finished Apr 28 04:42:01 PM PDT 24
Peak memory 269924 kb
Host smart-918d7cc6-ba2f-46ee-8c3f-f898c8a16a31
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905057818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.3905057818
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.1513816781
Short name T205
Test name
Test status
Simulation time 205164274 ps
CPU time 4.78 seconds
Started Apr 28 04:18:08 PM PDT 24
Finished Apr 28 04:18:13 PM PDT 24
Peak memory 248908 kb
Host smart-4b9ae78d-0f8a-43a6-8b58-c3b9d023a41c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1513816781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.1513816781
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.1065170372
Short name T394
Test name
Test status
Simulation time 17620230633 ps
CPU time 1189.12 seconds
Started Apr 28 04:18:05 PM PDT 24
Finished Apr 28 04:37:55 PM PDT 24
Peak memory 273268 kb
Host smart-c408ad89-352a-4bf7-a571-44ccbc2e0dc6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065170372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.1065170372
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.2811726519
Short name T540
Test name
Test status
Simulation time 2219273769 ps
CPU time 28.31 seconds
Started Apr 28 04:18:03 PM PDT 24
Finished Apr 28 04:18:32 PM PDT 24
Peak memory 252408 kb
Host smart-97af7ab8-98b0-4778-a43d-f9b10395eb21
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2811726519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.2811726519
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.2276418393
Short name T371
Test name
Test status
Simulation time 920686351 ps
CPU time 80.36 seconds
Started Apr 28 04:18:02 PM PDT 24
Finished Apr 28 04:19:23 PM PDT 24
Peak memory 248680 kb
Host smart-bc5de3fb-94ad-4dfc-9fd9-0f53b296dea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22764
18393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.2276418393
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.4122132583
Short name T442
Test name
Test status
Simulation time 356155438 ps
CPU time 21.11 seconds
Started Apr 28 04:18:00 PM PDT 24
Finished Apr 28 04:18:21 PM PDT 24
Peak memory 255844 kb
Host smart-83aee899-5a2c-401e-b2c3-267abab0f435
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41221
32583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.4122132583
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.4260568008
Short name T652
Test name
Test status
Simulation time 39972749777 ps
CPU time 951.19 seconds
Started Apr 28 04:18:08 PM PDT 24
Finished Apr 28 04:33:59 PM PDT 24
Peak memory 267208 kb
Host smart-77325cb3-f73c-4f72-a0d2-194a64f31755
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260568008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.4260568008
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.4126728251
Short name T367
Test name
Test status
Simulation time 63705423885 ps
CPU time 1486.51 seconds
Started Apr 28 04:18:06 PM PDT 24
Finished Apr 28 04:42:53 PM PDT 24
Peak memory 286436 kb
Host smart-9f8b1da7-c445-4003-8ad4-b9ed35fb82c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126728251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.4126728251
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.3510672734
Short name T2
Test name
Test status
Simulation time 795032745 ps
CPU time 68.78 seconds
Started Apr 28 04:18:16 PM PDT 24
Finished Apr 28 04:19:25 PM PDT 24
Peak memory 248780 kb
Host smart-7b163794-835e-42ab-99ad-72c3f4c5bd40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35106
72734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.3510672734
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.1077618032
Short name T368
Test name
Test status
Simulation time 97956855 ps
CPU time 8.21 seconds
Started Apr 28 04:17:55 PM PDT 24
Finished Apr 28 04:18:03 PM PDT 24
Peak memory 248720 kb
Host smart-77eb07b2-1190-4500-a9aa-4d42cfb9d291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10776
18032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.1077618032
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.1299495550
Short name T643
Test name
Test status
Simulation time 410364731 ps
CPU time 26.16 seconds
Started Apr 28 04:17:56 PM PDT 24
Finished Apr 28 04:18:23 PM PDT 24
Peak memory 256916 kb
Host smart-3e552b68-9ecd-4fd6-b07f-6f2b938ce2cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12994
95550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.1299495550
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.640441327
Short name T30
Test name
Test status
Simulation time 4076424965 ps
CPU time 298.89 seconds
Started Apr 28 04:18:05 PM PDT 24
Finished Apr 28 04:23:04 PM PDT 24
Peak memory 256868 kb
Host smart-39368411-1fed-4218-84f1-69722e72d43e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640441327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_han
dler_stress_all.640441327
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.1655274177
Short name T269
Test name
Test status
Simulation time 117437363472 ps
CPU time 2449.05 seconds
Started Apr 28 04:18:13 PM PDT 24
Finished Apr 28 04:59:03 PM PDT 24
Peak memory 281696 kb
Host smart-1ce1f12e-1b69-4e6e-b18c-194856481543
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655274177 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.1655274177
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.316486041
Short name T218
Test name
Test status
Simulation time 68066162 ps
CPU time 3.81 seconds
Started Apr 28 04:10:46 PM PDT 24
Finished Apr 28 04:10:51 PM PDT 24
Peak memory 248868 kb
Host smart-9ad30cc7-89f9-40bd-8b20-55373d4ec6e6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=316486041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.316486041
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.164600738
Short name T399
Test name
Test status
Simulation time 15805980322 ps
CPU time 1582.51 seconds
Started Apr 28 04:10:11 PM PDT 24
Finished Apr 28 04:36:35 PM PDT 24
Peak memory 289376 kb
Host smart-cffd2443-f47c-4efc-9f76-5a86e6ff8ba0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164600738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.164600738
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.3785256843
Short name T422
Test name
Test status
Simulation time 476610035 ps
CPU time 14.44 seconds
Started Apr 28 04:10:16 PM PDT 24
Finished Apr 28 04:10:31 PM PDT 24
Peak memory 248692 kb
Host smart-31638c8e-7eee-4b51-8aed-8701acc533fe
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3785256843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.3785256843
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.822980543
Short name T550
Test name
Test status
Simulation time 433877416 ps
CPU time 11.11 seconds
Started Apr 28 04:10:02 PM PDT 24
Finished Apr 28 04:10:13 PM PDT 24
Peak memory 253916 kb
Host smart-e497c647-6945-4aee-9059-bc2b84ab80e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82298
0543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.822980543
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.2313416200
Short name T188
Test name
Test status
Simulation time 627507437 ps
CPU time 39.43 seconds
Started Apr 28 04:09:54 PM PDT 24
Finished Apr 28 04:10:34 PM PDT 24
Peak memory 255544 kb
Host smart-aa75a01a-62b0-48ba-8c6d-cc713ae2a928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23134
16200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.2313416200
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.3756993853
Short name T692
Test name
Test status
Simulation time 52044667237 ps
CPU time 3098.85 seconds
Started Apr 28 04:10:14 PM PDT 24
Finished Apr 28 05:01:54 PM PDT 24
Peak memory 281528 kb
Host smart-bab16db9-342c-43ef-92b5-dd22f46972c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756993853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.3756993853
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.3638949871
Short name T318
Test name
Test status
Simulation time 41728405372 ps
CPU time 543.46 seconds
Started Apr 28 04:10:39 PM PDT 24
Finished Apr 28 04:19:44 PM PDT 24
Peak memory 248024 kb
Host smart-de70af94-49e2-4ec4-94db-3130ebdb7b10
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638949871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.3638949871
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.114443600
Short name T451
Test name
Test status
Simulation time 75609555 ps
CPU time 6.14 seconds
Started Apr 28 04:09:34 PM PDT 24
Finished Apr 28 04:09:41 PM PDT 24
Peak memory 256872 kb
Host smart-4c99ab03-6d7e-4dec-83bd-52aff0293d35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11444
3600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.114443600
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.1420429173
Short name T667
Test name
Test status
Simulation time 479585328 ps
CPU time 9.66 seconds
Started Apr 28 04:09:54 PM PDT 24
Finished Apr 28 04:10:04 PM PDT 24
Peak memory 248740 kb
Host smart-d2c918fa-0ec1-44b8-a2f7-382f9372bd35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14204
29173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.1420429173
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.1945829422
Short name T32
Test name
Test status
Simulation time 144608708 ps
CPU time 15.43 seconds
Started Apr 28 04:09:55 PM PDT 24
Finished Apr 28 04:10:11 PM PDT 24
Peak memory 255440 kb
Host smart-a0d8cdb7-7990-4186-a280-0357ecf143fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19458
29422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.1945829422
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.1270749090
Short name T478
Test name
Test status
Simulation time 1280976788 ps
CPU time 90.23 seconds
Started Apr 28 04:09:55 PM PDT 24
Finished Apr 28 04:11:25 PM PDT 24
Peak memory 248724 kb
Host smart-c923bb0a-bf2f-49ce-a8e5-5cd6200d1ad3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12707
49090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.1270749090
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.264752828
Short name T623
Test name
Test status
Simulation time 90056984920 ps
CPU time 1625.6 seconds
Started Apr 28 04:10:22 PM PDT 24
Finished Apr 28 04:37:28 PM PDT 24
Peak memory 289724 kb
Host smart-79f98313-7a11-4634-b7e7-31351827237f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264752828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_hand
ler_stress_all.264752828
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.1644368244
Short name T72
Test name
Test status
Simulation time 31943922100 ps
CPU time 1197.25 seconds
Started Apr 28 04:10:26 PM PDT 24
Finished Apr 28 04:30:23 PM PDT 24
Peak memory 272388 kb
Host smart-0e609480-4d2a-47d5-8d19-987beedf007b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644368244 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.1644368244
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.2829562154
Short name T543
Test name
Test status
Simulation time 1944664553 ps
CPU time 136.7 seconds
Started Apr 28 04:18:12 PM PDT 24
Finished Apr 28 04:20:29 PM PDT 24
Peak memory 248696 kb
Host smart-76f3c809-0657-404e-9dce-56fde75e0428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28295
62154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.2829562154
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.2304128774
Short name T600
Test name
Test status
Simulation time 371661383 ps
CPU time 32.05 seconds
Started Apr 28 04:18:17 PM PDT 24
Finished Apr 28 04:18:50 PM PDT 24
Peak memory 248740 kb
Host smart-6af60e05-d0f2-46a1-b593-2b2fadef8493
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23041
28774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.2304128774
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.337956635
Short name T48
Test name
Test status
Simulation time 50989547179 ps
CPU time 2808.12 seconds
Started Apr 28 04:18:11 PM PDT 24
Finished Apr 28 05:05:00 PM PDT 24
Peak memory 280960 kb
Host smart-ff5c9e67-353d-424a-a094-2793f73e6f65
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337956635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.337956635
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.3632414648
Short name T485
Test name
Test status
Simulation time 17065854858 ps
CPU time 1299.41 seconds
Started Apr 28 04:18:14 PM PDT 24
Finished Apr 28 04:39:54 PM PDT 24
Peak memory 281576 kb
Host smart-d253447e-1693-4507-a062-db22b0472363
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632414648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.3632414648
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.3081889710
Short name T228
Test name
Test status
Simulation time 20232124100 ps
CPU time 213.61 seconds
Started Apr 28 04:18:18 PM PDT 24
Finished Apr 28 04:21:51 PM PDT 24
Peak memory 248124 kb
Host smart-97d2ffc6-dbf5-4caf-a88f-8330d73defb6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081889710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.3081889710
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.3773569449
Short name T431
Test name
Test status
Simulation time 1465054735 ps
CPU time 36.34 seconds
Started Apr 28 04:18:15 PM PDT 24
Finished Apr 28 04:18:52 PM PDT 24
Peak memory 256848 kb
Host smart-68138056-df30-4f4d-bdcb-ecd963af36c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37735
69449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.3773569449
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.3595382693
Short name T13
Test name
Test status
Simulation time 49128914 ps
CPU time 8.27 seconds
Started Apr 28 04:18:22 PM PDT 24
Finished Apr 28 04:18:31 PM PDT 24
Peak memory 248700 kb
Host smart-64e975e9-4d5c-4366-b359-9e03d3f8bad8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35953
82693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.3595382693
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.4189419999
Short name T664
Test name
Test status
Simulation time 1099404584 ps
CPU time 13.68 seconds
Started Apr 28 04:18:17 PM PDT 24
Finished Apr 28 04:18:31 PM PDT 24
Peak memory 252828 kb
Host smart-37f29c32-6b0e-48db-9c8b-3e2022692c83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41894
19999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.4189419999
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.2862169841
Short name T387
Test name
Test status
Simulation time 171534050 ps
CPU time 6.09 seconds
Started Apr 28 04:18:08 PM PDT 24
Finished Apr 28 04:18:14 PM PDT 24
Peak memory 248696 kb
Host smart-d1e98969-32a8-4d72-a6f9-3d7b3ffd167e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28621
69841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.2862169841
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.2226205135
Short name T549
Test name
Test status
Simulation time 14092782797 ps
CPU time 812.81 seconds
Started Apr 28 04:18:15 PM PDT 24
Finished Apr 28 04:31:49 PM PDT 24
Peak memory 266620 kb
Host smart-9070f95f-3e76-422c-93cc-ba7f7fedf39b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226205135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.2226205135
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.1596599960
Short name T1
Test name
Test status
Simulation time 41816629881 ps
CPU time 2853.82 seconds
Started Apr 28 04:18:15 PM PDT 24
Finished Apr 28 05:05:50 PM PDT 24
Peak memory 287196 kb
Host smart-94e6122f-dbe0-4a70-88d0-38fd659e658a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596599960 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.1596599960
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.3901064026
Short name T290
Test name
Test status
Simulation time 15469037721 ps
CPU time 1353 seconds
Started Apr 28 04:18:40 PM PDT 24
Finished Apr 28 04:41:13 PM PDT 24
Peak memory 284760 kb
Host smart-d43ca8d2-3189-4a27-a4bc-4c3f148794d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901064026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.3901064026
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.4205594489
Short name T21
Test name
Test status
Simulation time 9637624684 ps
CPU time 311.05 seconds
Started Apr 28 04:18:23 PM PDT 24
Finished Apr 28 04:23:34 PM PDT 24
Peak memory 250844 kb
Host smart-ac3dbb7e-025d-48a2-b7e6-0c14c8d1a1d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42055
94489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.4205594489
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.1876777100
Short name T590
Test name
Test status
Simulation time 328199283 ps
CPU time 31.07 seconds
Started Apr 28 04:18:26 PM PDT 24
Finished Apr 28 04:18:58 PM PDT 24
Peak memory 255844 kb
Host smart-ba2e94db-883d-4ec8-aa53-6b5db24aa779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18767
77100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.1876777100
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.2511179747
Short name T602
Test name
Test status
Simulation time 33254206030 ps
CPU time 1999.69 seconds
Started Apr 28 04:18:32 PM PDT 24
Finished Apr 28 04:51:52 PM PDT 24
Peak memory 271284 kb
Host smart-bb252fb7-58fa-4a88-9f54-0339c8e3c2f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511179747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.2511179747
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.2081771811
Short name T670
Test name
Test status
Simulation time 52361811661 ps
CPU time 534.08 seconds
Started Apr 28 04:18:32 PM PDT 24
Finished Apr 28 04:27:26 PM PDT 24
Peak memory 247776 kb
Host smart-412e283e-8e6e-4529-9e39-4064ae823709
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081771811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.2081771811
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.3460528101
Short name T81
Test name
Test status
Simulation time 746656987 ps
CPU time 9.22 seconds
Started Apr 28 04:18:18 PM PDT 24
Finished Apr 28 04:18:27 PM PDT 24
Peak memory 252940 kb
Host smart-bc6c65a9-06a5-42d7-9a31-37b898a0f3f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34605
28101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.3460528101
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.441730182
Short name T624
Test name
Test status
Simulation time 506804454 ps
CPU time 62.12 seconds
Started Apr 28 04:18:20 PM PDT 24
Finished Apr 28 04:19:22 PM PDT 24
Peak memory 256704 kb
Host smart-37419dcb-1cb1-48ea-8050-a96dfb0bbb6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44173
0182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.441730182
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.85030565
Short name T462
Test name
Test status
Simulation time 171537428 ps
CPU time 30.01 seconds
Started Apr 28 04:18:43 PM PDT 24
Finished Apr 28 04:19:14 PM PDT 24
Peak memory 248732 kb
Host smart-473aa9d8-ed6c-4c07-b1a1-ec642cd18bcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85030
565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.85030565
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.2085388364
Short name T74
Test name
Test status
Simulation time 235148812 ps
CPU time 15.96 seconds
Started Apr 28 04:18:19 PM PDT 24
Finished Apr 28 04:18:35 PM PDT 24
Peak memory 248696 kb
Host smart-df096143-45ac-4507-bd0d-31a54a5e186a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20853
88364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.2085388364
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.1771747073
Short name T538
Test name
Test status
Simulation time 7948440776 ps
CPU time 201.39 seconds
Started Apr 28 04:18:33 PM PDT 24
Finished Apr 28 04:21:55 PM PDT 24
Peak memory 256932 kb
Host smart-b2fdcd81-42db-450d-aa6b-b9caab4cc56b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771747073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.1771747073
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.1429364483
Short name T67
Test name
Test status
Simulation time 9855738941 ps
CPU time 1235.58 seconds
Started Apr 28 04:18:34 PM PDT 24
Finished Apr 28 04:39:09 PM PDT 24
Peak memory 281580 kb
Host smart-4ad4055d-4481-4bdb-8071-db7c563ca127
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429364483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.1429364483
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.3706088610
Short name T22
Test name
Test status
Simulation time 13181180801 ps
CPU time 236.47 seconds
Started Apr 28 04:18:36 PM PDT 24
Finished Apr 28 04:22:32 PM PDT 24
Peak memory 256968 kb
Host smart-382d8db7-83eb-4663-a2c5-9b5d1a21bf74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37060
88610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.3706088610
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.1868117004
Short name T654
Test name
Test status
Simulation time 574222021 ps
CPU time 13.35 seconds
Started Apr 28 04:18:39 PM PDT 24
Finished Apr 28 04:18:53 PM PDT 24
Peak memory 252976 kb
Host smart-de8168f6-8401-455c-b28c-848f90ffbcf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18681
17004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.1868117004
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.359607243
Short name T339
Test name
Test status
Simulation time 40925156097 ps
CPU time 1672.69 seconds
Started Apr 28 04:18:40 PM PDT 24
Finished Apr 28 04:46:33 PM PDT 24
Peak memory 288872 kb
Host smart-c4f8ad68-762b-460a-8691-3c8d455cd712
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359607243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.359607243
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.1262357196
Short name T631
Test name
Test status
Simulation time 81514169711 ps
CPU time 2026.38 seconds
Started Apr 28 04:18:45 PM PDT 24
Finished Apr 28 04:52:31 PM PDT 24
Peak memory 282592 kb
Host smart-d25e3362-ed1d-46f6-942f-0772869337a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262357196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.1262357196
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.396165696
Short name T328
Test name
Test status
Simulation time 5901758451 ps
CPU time 132.15 seconds
Started Apr 28 04:18:40 PM PDT 24
Finished Apr 28 04:20:52 PM PDT 24
Peak memory 248164 kb
Host smart-7ed2c2c9-fa8e-4e3b-861b-3c0abb827975
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396165696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.396165696
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.3381322402
Short name T224
Test name
Test status
Simulation time 476462492 ps
CPU time 5.6 seconds
Started Apr 28 04:18:36 PM PDT 24
Finished Apr 28 04:18:42 PM PDT 24
Peak memory 240528 kb
Host smart-9fc55748-1e20-4e77-8d60-f334e6760890
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33813
22402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.3381322402
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.2458588377
Short name T412
Test name
Test status
Simulation time 538244522 ps
CPU time 30.25 seconds
Started Apr 28 04:18:39 PM PDT 24
Finished Apr 28 04:19:10 PM PDT 24
Peak memory 255488 kb
Host smart-03832f3c-b29a-4ba7-9fbb-a1d2cfd93d14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24585
88377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.2458588377
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.1575871857
Short name T68
Test name
Test status
Simulation time 1101018374 ps
CPU time 50.52 seconds
Started Apr 28 04:18:36 PM PDT 24
Finished Apr 28 04:19:26 PM PDT 24
Peak memory 248724 kb
Host smart-c420749f-e525-4727-a718-45503488880c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15758
71857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.1575871857
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.3050070809
Short name T568
Test name
Test status
Simulation time 149471051 ps
CPU time 5.74 seconds
Started Apr 28 04:18:34 PM PDT 24
Finished Apr 28 04:18:40 PM PDT 24
Peak memory 248736 kb
Host smart-91c7c3ba-2cfb-4571-b778-19bc00cbe6e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30500
70809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.3050070809
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.1687623748
Short name T66
Test name
Test status
Simulation time 156520486658 ps
CPU time 1158.66 seconds
Started Apr 28 04:18:46 PM PDT 24
Finished Apr 28 04:38:05 PM PDT 24
Peak memory 281692 kb
Host smart-8e3bf3aa-2386-45f4-8255-759566b3a9f8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687623748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.1687623748
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.4061834023
Short name T516
Test name
Test status
Simulation time 465801881313 ps
CPU time 3423.91 seconds
Started Apr 28 04:18:51 PM PDT 24
Finished Apr 28 05:15:56 PM PDT 24
Peak memory 288936 kb
Host smart-4c7f8cb0-b1a0-4725-aed0-4146b1c3adc4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061834023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.4061834023
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.2952512371
Short name T402
Test name
Test status
Simulation time 4692753873 ps
CPU time 199.84 seconds
Started Apr 28 04:18:46 PM PDT 24
Finished Apr 28 04:22:06 PM PDT 24
Peak memory 256964 kb
Host smart-0536fadb-d0d2-45d2-8962-ee7d575c0891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29525
12371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.2952512371
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.941461100
Short name T558
Test name
Test status
Simulation time 1251066291 ps
CPU time 32.84 seconds
Started Apr 28 04:18:47 PM PDT 24
Finished Apr 28 04:19:20 PM PDT 24
Peak memory 248708 kb
Host smart-2668a340-e03a-433d-8001-1fc36265d4dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94146
1100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.941461100
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.1773750246
Short name T366
Test name
Test status
Simulation time 42613282122 ps
CPU time 960.77 seconds
Started Apr 28 04:18:55 PM PDT 24
Finished Apr 28 04:34:56 PM PDT 24
Peak memory 273364 kb
Host smart-8e0a1a77-a94d-40e7-b539-a85537df444c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773750246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.1773750246
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.632609568
Short name T321
Test name
Test status
Simulation time 4614260324 ps
CPU time 203.33 seconds
Started Apr 28 04:18:50 PM PDT 24
Finished Apr 28 04:22:14 PM PDT 24
Peak memory 248108 kb
Host smart-005833b3-5d02-4ec0-9823-3b913d8f4399
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632609568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.632609568
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.530304370
Short name T223
Test name
Test status
Simulation time 1841351697 ps
CPU time 36.34 seconds
Started Apr 28 04:18:47 PM PDT 24
Finished Apr 28 04:19:24 PM PDT 24
Peak memory 248672 kb
Host smart-9b619672-2218-4cce-91c8-97749859102d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53030
4370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.530304370
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.3081035755
Short name T7
Test name
Test status
Simulation time 2182405613 ps
CPU time 67.61 seconds
Started Apr 28 04:18:47 PM PDT 24
Finished Apr 28 04:19:55 PM PDT 24
Peak memory 255932 kb
Host smart-53457b8b-f008-4571-8c46-5bccb012750e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30810
35755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.3081035755
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.1310652104
Short name T607
Test name
Test status
Simulation time 135169287 ps
CPU time 10.16 seconds
Started Apr 28 04:18:47 PM PDT 24
Finished Apr 28 04:18:58 PM PDT 24
Peak memory 248776 kb
Host smart-81b00236-0112-4a01-a96c-0ae0d0bc812f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13106
52104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.1310652104
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.867275991
Short name T537
Test name
Test status
Simulation time 151720903 ps
CPU time 12.15 seconds
Started Apr 28 04:18:43 PM PDT 24
Finished Apr 28 04:18:55 PM PDT 24
Peak memory 248728 kb
Host smart-4975d8b4-52d8-4793-8150-6ad26850873f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86727
5991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.867275991
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.2943458317
Short name T688
Test name
Test status
Simulation time 28006139339 ps
CPU time 1752.62 seconds
Started Apr 28 04:19:15 PM PDT 24
Finished Apr 28 04:48:28 PM PDT 24
Peak memory 273356 kb
Host smart-69df1607-53ea-4ec8-8a85-a60e4db1ed5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943458317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.2943458317
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.1610858546
Short name T591
Test name
Test status
Simulation time 2881044309 ps
CPU time 50.75 seconds
Started Apr 28 04:19:06 PM PDT 24
Finished Apr 28 04:19:57 PM PDT 24
Peak memory 256000 kb
Host smart-ec44c6ef-a557-44d5-a9fb-f1b27cdbf896
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16108
58546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.1610858546
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.621357471
Short name T313
Test name
Test status
Simulation time 150659013189 ps
CPU time 2246.16 seconds
Started Apr 28 04:19:10 PM PDT 24
Finished Apr 28 04:56:37 PM PDT 24
Peak memory 273268 kb
Host smart-e92bd065-74e6-44b4-b996-7685b06c3e57
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621357471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.621357471
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.1238212808
Short name T124
Test name
Test status
Simulation time 55383036102 ps
CPU time 1161.97 seconds
Started Apr 28 04:19:07 PM PDT 24
Finished Apr 28 04:38:30 PM PDT 24
Peak memory 271344 kb
Host smart-baf70aa1-1d71-4789-b07d-676dbda6787f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238212808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.1238212808
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.2451090943
Short name T302
Test name
Test status
Simulation time 13614082680 ps
CPU time 584.84 seconds
Started Apr 28 04:19:13 PM PDT 24
Finished Apr 28 04:28:58 PM PDT 24
Peak memory 247172 kb
Host smart-02d54ade-6cfd-4497-8f76-112b6a88ec7c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451090943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.2451090943
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.1857447365
Short name T701
Test name
Test status
Simulation time 736141244 ps
CPU time 26.31 seconds
Started Apr 28 04:19:03 PM PDT 24
Finished Apr 28 04:19:30 PM PDT 24
Peak memory 255884 kb
Host smart-47bc7e2f-4d30-4c80-80bc-c7dea14ad8fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18574
47365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.1857447365
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.1365204167
Short name T576
Test name
Test status
Simulation time 6456202233 ps
CPU time 28.39 seconds
Started Apr 28 04:19:05 PM PDT 24
Finished Apr 28 04:19:34 PM PDT 24
Peak memory 248760 kb
Host smart-daeaae61-f6d3-407d-acdc-830da6c1f5e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13652
04167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.1365204167
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.1650199675
Short name T646
Test name
Test status
Simulation time 411694549 ps
CPU time 23.53 seconds
Started Apr 28 04:19:18 PM PDT 24
Finished Apr 28 04:19:42 PM PDT 24
Peak memory 256496 kb
Host smart-666f703d-7db6-48b2-a793-16139912f8a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16501
99675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.1650199675
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.2122809792
Short name T642
Test name
Test status
Simulation time 4302142807 ps
CPU time 273.96 seconds
Started Apr 28 04:19:21 PM PDT 24
Finished Apr 28 04:23:56 PM PDT 24
Peak memory 256956 kb
Host smart-a717c700-d389-405d-bb81-4b28322ac426
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122809792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.2122809792
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.1767007144
Short name T245
Test name
Test status
Simulation time 61614900348 ps
CPU time 4066.63 seconds
Started Apr 28 04:19:13 PM PDT 24
Finished Apr 28 05:27:00 PM PDT 24
Peak memory 298108 kb
Host smart-911984ec-0f21-4075-b3d0-92cac36c916e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767007144 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.1767007144
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.185887940
Short name T502
Test name
Test status
Simulation time 19837947741 ps
CPU time 1821.35 seconds
Started Apr 28 04:19:24 PM PDT 24
Finished Apr 28 04:49:46 PM PDT 24
Peak memory 288732 kb
Host smart-f57ede23-2a31-4109-a553-6b2bc49f358f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185887940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.185887940
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.1502311909
Short name T588
Test name
Test status
Simulation time 304816569 ps
CPU time 20.3 seconds
Started Apr 28 04:19:27 PM PDT 24
Finished Apr 28 04:19:47 PM PDT 24
Peak memory 254544 kb
Host smart-22392a79-4443-4527-b2be-9967bfa941de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15023
11909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.1502311909
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.2005216410
Short name T655
Test name
Test status
Simulation time 210318850 ps
CPU time 16.42 seconds
Started Apr 28 04:19:20 PM PDT 24
Finished Apr 28 04:19:37 PM PDT 24
Peak memory 252920 kb
Host smart-ccd5e949-2e11-4a0d-b8d0-2a0c5ee1a03f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20052
16410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.2005216410
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.3281757808
Short name T344
Test name
Test status
Simulation time 15276989631 ps
CPU time 1176.98 seconds
Started Apr 28 04:19:28 PM PDT 24
Finished Apr 28 04:39:06 PM PDT 24
Peak memory 269252 kb
Host smart-336012fc-9a12-4d84-83c3-15e1b7fec6c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281757808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.3281757808
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.3046430943
Short name T287
Test name
Test status
Simulation time 66196488994 ps
CPU time 3374.84 seconds
Started Apr 28 04:19:33 PM PDT 24
Finished Apr 28 05:15:49 PM PDT 24
Peak memory 289428 kb
Host smart-5e532f5d-94dd-4555-9dd2-45fd48bbb01f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046430943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.3046430943
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.2668451902
Short name T35
Test name
Test status
Simulation time 172525303336 ps
CPU time 349.48 seconds
Started Apr 28 04:19:22 PM PDT 24
Finished Apr 28 04:25:12 PM PDT 24
Peak memory 247884 kb
Host smart-6e6321ca-caeb-4ff6-9d92-e3c78caa3569
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668451902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.2668451902
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.1841317471
Short name T383
Test name
Test status
Simulation time 584823806 ps
CPU time 49.18 seconds
Started Apr 28 04:19:17 PM PDT 24
Finished Apr 28 04:20:07 PM PDT 24
Peak memory 256796 kb
Host smart-d58af097-3b34-46f4-b8ab-f9cf95fbab6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18413
17471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.1841317471
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.2865927178
Short name T520
Test name
Test status
Simulation time 486014820 ps
CPU time 31.64 seconds
Started Apr 28 04:19:21 PM PDT 24
Finished Apr 28 04:19:53 PM PDT 24
Peak memory 256116 kb
Host smart-dc5d5525-af9d-4ec0-91a2-97253ca1beaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28659
27178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.2865927178
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.179815102
Short name T230
Test name
Test status
Simulation time 3486544152 ps
CPU time 51.63 seconds
Started Apr 28 04:19:25 PM PDT 24
Finished Apr 28 04:20:17 PM PDT 24
Peak memory 248792 kb
Host smart-c38171a0-5d97-4fba-b141-0e1136225e73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17981
5102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.179815102
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.4080993753
Short name T528
Test name
Test status
Simulation time 1268103124 ps
CPU time 44.92 seconds
Started Apr 28 04:19:12 PM PDT 24
Finished Apr 28 04:19:57 PM PDT 24
Peak memory 255632 kb
Host smart-1c0e2851-e609-48b2-999e-6959f586da93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40809
93753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.4080993753
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.3361495495
Short name T372
Test name
Test status
Simulation time 580977271 ps
CPU time 40.9 seconds
Started Apr 28 04:19:27 PM PDT 24
Finished Apr 28 04:20:09 PM PDT 24
Peak memory 256428 kb
Host smart-9994fda3-8975-464e-9737-6c7665e7cdf7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361495495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.3361495495
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.2586585017
Short name T62
Test name
Test status
Simulation time 1707354363 ps
CPU time 105.7 seconds
Started Apr 28 04:19:34 PM PDT 24
Finished Apr 28 04:21:20 PM PDT 24
Peak memory 248908 kb
Host smart-e44b75ce-dfcf-44d2-9704-dcb5c64f80a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25865
85017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.2586585017
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.1029546430
Short name T262
Test name
Test status
Simulation time 1785853044 ps
CPU time 33.58 seconds
Started Apr 28 04:19:37 PM PDT 24
Finished Apr 28 04:20:11 PM PDT 24
Peak memory 248712 kb
Host smart-aa9501ed-2a35-43d7-9ab4-de67b32757b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10295
46430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.1029546430
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.4043064072
Short name T503
Test name
Test status
Simulation time 65806977515 ps
CPU time 1346.38 seconds
Started Apr 28 04:19:43 PM PDT 24
Finished Apr 28 04:42:10 PM PDT 24
Peak memory 281520 kb
Host smart-4075088f-cbd3-4d61-96b7-9d6d187eaecc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043064072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.4043064072
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.1474284708
Short name T690
Test name
Test status
Simulation time 144032889086 ps
CPU time 1489.21 seconds
Started Apr 28 04:19:42 PM PDT 24
Finished Apr 28 04:44:32 PM PDT 24
Peak memory 281556 kb
Host smart-f96c5696-09f8-4477-b17b-323db3ca1068
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474284708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.1474284708
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.2671528908
Short name T306
Test name
Test status
Simulation time 24990367229 ps
CPU time 550.59 seconds
Started Apr 28 04:19:42 PM PDT 24
Finished Apr 28 04:28:53 PM PDT 24
Peak memory 247876 kb
Host smart-468daeae-2a14-499b-b0a3-7728e735188a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671528908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.2671528908
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.1596348243
Short name T636
Test name
Test status
Simulation time 62123275 ps
CPU time 4.06 seconds
Started Apr 28 04:19:33 PM PDT 24
Finished Apr 28 04:19:38 PM PDT 24
Peak memory 240532 kb
Host smart-ea212e9e-d3f6-46ca-80c9-1bcb00bc8f77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15963
48243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.1596348243
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.3622569994
Short name T8
Test name
Test status
Simulation time 2990016832 ps
CPU time 51.67 seconds
Started Apr 28 04:19:47 PM PDT 24
Finished Apr 28 04:20:39 PM PDT 24
Peak memory 256976 kb
Host smart-8a5792b4-9649-498e-8f23-0b543301b62d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36225
69994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.3622569994
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.429822903
Short name T433
Test name
Test status
Simulation time 272636191 ps
CPU time 22.95 seconds
Started Apr 28 04:19:46 PM PDT 24
Finished Apr 28 04:20:09 PM PDT 24
Peak memory 254032 kb
Host smart-c8c9b602-c239-4734-bd85-c9c216220a2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42982
2903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.429822903
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.3791680021
Short name T702
Test name
Test status
Simulation time 275806618 ps
CPU time 33.64 seconds
Started Apr 28 04:19:32 PM PDT 24
Finished Apr 28 04:20:06 PM PDT 24
Peak memory 255892 kb
Host smart-85e1ebf3-cc11-49c8-9043-3be2babb004a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37916
80021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.3791680021
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.1007528150
Short name T691
Test name
Test status
Simulation time 160632823217 ps
CPU time 2555.12 seconds
Started Apr 28 04:19:43 PM PDT 24
Finished Apr 28 05:02:19 PM PDT 24
Peak memory 289552 kb
Host smart-28c2bdb2-14e0-4673-bd54-98f444ff8c32
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007528150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.1007528150
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.3900061686
Short name T378
Test name
Test status
Simulation time 150785739287 ps
CPU time 2491.4 seconds
Started Apr 28 04:19:56 PM PDT 24
Finished Apr 28 05:01:28 PM PDT 24
Peak memory 285272 kb
Host smart-a7c78f51-21f6-4536-bc66-525381e8cfe8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900061686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.3900061686
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.3477530646
Short name T10
Test name
Test status
Simulation time 2573950120 ps
CPU time 49.25 seconds
Started Apr 28 04:19:57 PM PDT 24
Finished Apr 28 04:20:47 PM PDT 24
Peak memory 249068 kb
Host smart-2236c44c-e687-47f9-bede-8697a4f1689a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34775
30646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.3477530646
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.1911209573
Short name T553
Test name
Test status
Simulation time 1503466758 ps
CPU time 28.52 seconds
Started Apr 28 04:19:54 PM PDT 24
Finished Apr 28 04:20:23 PM PDT 24
Peak memory 255604 kb
Host smart-17e34664-5352-4e1d-89f4-ccc4cd78ede2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19112
09573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.1911209573
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.1227330650
Short name T345
Test name
Test status
Simulation time 13606845583 ps
CPU time 1184.65 seconds
Started Apr 28 04:20:06 PM PDT 24
Finished Apr 28 04:39:51 PM PDT 24
Peak memory 271332 kb
Host smart-b36ce5d4-e85e-43fd-a4c4-07a955107721
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227330650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.1227330650
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.306531522
Short name T468
Test name
Test status
Simulation time 133142723551 ps
CPU time 1427.12 seconds
Started Apr 28 04:19:59 PM PDT 24
Finished Apr 28 04:43:47 PM PDT 24
Peak memory 273100 kb
Host smart-299e3854-d15d-45c0-9dca-ad739b1bc571
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306531522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.306531522
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.1141310480
Short name T319
Test name
Test status
Simulation time 11460738197 ps
CPU time 124.51 seconds
Started Apr 28 04:19:58 PM PDT 24
Finished Apr 28 04:22:03 PM PDT 24
Peak memory 247816 kb
Host smart-aa572181-4a96-4af4-9d00-4368505b1995
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141310480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.1141310480
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.3527044324
Short name T241
Test name
Test status
Simulation time 248765959 ps
CPU time 12.05 seconds
Started Apr 28 04:19:49 PM PDT 24
Finished Apr 28 04:20:01 PM PDT 24
Peak memory 248636 kb
Host smart-c6b2e51a-5e06-46a5-bc86-0692f1f6729e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35270
44324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.3527044324
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.1044481163
Short name T548
Test name
Test status
Simulation time 2264932039 ps
CPU time 15.32 seconds
Started Apr 28 04:19:47 PM PDT 24
Finished Apr 28 04:20:03 PM PDT 24
Peak memory 248792 kb
Host smart-3b80a592-07eb-4a76-b77e-1838729bcfd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10444
81163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.1044481163
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.2244842790
Short name T264
Test name
Test status
Simulation time 186852159 ps
CPU time 12.85 seconds
Started Apr 28 04:19:57 PM PDT 24
Finished Apr 28 04:20:10 PM PDT 24
Peak memory 247424 kb
Host smart-1f8d4f60-1974-4d0f-9769-57bb20f419bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22448
42790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.2244842790
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.3355386459
Short name T571
Test name
Test status
Simulation time 1549424089 ps
CPU time 38.05 seconds
Started Apr 28 04:19:43 PM PDT 24
Finished Apr 28 04:20:21 PM PDT 24
Peak memory 248804 kb
Host smart-6069b907-c56d-4fc7-9205-ac7cd6bbe2c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33553
86459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.3355386459
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.1878009309
Short name T460
Test name
Test status
Simulation time 5994445534 ps
CPU time 107.02 seconds
Started Apr 28 04:20:04 PM PDT 24
Finished Apr 28 04:21:51 PM PDT 24
Peak memory 256848 kb
Host smart-35978d8a-81e8-421e-8c85-5906cd5a98a2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878009309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.1878009309
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.2976628777
Short name T512
Test name
Test status
Simulation time 72918389625 ps
CPU time 1785.96 seconds
Started Apr 28 04:20:09 PM PDT 24
Finished Apr 28 04:49:55 PM PDT 24
Peak memory 281564 kb
Host smart-38565b6b-dc73-444d-95c8-fa1aabcfdac2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976628777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.2976628777
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.3508165110
Short name T31
Test name
Test status
Simulation time 2751167977 ps
CPU time 143.6 seconds
Started Apr 28 04:20:12 PM PDT 24
Finished Apr 28 04:22:35 PM PDT 24
Peak memory 248756 kb
Host smart-23bbf443-16cd-432c-83cd-fe6aa6a3e3a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35081
65110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.3508165110
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.2500722324
Short name T123
Test name
Test status
Simulation time 1183669951 ps
CPU time 42.27 seconds
Started Apr 28 04:20:05 PM PDT 24
Finished Apr 28 04:20:47 PM PDT 24
Peak memory 256028 kb
Host smart-5f10d0f7-82dd-46d0-bff2-09460cf600f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25007
22324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.2500722324
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.1142948055
Short name T574
Test name
Test status
Simulation time 12785357418 ps
CPU time 1299.2 seconds
Started Apr 28 04:20:18 PM PDT 24
Finished Apr 28 04:41:58 PM PDT 24
Peak memory 288852 kb
Host smart-a6a28e30-63b2-44e1-94df-985fe5d7d8d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142948055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.1142948055
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.4230796945
Short name T229
Test name
Test status
Simulation time 111006170393 ps
CPU time 236.84 seconds
Started Apr 28 04:20:14 PM PDT 24
Finished Apr 28 04:24:11 PM PDT 24
Peak memory 247932 kb
Host smart-2c85c838-a045-4995-9a7f-aa38c9a4445f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230796945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.4230796945
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.378434274
Short name T80
Test name
Test status
Simulation time 332007947 ps
CPU time 37.2 seconds
Started Apr 28 04:20:04 PM PDT 24
Finished Apr 28 04:20:41 PM PDT 24
Peak memory 248800 kb
Host smart-f78ff536-7140-4616-ab4b-4a17f744547c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37843
4274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.378434274
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.231176741
Short name T601
Test name
Test status
Simulation time 1544398416 ps
CPU time 28.5 seconds
Started Apr 28 04:20:03 PM PDT 24
Finished Apr 28 04:20:32 PM PDT 24
Peak memory 248708 kb
Host smart-8f868e23-1d30-48bf-b1fc-3bcc277d5509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23117
6741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.231176741
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.227168307
Short name T266
Test name
Test status
Simulation time 3985302810 ps
CPU time 43.86 seconds
Started Apr 28 04:20:07 PM PDT 24
Finished Apr 28 04:20:51 PM PDT 24
Peak memory 248784 kb
Host smart-d772fd35-9311-4780-807f-e66e4ea7dfca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22716
8307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.227168307
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.1885655315
Short name T125
Test name
Test status
Simulation time 584202563 ps
CPU time 50.25 seconds
Started Apr 28 04:20:07 PM PDT 24
Finished Apr 28 04:20:57 PM PDT 24
Peak memory 256872 kb
Host smart-00538918-49f0-47c8-9234-81a5eff7d9e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18856
55315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.1885655315
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.2492407662
Short name T582
Test name
Test status
Simulation time 47433262348 ps
CPU time 1646.32 seconds
Started Apr 28 04:20:33 PM PDT 24
Finished Apr 28 04:47:59 PM PDT 24
Peak memory 281556 kb
Host smart-2cfa990a-69eb-4ec0-b4ce-fd02a70dd42f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492407662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.2492407662
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.3813652337
Short name T438
Test name
Test status
Simulation time 5135755234 ps
CPU time 168.25 seconds
Started Apr 28 04:20:25 PM PDT 24
Finished Apr 28 04:23:14 PM PDT 24
Peak memory 249896 kb
Host smart-f4c60de9-6204-4cac-9b41-082569db1b23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38136
52337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.3813652337
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.4162192756
Short name T191
Test name
Test status
Simulation time 609830924 ps
CPU time 41.33 seconds
Started Apr 28 04:20:27 PM PDT 24
Finished Apr 28 04:21:08 PM PDT 24
Peak memory 248708 kb
Host smart-17b1e042-4d52-4496-a7bd-df802236b428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41621
92756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.4162192756
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.580283437
Short name T335
Test name
Test status
Simulation time 17757359533 ps
CPU time 1503.73 seconds
Started Apr 28 04:20:34 PM PDT 24
Finished Apr 28 04:45:38 PM PDT 24
Peak memory 289256 kb
Host smart-afa9e7d1-a503-45a4-9afa-98def0a9cbc2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580283437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.580283437
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.2295753611
Short name T656
Test name
Test status
Simulation time 451777069880 ps
CPU time 1880.45 seconds
Started Apr 28 04:20:35 PM PDT 24
Finished Apr 28 04:51:55 PM PDT 24
Peak memory 273080 kb
Host smart-a2f574a2-cdc7-4389-b3f1-adb3f5a98b81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295753611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.2295753611
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.2880193645
Short name T685
Test name
Test status
Simulation time 26993236984 ps
CPU time 526.2 seconds
Started Apr 28 04:20:30 PM PDT 24
Finished Apr 28 04:29:17 PM PDT 24
Peak memory 247800 kb
Host smart-01dbc3c4-ef9e-4c92-a58f-fca6976d52dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880193645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.2880193645
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.1447255572
Short name T572
Test name
Test status
Simulation time 1193140929 ps
CPU time 41.04 seconds
Started Apr 28 04:20:21 PM PDT 24
Finished Apr 28 04:21:02 PM PDT 24
Peak memory 255864 kb
Host smart-4078a7d8-63ae-4084-904a-9910bf6ed168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14472
55572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.1447255572
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.2113929545
Short name T620
Test name
Test status
Simulation time 877856171 ps
CPU time 67.33 seconds
Started Apr 28 04:20:26 PM PDT 24
Finished Apr 28 04:21:34 PM PDT 24
Peak memory 248680 kb
Host smart-10d3f035-42ae-4d11-b685-e981494a2a32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21139
29545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.2113929545
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.1953712156
Short name T536
Test name
Test status
Simulation time 630953402 ps
CPU time 43.73 seconds
Started Apr 28 04:20:30 PM PDT 24
Finished Apr 28 04:21:14 PM PDT 24
Peak memory 255892 kb
Host smart-482924cd-0768-465e-96a5-cff94b4da511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19537
12156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.1953712156
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.940966651
Short name T482
Test name
Test status
Simulation time 36229831 ps
CPU time 5.66 seconds
Started Apr 28 04:20:37 PM PDT 24
Finished Apr 28 04:20:43 PM PDT 24
Peak memory 248708 kb
Host smart-9dcfb99e-11f0-479d-b1cb-490877c1dc5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94096
6651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.940966651
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.3719852170
Short name T405
Test name
Test status
Simulation time 18563059132 ps
CPU time 92.74 seconds
Started Apr 28 04:20:38 PM PDT 24
Finished Apr 28 04:22:11 PM PDT 24
Peak memory 256912 kb
Host smart-fe4e5b67-859c-4ff1-a71e-14caeac5efbc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719852170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.3719852170
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.4188522282
Short name T104
Test name
Test status
Simulation time 80715266561 ps
CPU time 2737.79 seconds
Started Apr 28 04:20:42 PM PDT 24
Finished Apr 28 05:06:20 PM PDT 24
Peak memory 298176 kb
Host smart-87cfe948-54b7-491e-8ffc-85c0610e1376
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188522282 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.4188522282
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.4252341657
Short name T202
Test name
Test status
Simulation time 51497275 ps
CPU time 3.59 seconds
Started Apr 28 04:11:18 PM PDT 24
Finished Apr 28 04:11:22 PM PDT 24
Peak memory 248876 kb
Host smart-07fd4340-3ed3-4e52-a531-58d67f111613
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4252341657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.4252341657
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.2807153487
Short name T430
Test name
Test status
Simulation time 40902589105 ps
CPU time 1604.66 seconds
Started Apr 28 04:10:57 PM PDT 24
Finished Apr 28 04:37:43 PM PDT 24
Peak memory 267572 kb
Host smart-53e547a0-363d-4c17-bc7d-3bf3abe596b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807153487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.2807153487
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.2087975604
Short name T592
Test name
Test status
Simulation time 500616321 ps
CPU time 23.71 seconds
Started Apr 28 04:11:12 PM PDT 24
Finished Apr 28 04:11:36 PM PDT 24
Peak memory 240468 kb
Host smart-7870666e-c7b2-4243-9d17-ca688c821a2a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2087975604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.2087975604
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.2962569667
Short name T669
Test name
Test status
Simulation time 877263570 ps
CPU time 31.75 seconds
Started Apr 28 04:10:46 PM PDT 24
Finished Apr 28 04:11:18 PM PDT 24
Peak memory 248812 kb
Host smart-897ce827-e0a5-4e1a-9652-4d495457b23e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29625
69667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.2962569667
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.2510059187
Short name T489
Test name
Test status
Simulation time 82398292 ps
CPU time 4.03 seconds
Started Apr 28 04:10:48 PM PDT 24
Finished Apr 28 04:10:52 PM PDT 24
Peak memory 240536 kb
Host smart-ad897431-d97b-49f2-be55-0788606ba485
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25100
59187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.2510059187
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.3085642300
Short name T12
Test name
Test status
Simulation time 13606558504 ps
CPU time 1244.84 seconds
Started Apr 28 04:11:00 PM PDT 24
Finished Apr 28 04:31:45 PM PDT 24
Peak memory 271336 kb
Host smart-e622b6a1-4265-46ef-8aa1-30bbbebe8df2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085642300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.3085642300
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.1572239800
Short name T609
Test name
Test status
Simulation time 61753353480 ps
CPU time 2010.86 seconds
Started Apr 28 04:11:07 PM PDT 24
Finished Apr 28 04:44:38 PM PDT 24
Peak memory 273336 kb
Host smart-819ea0c3-4ddf-48a5-8b6c-568bffc6291a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572239800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.1572239800
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.336504795
Short name T324
Test name
Test status
Simulation time 12797920802 ps
CPU time 124.17 seconds
Started Apr 28 04:10:57 PM PDT 24
Finished Apr 28 04:13:02 PM PDT 24
Peak memory 247076 kb
Host smart-94da912d-27af-40b6-94b7-cb18b64ed5a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336504795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.336504795
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.1281979578
Short name T569
Test name
Test status
Simulation time 210109834 ps
CPU time 20.27 seconds
Started Apr 28 04:10:38 PM PDT 24
Finished Apr 28 04:10:58 PM PDT 24
Peak memory 248708 kb
Host smart-372c5c38-1e7c-46b1-bdac-9860f16ad963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12819
79578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.1281979578
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.2123774707
Short name T658
Test name
Test status
Simulation time 290855406 ps
CPU time 28.95 seconds
Started Apr 28 04:10:42 PM PDT 24
Finished Apr 28 04:11:11 PM PDT 24
Peak memory 249148 kb
Host smart-7ad57870-a741-4342-8d63-575bcb73eec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21237
74707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.2123774707
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.1168060050
Short name T556
Test name
Test status
Simulation time 2064007763 ps
CPU time 36.47 seconds
Started Apr 28 04:10:39 PM PDT 24
Finished Apr 28 04:11:15 PM PDT 24
Peak memory 248712 kb
Host smart-2ca6f4f8-40b4-4bd6-abee-6a0d92ceee7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11680
60050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.1168060050
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.1693072823
Short name T75
Test name
Test status
Simulation time 3665727146 ps
CPU time 140.99 seconds
Started Apr 28 04:11:19 PM PDT 24
Finished Apr 28 04:13:40 PM PDT 24
Peak memory 256956 kb
Host smart-c00ebd01-3061-411d-b29c-9a3fa2dae635
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693072823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.1693072823
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.670808325
Short name T297
Test name
Test status
Simulation time 10900572266 ps
CPU time 1043.97 seconds
Started Apr 28 04:20:42 PM PDT 24
Finished Apr 28 04:38:07 PM PDT 24
Peak memory 271388 kb
Host smart-df52b490-3f11-4373-97a8-b3000821236f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670808325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.670808325
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.1777028662
Short name T18
Test name
Test status
Simulation time 10658669851 ps
CPU time 116.69 seconds
Started Apr 28 04:20:42 PM PDT 24
Finished Apr 28 04:22:39 PM PDT 24
Peak memory 256836 kb
Host smart-e33d8bf9-1c08-4064-9367-7eb5e31395e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17770
28662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1777028662
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.218851975
Short name T398
Test name
Test status
Simulation time 2018075079 ps
CPU time 36.93 seconds
Started Apr 28 04:20:43 PM PDT 24
Finished Apr 28 04:21:20 PM PDT 24
Peak memory 255864 kb
Host smart-26a0fd5f-2979-4a0e-8b05-09c18bfc7ab7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21885
1975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.218851975
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.3889897574
Short name T330
Test name
Test status
Simulation time 40311972320 ps
CPU time 2017.92 seconds
Started Apr 28 04:20:47 PM PDT 24
Finished Apr 28 04:54:25 PM PDT 24
Peak memory 268276 kb
Host smart-96ce8625-beaa-42db-9c43-2bf11c501ecb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889897574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.3889897574
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.968086680
Short name T98
Test name
Test status
Simulation time 386726199929 ps
CPU time 1878.51 seconds
Started Apr 28 04:20:58 PM PDT 24
Finished Apr 28 04:52:17 PM PDT 24
Peak memory 285424 kb
Host smart-adec2c9f-5784-4e4f-b5b2-8132cb619d85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968086680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.968086680
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.16607687
Short name T681
Test name
Test status
Simulation time 9007139164 ps
CPU time 93.42 seconds
Started Apr 28 04:20:48 PM PDT 24
Finished Apr 28 04:22:21 PM PDT 24
Peak memory 247932 kb
Host smart-78b0c1a9-c8db-4d2d-8118-22b02b9b0a0c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16607687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.16607687
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.2571497000
Short name T612
Test name
Test status
Simulation time 1639829439 ps
CPU time 48.17 seconds
Started Apr 28 04:20:39 PM PDT 24
Finished Apr 28 04:21:28 PM PDT 24
Peak memory 248708 kb
Host smart-053bb0f6-6f17-496e-9869-4190d76149db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25714
97000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.2571497000
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.1136440932
Short name T575
Test name
Test status
Simulation time 5086229749 ps
CPU time 56.83 seconds
Started Apr 28 04:20:42 PM PDT 24
Finished Apr 28 04:21:40 PM PDT 24
Peak memory 256184 kb
Host smart-5afd7144-2b5f-4f8f-ba89-e6cd7831ca2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11364
40932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.1136440932
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.1658608175
Short name T374
Test name
Test status
Simulation time 102619067 ps
CPU time 13.32 seconds
Started Apr 28 04:20:42 PM PDT 24
Finished Apr 28 04:20:56 PM PDT 24
Peak memory 248736 kb
Host smart-00be7d3b-dc4a-40ff-b77e-a0a48a672bee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16586
08175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.1658608175
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.1099212116
Short name T495
Test name
Test status
Simulation time 143936764 ps
CPU time 16.05 seconds
Started Apr 28 04:20:38 PM PDT 24
Finished Apr 28 04:20:55 PM PDT 24
Peak memory 256020 kb
Host smart-a5cb1cce-f455-45c5-8355-1d2829b8cf7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10992
12116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.1099212116
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.172904512
Short name T114
Test name
Test status
Simulation time 13408254239 ps
CPU time 656.4 seconds
Started Apr 28 04:20:52 PM PDT 24
Finished Apr 28 04:31:49 PM PDT 24
Peak memory 272632 kb
Host smart-b4c44834-9200-4ea7-9ef0-9085bf11263f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172904512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_han
dler_stress_all.172904512
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.1509579356
Short name T454
Test name
Test status
Simulation time 50124011939 ps
CPU time 3051.01 seconds
Started Apr 28 04:20:53 PM PDT 24
Finished Apr 28 05:11:45 PM PDT 24
Peak memory 305444 kb
Host smart-79f78388-bfc2-4491-b22f-4a85157d960b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509579356 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.1509579356
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.851564688
Short name T457
Test name
Test status
Simulation time 197474039379 ps
CPU time 2735.01 seconds
Started Apr 28 04:21:04 PM PDT 24
Finished Apr 28 05:06:39 PM PDT 24
Peak memory 287460 kb
Host smart-3a74f9e8-c203-407c-807c-909cc13bb3a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851564688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.851564688
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.600325032
Short name T390
Test name
Test status
Simulation time 3697813748 ps
CPU time 219.46 seconds
Started Apr 28 04:21:01 PM PDT 24
Finished Apr 28 04:24:41 PM PDT 24
Peak memory 256940 kb
Host smart-c2218dd8-ef02-438c-8987-a7c8316c8f9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60032
5032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.600325032
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.2895314733
Short name T73
Test name
Test status
Simulation time 1164854236 ps
CPU time 20.63 seconds
Started Apr 28 04:21:02 PM PDT 24
Finished Apr 28 04:21:23 PM PDT 24
Peak memory 249232 kb
Host smart-335da305-468c-4c2a-98d2-91e2b70e15e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28953
14733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.2895314733
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.2902145496
Short name T465
Test name
Test status
Simulation time 402051046123 ps
CPU time 1765.06 seconds
Started Apr 28 04:21:04 PM PDT 24
Finished Apr 28 04:50:29 PM PDT 24
Peak memory 269224 kb
Host smart-22a45388-4c50-47e8-ae90-3c7ddf5be87d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902145496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.2902145496
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.3410688027
Short name T450
Test name
Test status
Simulation time 40172636826 ps
CPU time 1143.9 seconds
Started Apr 28 04:21:06 PM PDT 24
Finished Apr 28 04:40:11 PM PDT 24
Peak memory 286720 kb
Host smart-381234d9-03f1-4483-944d-8e4410709c3f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410688027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.3410688027
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.28766095
Short name T415
Test name
Test status
Simulation time 521400700 ps
CPU time 15 seconds
Started Apr 28 04:20:56 PM PDT 24
Finished Apr 28 04:21:11 PM PDT 24
Peak memory 253856 kb
Host smart-cafd7254-4aad-42c5-ba32-a1d75d78dc10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28766
095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.28766095
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.1853857620
Short name T479
Test name
Test status
Simulation time 300444187 ps
CPU time 23.83 seconds
Started Apr 28 04:20:59 PM PDT 24
Finished Apr 28 04:21:23 PM PDT 24
Peak memory 255860 kb
Host smart-f9453914-cbb7-4e68-8a72-3fb3ee79de4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18538
57620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.1853857620
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.1002437327
Short name T56
Test name
Test status
Simulation time 695494537 ps
CPU time 31.99 seconds
Started Apr 28 04:20:58 PM PDT 24
Finished Apr 28 04:21:31 PM PDT 24
Peak memory 248676 kb
Host smart-25b57fa4-5fc9-49a0-8776-c62b0ffb3ae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10024
37327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.1002437327
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.2437195795
Short name T376
Test name
Test status
Simulation time 306407593 ps
CPU time 34.7 seconds
Started Apr 28 04:20:55 PM PDT 24
Finished Apr 28 04:21:29 PM PDT 24
Peak memory 248684 kb
Host smart-c747bb1a-27fa-4436-8eda-45a39d631d76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24371
95795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.2437195795
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.982848006
Short name T661
Test name
Test status
Simulation time 10720057958 ps
CPU time 1163.12 seconds
Started Apr 28 04:21:19 PM PDT 24
Finished Apr 28 04:40:43 PM PDT 24
Peak memory 273416 kb
Host smart-5ecdfe98-2ebe-4d62-a22a-73c5b7eba94b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982848006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.982848006
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.512567160
Short name T240
Test name
Test status
Simulation time 11097803065 ps
CPU time 125.85 seconds
Started Apr 28 04:21:13 PM PDT 24
Finished Apr 28 04:23:19 PM PDT 24
Peak memory 256904 kb
Host smart-e84fcf92-29f7-48df-8ede-7788a413c281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51256
7160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.512567160
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.1336672529
Short name T487
Test name
Test status
Simulation time 174280231 ps
CPU time 8.39 seconds
Started Apr 28 04:21:13 PM PDT 24
Finished Apr 28 04:21:22 PM PDT 24
Peak memory 251048 kb
Host smart-e8a83608-3d73-4154-bccf-ed3b565fb430
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13366
72529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1336672529
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.2778426514
Short name T471
Test name
Test status
Simulation time 81500217072 ps
CPU time 2622.5 seconds
Started Apr 28 04:21:17 PM PDT 24
Finished Apr 28 05:05:00 PM PDT 24
Peak memory 288840 kb
Host smart-ecfa6c5f-8dd9-41b4-b8fb-d19ae5e6ab89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778426514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.2778426514
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.1544739213
Short name T562
Test name
Test status
Simulation time 9144416418 ps
CPU time 1123.58 seconds
Started Apr 28 04:21:26 PM PDT 24
Finished Apr 28 04:40:11 PM PDT 24
Peak memory 271548 kb
Host smart-4807cec4-4257-4bce-b795-85ba942b3b75
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544739213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.1544739213
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.3199852551
Short name T704
Test name
Test status
Simulation time 7231438489 ps
CPU time 302.82 seconds
Started Apr 28 04:21:17 PM PDT 24
Finished Apr 28 04:26:20 PM PDT 24
Peak memory 248092 kb
Host smart-809cec59-3714-4054-a717-3eeb85ae2f4b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199852551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.3199852551
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.1168064601
Short name T385
Test name
Test status
Simulation time 41853060 ps
CPU time 6.44 seconds
Started Apr 28 04:21:09 PM PDT 24
Finished Apr 28 04:21:16 PM PDT 24
Peak memory 248612 kb
Host smart-3d789b84-af4c-4461-9581-f89f352b0d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11680
64601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.1168064601
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.2103199804
Short name T106
Test name
Test status
Simulation time 2648925328 ps
CPU time 49.71 seconds
Started Apr 28 04:21:13 PM PDT 24
Finished Apr 28 04:22:03 PM PDT 24
Peak memory 256152 kb
Host smart-5484180f-f53a-42bd-9ce8-53cdfe62a1d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21031
99804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.2103199804
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.4064267024
Short name T91
Test name
Test status
Simulation time 261418025 ps
CPU time 30.6 seconds
Started Apr 28 04:21:17 PM PDT 24
Finished Apr 28 04:21:48 PM PDT 24
Peak memory 248724 kb
Host smart-726e4a2e-a143-4901-b26c-18224c00159f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40642
67024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.4064267024
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.3318318101
Short name T662
Test name
Test status
Simulation time 717576822 ps
CPU time 48.5 seconds
Started Apr 28 04:21:07 PM PDT 24
Finished Apr 28 04:21:55 PM PDT 24
Peak memory 249192 kb
Host smart-9577cddd-8fa0-4e88-821f-9da9b7d89aa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33183
18101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.3318318101
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.4235915635
Short name T251
Test name
Test status
Simulation time 247805447400 ps
CPU time 3675.16 seconds
Started Apr 28 04:21:22 PM PDT 24
Finished Apr 28 05:22:38 PM PDT 24
Peak memory 297940 kb
Host smart-f2a67ff9-9c11-4da5-9230-fe56bd068727
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235915635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.4235915635
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.2196670543
Short name T199
Test name
Test status
Simulation time 280726001979 ps
CPU time 5335.41 seconds
Started Apr 28 04:21:24 PM PDT 24
Finished Apr 28 05:50:20 PM PDT 24
Peak memory 338400 kb
Host smart-1340ee62-5eca-4952-b809-7979ccbabfaf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196670543 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.2196670543
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.2782226600
Short name T679
Test name
Test status
Simulation time 45769140823 ps
CPU time 1201.1 seconds
Started Apr 28 04:21:29 PM PDT 24
Finished Apr 28 04:41:30 PM PDT 24
Peak memory 289200 kb
Host smart-57cbf064-623e-472c-9b6a-aa6833a9d899
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782226600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.2782226600
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.727360688
Short name T447
Test name
Test status
Simulation time 13660938422 ps
CPU time 223.9 seconds
Started Apr 28 04:21:26 PM PDT 24
Finished Apr 28 04:25:11 PM PDT 24
Peak memory 256956 kb
Host smart-9a83b9b0-e7b7-40ff-92ed-edefb8dd5f5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72736
0688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.727360688
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.3165920737
Short name T467
Test name
Test status
Simulation time 311109564 ps
CPU time 26.05 seconds
Started Apr 28 04:21:26 PM PDT 24
Finished Apr 28 04:21:52 PM PDT 24
Peak memory 255172 kb
Host smart-5e317bb1-cdbe-40bb-b7aa-c8785e6f3eaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31659
20737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.3165920737
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.734016243
Short name T296
Test name
Test status
Simulation time 25363183159 ps
CPU time 1542.47 seconds
Started Apr 28 04:21:28 PM PDT 24
Finished Apr 28 04:47:11 PM PDT 24
Peak memory 265156 kb
Host smart-70bf57f6-99f5-4f2d-8bd0-60ef6f580c1e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734016243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.734016243
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.2321848622
Short name T645
Test name
Test status
Simulation time 29981071808 ps
CPU time 1969.14 seconds
Started Apr 28 04:21:29 PM PDT 24
Finished Apr 28 04:54:19 PM PDT 24
Peak memory 272908 kb
Host smart-7bd4fa98-50b3-4272-b5d4-67f7bd103549
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321848622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.2321848622
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.1637097857
Short name T640
Test name
Test status
Simulation time 12965352493 ps
CPU time 139.57 seconds
Started Apr 28 04:21:29 PM PDT 24
Finished Apr 28 04:23:49 PM PDT 24
Peak memory 254448 kb
Host smart-eaef3c87-4c56-454a-b4d9-87f3a073fa84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637097857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.1637097857
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.3489524002
Short name T275
Test name
Test status
Simulation time 255750800 ps
CPU time 20.74 seconds
Started Apr 28 04:21:24 PM PDT 24
Finished Apr 28 04:21:46 PM PDT 24
Peak memory 248676 kb
Host smart-8d8b5df3-bde5-4bee-b734-9e87dae82bb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34895
24002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.3489524002
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.3233649987
Short name T107
Test name
Test status
Simulation time 1161225740 ps
CPU time 25.11 seconds
Started Apr 28 04:21:26 PM PDT 24
Finished Apr 28 04:21:51 PM PDT 24
Peak memory 248704 kb
Host smart-d46bd715-5ef8-4d6a-bcc4-ca1468b9d594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32336
49987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.3233649987
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.252143176
Short name T567
Test name
Test status
Simulation time 242236720 ps
CPU time 18.24 seconds
Started Apr 28 04:21:30 PM PDT 24
Finished Apr 28 04:21:48 PM PDT 24
Peak memory 248708 kb
Host smart-90a970a5-c39c-4e21-b519-a653a129a8b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25214
3176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.252143176
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.229858355
Short name T511
Test name
Test status
Simulation time 1608439087 ps
CPU time 21.48 seconds
Started Apr 28 04:21:22 PM PDT 24
Finished Apr 28 04:21:44 PM PDT 24
Peak memory 248700 kb
Host smart-16c8918e-0612-4380-9f70-74c9bb439d5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22985
8355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.229858355
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.4290248791
Short name T120
Test name
Test status
Simulation time 129167924225 ps
CPU time 2055.27 seconds
Started Apr 28 04:21:41 PM PDT 24
Finished Apr 28 04:55:57 PM PDT 24
Peak memory 282392 kb
Host smart-15a0148f-877c-405f-8d84-1b5ac5444079
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290248791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.4290248791
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.936734099
Short name T429
Test name
Test status
Simulation time 7604724513 ps
CPU time 156.63 seconds
Started Apr 28 04:21:40 PM PDT 24
Finished Apr 28 04:24:17 PM PDT 24
Peak memory 251296 kb
Host smart-25fe0ddf-5fa4-4c27-9916-77121a88d967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93673
4099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.936734099
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.1433645695
Short name T557
Test name
Test status
Simulation time 9226380624 ps
CPU time 91.77 seconds
Started Apr 28 04:21:55 PM PDT 24
Finished Apr 28 04:23:27 PM PDT 24
Peak memory 249188 kb
Host smart-1ace384c-a339-4ba7-af26-ce125db1b535
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14336
45695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.1433645695
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.4116540906
Short name T220
Test name
Test status
Simulation time 208853502072 ps
CPU time 1123.97 seconds
Started Apr 28 04:21:47 PM PDT 24
Finished Apr 28 04:40:31 PM PDT 24
Peak memory 268252 kb
Host smart-a1d1ce22-e356-4dae-b31f-987638cb46da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116540906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.4116540906
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.2059598850
Short name T327
Test name
Test status
Simulation time 53573273301 ps
CPU time 569.94 seconds
Started Apr 28 04:21:45 PM PDT 24
Finished Apr 28 04:31:15 PM PDT 24
Peak memory 248124 kb
Host smart-8aa2a51f-6d15-423d-b755-694875d35caa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059598850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.2059598850
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.1899293672
Short name T578
Test name
Test status
Simulation time 342054461 ps
CPU time 11.32 seconds
Started Apr 28 04:21:37 PM PDT 24
Finished Apr 28 04:21:48 PM PDT 24
Peak memory 256824 kb
Host smart-6e2970d8-ab83-4725-a5a2-42eda67dbd2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18992
93672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.1899293672
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.2346150094
Short name T524
Test name
Test status
Simulation time 5757041955 ps
CPU time 25.71 seconds
Started Apr 28 04:21:37 PM PDT 24
Finished Apr 28 04:22:03 PM PDT 24
Peak memory 256308 kb
Host smart-2c2d7a52-bd0f-43ab-b90a-f79a6345ec87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23461
50094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.2346150094
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.2928801797
Short name T564
Test name
Test status
Simulation time 990338648 ps
CPU time 33.42 seconds
Started Apr 28 04:21:42 PM PDT 24
Finished Apr 28 04:22:16 PM PDT 24
Peak memory 249176 kb
Host smart-fce0b1f3-a5f3-4800-bf23-6aad857d4e60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29288
01797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.2928801797
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.546975589
Short name T583
Test name
Test status
Simulation time 9259090369 ps
CPU time 55.17 seconds
Started Apr 28 04:21:34 PM PDT 24
Finished Apr 28 04:22:30 PM PDT 24
Peak memory 248760 kb
Host smart-1152318e-57c2-4027-beed-7d4ffe5c41d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54697
5589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.546975589
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.1521620733
Short name T675
Test name
Test status
Simulation time 96749173590 ps
CPU time 302.21 seconds
Started Apr 28 04:21:47 PM PDT 24
Finished Apr 28 04:26:50 PM PDT 24
Peak memory 255732 kb
Host smart-2e7aca8c-080f-4ca4-baa7-064ef454fb66
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521620733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.1521620733
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.4254142902
Short name T284
Test name
Test status
Simulation time 28366662939 ps
CPU time 996.39 seconds
Started Apr 28 04:21:54 PM PDT 24
Finished Apr 28 04:38:31 PM PDT 24
Peak memory 273228 kb
Host smart-88f38cbf-61a0-4b92-b804-3740fa8afd7f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254142902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.4254142902
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.987355651
Short name T621
Test name
Test status
Simulation time 23449478124 ps
CPU time 367.14 seconds
Started Apr 28 04:22:05 PM PDT 24
Finished Apr 28 04:28:12 PM PDT 24
Peak memory 251436 kb
Host smart-7d471d8d-c3fb-4bf0-a481-394e2e006931
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98735
5651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.987355651
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.855136197
Short name T561
Test name
Test status
Simulation time 421004436 ps
CPU time 16.05 seconds
Started Apr 28 04:21:51 PM PDT 24
Finished Apr 28 04:22:07 PM PDT 24
Peak memory 252028 kb
Host smart-0e55d920-503b-46fd-92a3-d00293fba745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85513
6197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.855136197
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.123699773
Short name T332
Test name
Test status
Simulation time 150600142458 ps
CPU time 1790.34 seconds
Started Apr 28 04:21:54 PM PDT 24
Finished Apr 28 04:51:45 PM PDT 24
Peak memory 267200 kb
Host smart-df0dd6a0-83dc-4750-ae81-ee79ef7d83d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123699773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.123699773
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.1984872038
Short name T446
Test name
Test status
Simulation time 185086157740 ps
CPU time 2864.48 seconds
Started Apr 28 04:21:53 PM PDT 24
Finished Apr 28 05:09:38 PM PDT 24
Peak memory 281584 kb
Host smart-bc381bb3-668f-49ea-859c-9f02d2d45787
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984872038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.1984872038
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.3452346893
Short name T331
Test name
Test status
Simulation time 6278169073 ps
CPU time 276.44 seconds
Started Apr 28 04:21:56 PM PDT 24
Finished Apr 28 04:26:33 PM PDT 24
Peak memory 255656 kb
Host smart-8b6a89da-7f87-4bd7-8884-911d77509b24
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452346893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.3452346893
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.98277411
Short name T632
Test name
Test status
Simulation time 1394751377 ps
CPU time 29.16 seconds
Started Apr 28 04:21:46 PM PDT 24
Finished Apr 28 04:22:15 PM PDT 24
Peak memory 254424 kb
Host smart-4b72781c-578a-4499-8557-598ce3f48492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98277
411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.98277411
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.3182150454
Short name T90
Test name
Test status
Simulation time 220664723 ps
CPU time 18.61 seconds
Started Apr 28 04:21:49 PM PDT 24
Finished Apr 28 04:22:08 PM PDT 24
Peak memory 249004 kb
Host smart-a34c2897-5c52-49e3-8f1f-4b51d4821c62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31821
50454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.3182150454
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.3899515660
Short name T598
Test name
Test status
Simulation time 102925255 ps
CPU time 7.68 seconds
Started Apr 28 04:21:51 PM PDT 24
Finished Apr 28 04:21:59 PM PDT 24
Peak memory 248732 kb
Host smart-da12be29-0584-42a1-a8ef-1d362d35931f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38995
15660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.3899515660
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.2152268239
Short name T693
Test name
Test status
Simulation time 194678162 ps
CPU time 15.26 seconds
Started Apr 28 04:21:46 PM PDT 24
Finished Apr 28 04:22:01 PM PDT 24
Peak memory 248692 kb
Host smart-212c3f75-0e7e-4304-94ba-deabc728975d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21522
68239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.2152268239
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.2386144182
Short name T453
Test name
Test status
Simulation time 118917909913 ps
CPU time 1952.71 seconds
Started Apr 28 04:21:54 PM PDT 24
Finished Apr 28 04:54:28 PM PDT 24
Peak memory 273072 kb
Host smart-69bad154-514d-45be-980c-6147c8ec1a03
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386144182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.2386144182
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.3303036404
Short name T618
Test name
Test status
Simulation time 88609269028 ps
CPU time 1524.59 seconds
Started Apr 28 04:22:05 PM PDT 24
Finished Apr 28 04:47:30 PM PDT 24
Peak memory 267440 kb
Host smart-e6cf6960-e978-45d8-ab50-f783521e0a09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303036404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.3303036404
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.3425450991
Short name T414
Test name
Test status
Simulation time 672645451 ps
CPU time 57.08 seconds
Started Apr 28 04:22:01 PM PDT 24
Finished Apr 28 04:22:58 PM PDT 24
Peak memory 248896 kb
Host smart-81b8a00a-2823-4b4d-a84d-ea723f6f7a98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34254
50991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.3425450991
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.3227311426
Short name T668
Test name
Test status
Simulation time 1197116342 ps
CPU time 44.41 seconds
Started Apr 28 04:22:02 PM PDT 24
Finished Apr 28 04:22:47 PM PDT 24
Peak memory 248732 kb
Host smart-8f8c7cbc-5009-48a6-ac7f-2ef79d0bff32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32273
11426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.3227311426
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.3155650842
Short name T46
Test name
Test status
Simulation time 10303967661 ps
CPU time 1340.4 seconds
Started Apr 28 04:22:07 PM PDT 24
Finished Apr 28 04:44:28 PM PDT 24
Peak memory 273332 kb
Host smart-ccd0c83f-eca8-4878-ae45-81f4ac453634
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155650842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3155650842
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.2686809714
Short name T477
Test name
Test status
Simulation time 50536157849 ps
CPU time 1312.76 seconds
Started Apr 28 04:22:10 PM PDT 24
Finished Apr 28 04:44:03 PM PDT 24
Peak memory 282124 kb
Host smart-3e7068be-8544-4564-8494-d0754ac8351c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686809714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.2686809714
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.3515678436
Short name T310
Test name
Test status
Simulation time 26909273581 ps
CPU time 292.06 seconds
Started Apr 28 04:22:05 PM PDT 24
Finished Apr 28 04:26:57 PM PDT 24
Peak memory 247048 kb
Host smart-1ae66b46-fb62-4b0b-9c53-8a7433ab4818
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515678436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.3515678436
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.3854119695
Short name T506
Test name
Test status
Simulation time 197713400 ps
CPU time 13.63 seconds
Started Apr 28 04:21:56 PM PDT 24
Finished Apr 28 04:22:10 PM PDT 24
Peak memory 248728 kb
Host smart-1d550467-3d61-4fba-a5ad-42374f370af5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38541
19695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.3854119695
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.2026543322
Short name T100
Test name
Test status
Simulation time 1465580816 ps
CPU time 17.39 seconds
Started Apr 28 04:22:03 PM PDT 24
Finished Apr 28 04:22:21 PM PDT 24
Peak memory 249132 kb
Host smart-804ab7d9-5c7c-4b9e-9e16-6c071b71ab14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20265
43322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.2026543322
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.3999495478
Short name T510
Test name
Test status
Simulation time 210863798 ps
CPU time 14.75 seconds
Started Apr 28 04:22:05 PM PDT 24
Finished Apr 28 04:22:20 PM PDT 24
Peak memory 248992 kb
Host smart-510e2e65-e62b-4055-9a80-d6477b71e42a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39994
95478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.3999495478
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.2050379660
Short name T95
Test name
Test status
Simulation time 292602064 ps
CPU time 16.14 seconds
Started Apr 28 04:21:55 PM PDT 24
Finished Apr 28 04:22:12 PM PDT 24
Peak memory 248704 kb
Host smart-4db5c8ad-3ddd-4561-952d-e4718fdaba60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20503
79660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.2050379660
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.2077997893
Short name T78
Test name
Test status
Simulation time 22332170919 ps
CPU time 1525.82 seconds
Started Apr 28 04:22:13 PM PDT 24
Finished Apr 28 04:47:39 PM PDT 24
Peak memory 273116 kb
Host smart-f1659290-cc43-4293-b1ff-af7ba89b2c40
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077997893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.2077997893
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.435647572
Short name T28
Test name
Test status
Simulation time 51839938063 ps
CPU time 2418.03 seconds
Started Apr 28 04:22:14 PM PDT 24
Finished Apr 28 05:02:33 PM PDT 24
Peak memory 304944 kb
Host smart-06793b62-9b09-419d-a5e3-f8337f55bc01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435647572 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.435647572
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.2404013336
Short name T281
Test name
Test status
Simulation time 29449309095 ps
CPU time 1827.74 seconds
Started Apr 28 04:22:23 PM PDT 24
Finished Apr 28 04:52:51 PM PDT 24
Peak memory 273392 kb
Host smart-f6f2e8a4-38bd-49a6-bee5-6fba9d0abb4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404013336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.2404013336
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.2381340754
Short name T650
Test name
Test status
Simulation time 4745085740 ps
CPU time 303.22 seconds
Started Apr 28 04:22:20 PM PDT 24
Finished Apr 28 04:27:24 PM PDT 24
Peak memory 251272 kb
Host smart-ac11b621-675e-4355-9d00-28be5339955d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23813
40754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.2381340754
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1623730522
Short name T686
Test name
Test status
Simulation time 3072397219 ps
CPU time 52.81 seconds
Started Apr 28 04:22:19 PM PDT 24
Finished Apr 28 04:23:12 PM PDT 24
Peak memory 255524 kb
Host smart-c7b41056-b095-4fe5-bd9a-18df9c30bdd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16237
30522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1623730522
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.2624986201
Short name T509
Test name
Test status
Simulation time 49201861621 ps
CPU time 1525.59 seconds
Started Apr 28 04:22:26 PM PDT 24
Finished Apr 28 04:47:52 PM PDT 24
Peak memory 267168 kb
Host smart-6333c14e-701e-4af6-9ca1-c0f1aa9d7761
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624986201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.2624986201
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.3721009201
Short name T118
Test name
Test status
Simulation time 101096637569 ps
CPU time 1734.52 seconds
Started Apr 28 04:22:27 PM PDT 24
Finished Apr 28 04:51:21 PM PDT 24
Peak memory 270200 kb
Host smart-fedcea92-18e5-4973-9612-44b08272b80e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721009201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.3721009201
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.3733569665
Short name T57
Test name
Test status
Simulation time 1661267430 ps
CPU time 32 seconds
Started Apr 28 04:22:18 PM PDT 24
Finished Apr 28 04:22:51 PM PDT 24
Peak memory 248692 kb
Host smart-23a746d0-f44a-4a38-bc69-c3d3b818e37c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37335
69665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.3733569665
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.2030379197
Short name T483
Test name
Test status
Simulation time 2340263216 ps
CPU time 42.17 seconds
Started Apr 28 04:22:20 PM PDT 24
Finished Apr 28 04:23:02 PM PDT 24
Peak memory 255516 kb
Host smart-73bc0267-353b-4d6f-a6ad-f71f37dd0569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20303
79197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.2030379197
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.308441118
Short name T657
Test name
Test status
Simulation time 1254470825 ps
CPU time 50.6 seconds
Started Apr 28 04:22:19 PM PDT 24
Finished Apr 28 04:23:10 PM PDT 24
Peak memory 248712 kb
Host smart-b9895e33-79e7-4c50-addb-1d40ba1bbd78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30844
1118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.308441118
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.3100853067
Short name T595
Test name
Test status
Simulation time 53448723943 ps
CPU time 3089.25 seconds
Started Apr 28 04:22:29 PM PDT 24
Finished Apr 28 05:13:59 PM PDT 24
Peak memory 289192 kb
Host smart-2a638f37-8c80-4373-90f0-832cea03f45a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100853067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.3100853067
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.3998138953
Short name T96
Test name
Test status
Simulation time 5007690029 ps
CPU time 322.48 seconds
Started Apr 28 04:22:30 PM PDT 24
Finished Apr 28 04:27:53 PM PDT 24
Peak memory 250988 kb
Host smart-571dd48a-5328-4c83-a642-9d6a4e39a28f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39981
38953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.3998138953
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.2816022407
Short name T529
Test name
Test status
Simulation time 1831193289 ps
CPU time 62.46 seconds
Started Apr 28 04:22:33 PM PDT 24
Finished Apr 28 04:23:35 PM PDT 24
Peak memory 248744 kb
Host smart-febda056-ee86-41ca-bc1f-7c35fcadfe0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28160
22407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.2816022407
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.1807473327
Short name T336
Test name
Test status
Simulation time 58321313899 ps
CPU time 1591.5 seconds
Started Apr 28 04:22:37 PM PDT 24
Finished Apr 28 04:49:09 PM PDT 24
Peak memory 288776 kb
Host smart-c3652e58-cf7e-49c8-a3e3-b893dbbbde4e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807473327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.1807473327
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.2705920046
Short name T674
Test name
Test status
Simulation time 489257536075 ps
CPU time 2219.41 seconds
Started Apr 28 04:22:34 PM PDT 24
Finished Apr 28 04:59:34 PM PDT 24
Peak memory 272972 kb
Host smart-1a75ef01-8739-4581-ad21-bfbe4f169f56
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705920046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.2705920046
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.2151337601
Short name T304
Test name
Test status
Simulation time 10767165628 ps
CPU time 419.82 seconds
Started Apr 28 04:22:30 PM PDT 24
Finished Apr 28 04:29:30 PM PDT 24
Peak memory 248288 kb
Host smart-a2f4f515-893e-4c11-acc6-5512ce3352d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151337601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.2151337601
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.664087736
Short name T392
Test name
Test status
Simulation time 403139699 ps
CPU time 30.29 seconds
Started Apr 28 04:22:25 PM PDT 24
Finished Apr 28 04:22:56 PM PDT 24
Peak memory 248724 kb
Host smart-9b5a1e9c-4f60-4ba2-b6e0-9ad34a377e5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66408
7736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.664087736
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.361196455
Short name T449
Test name
Test status
Simulation time 383194215 ps
CPU time 24.82 seconds
Started Apr 28 04:22:32 PM PDT 24
Finished Apr 28 04:22:57 PM PDT 24
Peak memory 255912 kb
Host smart-c2340cb9-1376-4fe5-abb6-0af0f99fe0d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36119
6455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.361196455
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.806821480
Short name T267
Test name
Test status
Simulation time 3610398411 ps
CPU time 58.09 seconds
Started Apr 28 04:22:30 PM PDT 24
Finished Apr 28 04:23:28 PM PDT 24
Peak memory 255596 kb
Host smart-b545bf9d-cb28-4bef-b59a-74a815e2b60d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80682
1480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.806821480
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.3519528080
Short name T436
Test name
Test status
Simulation time 152545235 ps
CPU time 9.83 seconds
Started Apr 28 04:22:26 PM PDT 24
Finished Apr 28 04:22:36 PM PDT 24
Peak memory 248656 kb
Host smart-d26fe664-574d-41bb-847d-6246e6f50014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35195
28080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3519528080
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.2720096200
Short name T585
Test name
Test status
Simulation time 243284820 ps
CPU time 25.07 seconds
Started Apr 28 04:22:35 PM PDT 24
Finished Apr 28 04:23:00 PM PDT 24
Peak memory 256184 kb
Host smart-4afd3b15-c1a6-4d39-844c-d9e2f8fc5364
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720096200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.2720096200
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.3994240523
Short name T519
Test name
Test status
Simulation time 58287636444 ps
CPU time 1854.85 seconds
Started Apr 28 04:22:43 PM PDT 24
Finished Apr 28 04:53:38 PM PDT 24
Peak memory 271868 kb
Host smart-bd443dda-9ec1-437d-8f72-f73a7ab5a5e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994240523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.3994240523
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.43034539
Short name T689
Test name
Test status
Simulation time 5449424713 ps
CPU time 315.62 seconds
Started Apr 28 04:22:38 PM PDT 24
Finished Apr 28 04:27:53 PM PDT 24
Peak memory 250816 kb
Host smart-378c24f3-2aea-48e0-bf28-bc20027b279c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43034
539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.43034539
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.1679901823
Short name T89
Test name
Test status
Simulation time 415422443 ps
CPU time 29.38 seconds
Started Apr 28 04:22:40 PM PDT 24
Finished Apr 28 04:23:09 PM PDT 24
Peak memory 256872 kb
Host smart-7e8158dc-717d-4bfd-be14-ece85c312065
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16799
01823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.1679901823
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.1194093785
Short name T236
Test name
Test status
Simulation time 15031739409 ps
CPU time 1049.06 seconds
Started Apr 28 04:22:42 PM PDT 24
Finished Apr 28 04:40:11 PM PDT 24
Peak memory 273364 kb
Host smart-8caa7706-d175-4b6d-8ecc-777e3209572a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194093785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.1194093785
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.2671460176
Short name T421
Test name
Test status
Simulation time 191295007941 ps
CPU time 1415.44 seconds
Started Apr 28 04:22:43 PM PDT 24
Finished Apr 28 04:46:19 PM PDT 24
Peak memory 281576 kb
Host smart-fafdd692-1814-440a-bf07-e44c4c6b495c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671460176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.2671460176
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.3523214584
Short name T326
Test name
Test status
Simulation time 46781872350 ps
CPU time 605.35 seconds
Started Apr 28 04:22:43 PM PDT 24
Finished Apr 28 04:32:49 PM PDT 24
Peak memory 248092 kb
Host smart-f32d426f-db6e-4dab-81a2-76219cc8e91a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523214584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.3523214584
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.1971768815
Short name T525
Test name
Test status
Simulation time 3598061287 ps
CPU time 25.82 seconds
Started Apr 28 04:22:34 PM PDT 24
Finished Apr 28 04:23:01 PM PDT 24
Peak memory 256972 kb
Host smart-b238145f-b226-4711-ba3f-47a9ef6455ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19717
68815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.1971768815
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.2576008805
Short name T687
Test name
Test status
Simulation time 44348149 ps
CPU time 4.48 seconds
Started Apr 28 04:22:40 PM PDT 24
Finished Apr 28 04:22:45 PM PDT 24
Peak memory 240496 kb
Host smart-5a4fd224-c234-41a9-864f-20192cce8575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25760
08805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2576008805
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.1923998860
Short name T82
Test name
Test status
Simulation time 156925828 ps
CPU time 24.44 seconds
Started Apr 28 04:22:44 PM PDT 24
Finished Apr 28 04:23:09 PM PDT 24
Peak memory 248704 kb
Host smart-8e39a171-f3c6-430f-b7f2-421e17f3307c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19239
98860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.1923998860
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.2261180066
Short name T239
Test name
Test status
Simulation time 138031185 ps
CPU time 14.27 seconds
Started Apr 28 04:22:34 PM PDT 24
Finished Apr 28 04:22:49 PM PDT 24
Peak memory 248776 kb
Host smart-0d94f493-c3a4-44da-b72c-d9d71ccce0eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22611
80066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.2261180066
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.3534975836
Short name T39
Test name
Test status
Simulation time 19841610545 ps
CPU time 1432.33 seconds
Started Apr 28 04:22:43 PM PDT 24
Finished Apr 28 04:46:36 PM PDT 24
Peak memory 273352 kb
Host smart-e234d489-180c-4fa6-8603-c888cc225e32
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534975836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.3534975836
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.1126976840
Short name T19
Test name
Test status
Simulation time 125927899066 ps
CPU time 2128.17 seconds
Started Apr 28 04:22:47 PM PDT 24
Finished Apr 28 04:58:15 PM PDT 24
Peak memory 281692 kb
Host smart-45661a5f-1615-4e37-aed7-b8a7e0814a00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126976840 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.1126976840
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.2176214337
Short name T201
Test name
Test status
Simulation time 39774963 ps
CPU time 3.61 seconds
Started Apr 28 04:12:17 PM PDT 24
Finished Apr 28 04:12:20 PM PDT 24
Peak memory 248876 kb
Host smart-58391852-04b5-4dba-a3b5-e5a34aed559d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2176214337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.2176214337
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.3747240877
Short name T41
Test name
Test status
Simulation time 59672289356 ps
CPU time 3423.56 seconds
Started Apr 28 04:11:52 PM PDT 24
Finished Apr 28 05:08:56 PM PDT 24
Peak memory 289424 kb
Host smart-d40d3ba9-8c53-47d0-9349-8ee3a4375976
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747240877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.3747240877
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.3009126848
Short name T420
Test name
Test status
Simulation time 976781059 ps
CPU time 13.44 seconds
Started Apr 28 04:12:19 PM PDT 24
Finished Apr 28 04:12:32 PM PDT 24
Peak memory 248676 kb
Host smart-c18d06e0-f985-4d34-8365-d97abc0d6f00
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3009126848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.3009126848
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.771506068
Short name T587
Test name
Test status
Simulation time 2519536607 ps
CPU time 76.59 seconds
Started Apr 28 04:11:50 PM PDT 24
Finished Apr 28 04:13:07 PM PDT 24
Peak memory 249068 kb
Host smart-b8727b8e-0abd-4f6e-bb2e-6c03aac65651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77150
6068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.771506068
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.1197764061
Short name T627
Test name
Test status
Simulation time 568837736 ps
CPU time 29.22 seconds
Started Apr 28 04:11:55 PM PDT 24
Finished Apr 28 04:12:25 PM PDT 24
Peak memory 255856 kb
Host smart-dbe3dd10-02cb-4716-b747-28204c0cbbdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11977
64061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.1197764061
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.3671910984
Short name T475
Test name
Test status
Simulation time 38925371427 ps
CPU time 1095.63 seconds
Started Apr 28 04:12:00 PM PDT 24
Finished Apr 28 04:30:16 PM PDT 24
Peak memory 288704 kb
Host smart-a74f9233-92d0-4ee3-a4c6-562013380d77
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671910984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.3671910984
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.1402812195
Short name T614
Test name
Test status
Simulation time 33889865640 ps
CPU time 1885.99 seconds
Started Apr 28 04:12:00 PM PDT 24
Finished Apr 28 04:43:26 PM PDT 24
Peak memory 271292 kb
Host smart-40177a7e-7383-43a0-99d9-be8c5c953ef7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402812195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.1402812195
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.730734968
Short name T242
Test name
Test status
Simulation time 4262010021 ps
CPU time 182.32 seconds
Started Apr 28 04:11:50 PM PDT 24
Finished Apr 28 04:14:52 PM PDT 24
Peak memory 248356 kb
Host smart-6cbf8e70-121d-46ab-aa29-3dba4685b720
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730734968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.730734968
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.4010101127
Short name T597
Test name
Test status
Simulation time 494977369 ps
CPU time 33.81 seconds
Started Apr 28 04:11:33 PM PDT 24
Finished Apr 28 04:12:07 PM PDT 24
Peak memory 256916 kb
Host smart-5413819e-9d34-4ad1-ba5b-9b4e1c62fd30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40101
01127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.4010101127
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.716472527
Short name T58
Test name
Test status
Simulation time 1870754584 ps
CPU time 40.96 seconds
Started Apr 28 04:11:40 PM PDT 24
Finished Apr 28 04:12:21 PM PDT 24
Peak memory 255396 kb
Host smart-ebaa65c6-ceee-431b-86c0-43adb9f56c76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71647
2527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.716472527
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.1698475524
Short name T428
Test name
Test status
Simulation time 3640274135 ps
CPU time 66.5 seconds
Started Apr 28 04:11:27 PM PDT 24
Finished Apr 28 04:12:34 PM PDT 24
Peak memory 256060 kb
Host smart-8ba33b4a-a744-4add-8284-9c2ae3390396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16984
75524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.1698475524
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.3411857588
Short name T384
Test name
Test status
Simulation time 46664651629 ps
CPU time 2475.94 seconds
Started Apr 28 04:12:13 PM PDT 24
Finished Apr 28 04:53:29 PM PDT 24
Peak memory 288480 kb
Host smart-c131adc2-9272-4643-a622-40a803d649f5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411857588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.3411857588
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.1872230283
Short name T6
Test name
Test status
Simulation time 21830797675 ps
CPU time 1009.28 seconds
Started Apr 28 04:22:51 PM PDT 24
Finished Apr 28 04:39:40 PM PDT 24
Peak memory 282528 kb
Host smart-9b5d7d5e-4f19-4297-8014-3ac3ceea24fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872230283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.1872230283
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.2708165893
Short name T579
Test name
Test status
Simulation time 887816407 ps
CPU time 73.34 seconds
Started Apr 28 04:22:46 PM PDT 24
Finished Apr 28 04:24:00 PM PDT 24
Peak memory 248744 kb
Host smart-20280704-f3e7-4322-9622-3061e3d5149b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27081
65893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.2708165893
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.3856792689
Short name T541
Test name
Test status
Simulation time 807889304 ps
CPU time 38.07 seconds
Started Apr 28 04:22:47 PM PDT 24
Finished Apr 28 04:23:25 PM PDT 24
Peak memory 249164 kb
Host smart-11b3fc09-a3d6-43e8-9bc7-a08bd90b5dd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38567
92689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.3856792689
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.2688153376
Short name T671
Test name
Test status
Simulation time 14330409278 ps
CPU time 1142.67 seconds
Started Apr 28 04:22:54 PM PDT 24
Finished Apr 28 04:41:57 PM PDT 24
Peak memory 273364 kb
Host smart-fc1ae644-2a07-4fe7-997e-855b56e94c97
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688153376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.2688153376
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.4079960344
Short name T513
Test name
Test status
Simulation time 51561464252 ps
CPU time 764.7 seconds
Started Apr 28 04:22:55 PM PDT 24
Finished Apr 28 04:35:40 PM PDT 24
Peak memory 273256 kb
Host smart-bb6dfea0-8065-41bc-a7de-70e3f84429df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079960344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.4079960344
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.3489226961
Short name T373
Test name
Test status
Simulation time 1245511024 ps
CPU time 30.65 seconds
Started Apr 28 04:22:54 PM PDT 24
Finished Apr 28 04:23:25 PM PDT 24
Peak memory 248692 kb
Host smart-8ea44def-b5e9-46bd-a17c-294fd7bed81f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34892
26961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.3489226961
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.2332898391
Short name T115
Test name
Test status
Simulation time 1256691830 ps
CPU time 24.66 seconds
Started Apr 28 04:22:53 PM PDT 24
Finished Apr 28 04:23:18 PM PDT 24
Peak memory 255284 kb
Host smart-b8d43711-8996-4bcd-bb36-2bd6bd7aaae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23328
98391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.2332898391
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.3610541805
Short name T628
Test name
Test status
Simulation time 2352502417 ps
CPU time 40.28 seconds
Started Apr 28 04:22:54 PM PDT 24
Finished Apr 28 04:23:35 PM PDT 24
Peak memory 248764 kb
Host smart-6a1c0425-b1b3-4f40-aa17-8a9767a991e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36105
41805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.3610541805
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.3318603086
Short name T274
Test name
Test status
Simulation time 44470462324 ps
CPU time 2830.54 seconds
Started Apr 28 04:22:54 PM PDT 24
Finished Apr 28 05:10:05 PM PDT 24
Peak memory 289212 kb
Host smart-9fa40704-4291-4a36-b2fc-5831945fddb4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318603086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.3318603086
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.2632764730
Short name T247
Test name
Test status
Simulation time 134261150442 ps
CPU time 2274.56 seconds
Started Apr 28 04:22:56 PM PDT 24
Finished Apr 28 05:00:51 PM PDT 24
Peak memory 289708 kb
Host smart-c7609eb1-2b2a-442f-916b-01d7f4f0fcee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632764730 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.2632764730
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.2585924653
Short name T518
Test name
Test status
Simulation time 46297321914 ps
CPU time 1092.92 seconds
Started Apr 28 04:23:11 PM PDT 24
Finished Apr 28 04:41:24 PM PDT 24
Peak memory 285752 kb
Host smart-9fa476ad-4015-42da-8a20-17d34c27e4d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585924653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.2585924653
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.697868248
Short name T684
Test name
Test status
Simulation time 7383965125 ps
CPU time 130.83 seconds
Started Apr 28 04:23:07 PM PDT 24
Finished Apr 28 04:25:18 PM PDT 24
Peak memory 256920 kb
Host smart-0858bdaf-0b62-499b-99da-74d81b7cc528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69786
8248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.697868248
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.1281252490
Short name T644
Test name
Test status
Simulation time 876497185 ps
CPU time 56.97 seconds
Started Apr 28 04:23:07 PM PDT 24
Finished Apr 28 04:24:05 PM PDT 24
Peak memory 248740 kb
Host smart-c6c62335-54ba-411d-9666-3b08530ef15a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12812
52490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.1281252490
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.1901923667
Short name T596
Test name
Test status
Simulation time 46325735255 ps
CPU time 1620.4 seconds
Started Apr 28 04:23:11 PM PDT 24
Finished Apr 28 04:50:12 PM PDT 24
Peak memory 285632 kb
Host smart-094eceb6-0de3-44ad-8bfe-315eb5a9a3ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901923667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.1901923667
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.3749981019
Short name T635
Test name
Test status
Simulation time 76172588874 ps
CPU time 633.54 seconds
Started Apr 28 04:23:11 PM PDT 24
Finished Apr 28 04:33:45 PM PDT 24
Peak memory 247796 kb
Host smart-afacadeb-bb14-45d6-b223-1e73a3dea2b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749981019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.3749981019
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.2047869529
Short name T426
Test name
Test status
Simulation time 2359866432 ps
CPU time 80.4 seconds
Started Apr 28 04:23:06 PM PDT 24
Finished Apr 28 04:24:26 PM PDT 24
Peak memory 248744 kb
Host smart-e8a9218d-45aa-4f60-b497-5ff103d6be4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20478
69529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.2047869529
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.1527644577
Short name T472
Test name
Test status
Simulation time 625897379 ps
CPU time 41.1 seconds
Started Apr 28 04:23:07 PM PDT 24
Finished Apr 28 04:23:49 PM PDT 24
Peak memory 248744 kb
Host smart-69d268d2-8da6-4cb5-a866-388c20f4e2a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15276
44577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.1527644577
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.1853403969
Short name T532
Test name
Test status
Simulation time 443059812 ps
CPU time 36.08 seconds
Started Apr 28 04:22:59 PM PDT 24
Finished Apr 28 04:23:35 PM PDT 24
Peak memory 248708 kb
Host smart-9663b3f2-a404-4617-8059-38260186511e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18534
03969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.1853403969
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.1194492758
Short name T64
Test name
Test status
Simulation time 17846356927 ps
CPU time 1108.09 seconds
Started Apr 28 04:23:11 PM PDT 24
Finished Apr 28 04:41:40 PM PDT 24
Peak memory 288100 kb
Host smart-8503e3c4-90c2-4268-94a4-52ea888562da
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194492758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.1194492758
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.3886978211
Short name T603
Test name
Test status
Simulation time 17012171659 ps
CPU time 1342.89 seconds
Started Apr 28 04:23:28 PM PDT 24
Finished Apr 28 04:45:52 PM PDT 24
Peak memory 289140 kb
Host smart-dce02d90-eae0-4870-8811-9879d506f0df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886978211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.3886978211
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.620534101
Short name T515
Test name
Test status
Simulation time 921900543 ps
CPU time 65.43 seconds
Started Apr 28 04:23:24 PM PDT 24
Finished Apr 28 04:24:30 PM PDT 24
Peak memory 249036 kb
Host smart-94ec3eca-b2df-4944-be11-504684a0179e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62053
4101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.620534101
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.2033148651
Short name T425
Test name
Test status
Simulation time 695175846 ps
CPU time 42.82 seconds
Started Apr 28 04:23:19 PM PDT 24
Finished Apr 28 04:24:02 PM PDT 24
Peak memory 248644 kb
Host smart-bf4d918f-2aff-4721-b32f-6c300310d367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20331
48651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.2033148651
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.3230517063
Short name T333
Test name
Test status
Simulation time 56668628159 ps
CPU time 1528.29 seconds
Started Apr 28 04:23:26 PM PDT 24
Finished Apr 28 04:48:55 PM PDT 24
Peak memory 273408 kb
Host smart-7cfaf808-11de-4964-992a-9d4267c00547
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230517063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.3230517063
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.1807070863
Short name T285
Test name
Test status
Simulation time 9329867186 ps
CPU time 875.73 seconds
Started Apr 28 04:23:29 PM PDT 24
Finished Apr 28 04:38:05 PM PDT 24
Peak memory 272900 kb
Host smart-5568bb74-2dcb-45a6-b39c-b67b72d6fddc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807070863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.1807070863
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.3738890836
Short name T314
Test name
Test status
Simulation time 11539034542 ps
CPU time 502.96 seconds
Started Apr 28 04:23:26 PM PDT 24
Finished Apr 28 04:31:49 PM PDT 24
Peak memory 248216 kb
Host smart-0029a860-8a34-4fdc-8b80-d5480ce2248e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738890836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.3738890836
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.3416548324
Short name T65
Test name
Test status
Simulation time 6283926865 ps
CPU time 54.67 seconds
Started Apr 28 04:23:19 PM PDT 24
Finished Apr 28 04:24:14 PM PDT 24
Peak memory 248768 kb
Host smart-05e038be-da8e-448e-a598-e3a7d47f5b7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34165
48324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.3416548324
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.3236339337
Short name T97
Test name
Test status
Simulation time 830294480 ps
CPU time 68.13 seconds
Started Apr 28 04:23:19 PM PDT 24
Finished Apr 28 04:24:27 PM PDT 24
Peak memory 255564 kb
Host smart-ba7cd729-7daa-495c-b25a-7e573a80ae8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32363
39337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.3236339337
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.523669658
Short name T418
Test name
Test status
Simulation time 163493522 ps
CPU time 23.15 seconds
Started Apr 28 04:23:24 PM PDT 24
Finished Apr 28 04:23:48 PM PDT 24
Peak memory 247768 kb
Host smart-a5776e95-e877-4fd2-b4f6-714758990684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52366
9658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.523669658
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.2871963925
Short name T227
Test name
Test status
Simulation time 293552393 ps
CPU time 19.03 seconds
Started Apr 28 04:23:14 PM PDT 24
Finished Apr 28 04:23:34 PM PDT 24
Peak memory 248720 kb
Host smart-f4a225ff-3326-4096-8e0d-cad30551cccd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28719
63925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2871963925
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.4283388061
Short name T370
Test name
Test status
Simulation time 16404347518 ps
CPU time 171.54 seconds
Started Apr 28 04:23:30 PM PDT 24
Finished Apr 28 04:26:22 PM PDT 24
Peak memory 256388 kb
Host smart-ea1b6258-c312-423c-a949-27d91694e658
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283388061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.4283388061
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.4138891758
Short name T291
Test name
Test status
Simulation time 24594911475 ps
CPU time 1572.11 seconds
Started Apr 28 04:23:36 PM PDT 24
Finished Apr 28 04:49:49 PM PDT 24
Peak memory 289876 kb
Host smart-0f3f820c-d0d0-4b45-ad44-f0cc770961c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138891758 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.4138891758
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.2031866608
Short name T49
Test name
Test status
Simulation time 7138102749 ps
CPU time 913.33 seconds
Started Apr 28 04:23:42 PM PDT 24
Finished Apr 28 04:38:56 PM PDT 24
Peak memory 273412 kb
Host smart-349bac10-25da-4c2f-a9fb-b8a731756400
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031866608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.2031866608
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.257081726
Short name T507
Test name
Test status
Simulation time 4117932480 ps
CPU time 280.34 seconds
Started Apr 28 04:23:38 PM PDT 24
Finished Apr 28 04:28:19 PM PDT 24
Peak memory 250888 kb
Host smart-40ad6f84-f723-41f6-b719-3b346bae2f2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25708
1726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.257081726
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.3319249378
Short name T565
Test name
Test status
Simulation time 85959149 ps
CPU time 4.88 seconds
Started Apr 28 04:23:36 PM PDT 24
Finished Apr 28 04:23:42 PM PDT 24
Peak memory 240500 kb
Host smart-3356794e-e465-4459-8d52-4cff180d33d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33192
49378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.3319249378
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.3498352240
Short name T346
Test name
Test status
Simulation time 41855785447 ps
CPU time 2819.9 seconds
Started Apr 28 04:23:46 PM PDT 24
Finished Apr 28 05:10:46 PM PDT 24
Peak memory 289040 kb
Host smart-c932b66f-f178-489b-a145-0c5aadb9e7c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498352240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.3498352240
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.103253833
Short name T423
Test name
Test status
Simulation time 47446515168 ps
CPU time 2686.98 seconds
Started Apr 28 04:23:47 PM PDT 24
Finished Apr 28 05:08:35 PM PDT 24
Peak memory 288964 kb
Host smart-76144fb0-22ca-4fbb-9e49-67266f5d6efa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103253833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.103253833
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.3393115149
Short name T484
Test name
Test status
Simulation time 1372036552 ps
CPU time 32.23 seconds
Started Apr 28 04:23:33 PM PDT 24
Finished Apr 28 04:24:05 PM PDT 24
Peak memory 255836 kb
Host smart-15c0a867-a342-4d2e-9220-0bdc0ed10713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33931
15149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.3393115149
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.3580729815
Short name T697
Test name
Test status
Simulation time 913367787 ps
CPU time 50.66 seconds
Started Apr 28 04:23:34 PM PDT 24
Finished Apr 28 04:24:25 PM PDT 24
Peak memory 248732 kb
Host smart-8152021a-7920-4216-ac2c-7b4e2d595a93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35807
29815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.3580729815
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.796282068
Short name T293
Test name
Test status
Simulation time 1251716025 ps
CPU time 32.7 seconds
Started Apr 28 04:23:42 PM PDT 24
Finished Apr 28 04:24:15 PM PDT 24
Peak memory 248708 kb
Host smart-953dbaa4-4401-465c-8a11-6fccbcba1ffc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79628
2068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.796282068
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.274112157
Short name T626
Test name
Test status
Simulation time 737446826 ps
CPU time 53.93 seconds
Started Apr 28 04:23:34 PM PDT 24
Finished Apr 28 04:24:28 PM PDT 24
Peak memory 248728 kb
Host smart-3c89fc36-eb95-49f3-886e-465dfb53be45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27411
2157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.274112157
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.1158165353
Short name T363
Test name
Test status
Simulation time 472594473 ps
CPU time 49.96 seconds
Started Apr 28 04:23:47 PM PDT 24
Finished Apr 28 04:24:37 PM PDT 24
Peak memory 256192 kb
Host smart-7d6d14e9-b343-4863-990e-fb35b57f7829
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158165353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.1158165353
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.444583744
Short name T187
Test name
Test status
Simulation time 67921273977 ps
CPU time 1274.86 seconds
Started Apr 28 04:24:00 PM PDT 24
Finished Apr 28 04:45:15 PM PDT 24
Peak memory 265464 kb
Host smart-7147c5a6-06dc-49b3-bc9a-3da5ce0abc6d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444583744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.444583744
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.2583046913
Short name T369
Test name
Test status
Simulation time 2966224926 ps
CPU time 46.79 seconds
Started Apr 28 04:24:00 PM PDT 24
Finished Apr 28 04:24:47 PM PDT 24
Peak memory 248808 kb
Host smart-e2b215e0-b2c0-428d-a38e-ff9c16247072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25830
46913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.2583046913
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.2004804598
Short name T501
Test name
Test status
Simulation time 546936700 ps
CPU time 32.76 seconds
Started Apr 28 04:23:55 PM PDT 24
Finished Apr 28 04:24:28 PM PDT 24
Peak memory 248732 kb
Host smart-6b699d19-60d5-49b8-9b2c-d7548236de37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20048
04598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.2004804598
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.393770679
Short name T237
Test name
Test status
Simulation time 184410496746 ps
CPU time 2630.13 seconds
Started Apr 28 04:23:59 PM PDT 24
Finished Apr 28 05:07:50 PM PDT 24
Peak memory 272584 kb
Host smart-fbdbc956-599b-421a-b9d8-7d58aec2e49c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393770679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.393770679
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.4005625812
Short name T616
Test name
Test status
Simulation time 14557075670 ps
CPU time 1312.51 seconds
Started Apr 28 04:24:03 PM PDT 24
Finished Apr 28 04:45:56 PM PDT 24
Peak memory 285540 kb
Host smart-d1e93ae6-ee7a-492f-b0c1-eeecf544349c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005625812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.4005625812
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.3436192812
Short name T316
Test name
Test status
Simulation time 13846510525 ps
CPU time 561.5 seconds
Started Apr 28 04:23:59 PM PDT 24
Finished Apr 28 04:33:21 PM PDT 24
Peak memory 256036 kb
Host smart-8525daea-1aa7-40ed-a87a-25384390465b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436192812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.3436192812
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.2406383244
Short name T463
Test name
Test status
Simulation time 239245701 ps
CPU time 8.59 seconds
Started Apr 28 04:23:51 PM PDT 24
Finished Apr 28 04:24:00 PM PDT 24
Peak memory 248688 kb
Host smart-2498dad4-b3e9-442e-87a8-10c1971459ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24063
83244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.2406383244
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.3128134257
Short name T593
Test name
Test status
Simulation time 3693891503 ps
CPU time 56.25 seconds
Started Apr 28 04:23:56 PM PDT 24
Finished Apr 28 04:24:53 PM PDT 24
Peak memory 248760 kb
Host smart-509cbc63-6c97-4a55-a232-42f1be6065a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31281
34257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.3128134257
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.1838838256
Short name T544
Test name
Test status
Simulation time 116067989 ps
CPU time 15.04 seconds
Started Apr 28 04:23:58 PM PDT 24
Finished Apr 28 04:24:14 PM PDT 24
Peak memory 248676 kb
Host smart-5f592226-0188-473d-b6a2-1581634dee4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18388
38256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.1838838256
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.3459915772
Short name T92
Test name
Test status
Simulation time 825778723 ps
CPU time 27.89 seconds
Started Apr 28 04:23:52 PM PDT 24
Finished Apr 28 04:24:20 PM PDT 24
Peak memory 248696 kb
Host smart-37bace63-c030-42a2-83e4-2bf90a3403ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34599
15772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.3459915772
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.2194472477
Short name T88
Test name
Test status
Simulation time 12391115288 ps
CPU time 232.28 seconds
Started Apr 28 04:24:01 PM PDT 24
Finished Apr 28 04:27:54 PM PDT 24
Peak memory 256952 kb
Host smart-fc5b2e9b-9ecc-46d3-8fcf-32c6bfb30a3c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194472477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.2194472477
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.3108463097
Short name T33
Test name
Test status
Simulation time 77850795131 ps
CPU time 2617.89 seconds
Started Apr 28 04:24:03 PM PDT 24
Finished Apr 28 05:07:42 PM PDT 24
Peak memory 298020 kb
Host smart-6c16bb54-55ba-423a-bbb4-ef54204518cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108463097 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.3108463097
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.3009281020
Short name T53
Test name
Test status
Simulation time 45063011889 ps
CPU time 3001.15 seconds
Started Apr 28 04:24:06 PM PDT 24
Finished Apr 28 05:14:08 PM PDT 24
Peak memory 289412 kb
Host smart-9ef5a53e-296d-40f8-8d87-f51af7a171de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009281020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.3009281020
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.4054128123
Short name T375
Test name
Test status
Simulation time 807516591 ps
CPU time 19.17 seconds
Started Apr 28 04:24:07 PM PDT 24
Finished Apr 28 04:24:27 PM PDT 24
Peak memory 248696 kb
Host smart-4b6132df-8418-4351-97af-ab6af1b63617
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40541
28123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.4054128123
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.2351148985
Short name T637
Test name
Test status
Simulation time 829056317 ps
CPU time 48.94 seconds
Started Apr 28 04:24:07 PM PDT 24
Finished Apr 28 04:24:56 PM PDT 24
Peak memory 255860 kb
Host smart-dc2b9b7a-6c0d-46c2-88f3-9c118659c5a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23511
48985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.2351148985
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.3587079015
Short name T288
Test name
Test status
Simulation time 95849639895 ps
CPU time 1587.13 seconds
Started Apr 28 04:24:08 PM PDT 24
Finished Apr 28 04:50:36 PM PDT 24
Peak memory 267248 kb
Host smart-9b1910f6-71f8-4f91-a7b7-e35da9dfe7dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587079015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3587079015
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.1009470843
Short name T647
Test name
Test status
Simulation time 24110521972 ps
CPU time 1705.35 seconds
Started Apr 28 04:24:13 PM PDT 24
Finished Apr 28 04:52:39 PM PDT 24
Peak memory 273312 kb
Host smart-5963534a-a8a8-4bff-a8e8-6b86b7191adc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009470843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1009470843
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.3465551217
Short name T698
Test name
Test status
Simulation time 197947430 ps
CPU time 17.26 seconds
Started Apr 28 04:24:05 PM PDT 24
Finished Apr 28 04:24:23 PM PDT 24
Peak memory 248664 kb
Host smart-07a9d78a-c8eb-4b2c-86da-0c9d1a87cf8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34655
51217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.3465551217
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.4510412
Short name T649
Test name
Test status
Simulation time 611020158 ps
CPU time 42.09 seconds
Started Apr 28 04:24:05 PM PDT 24
Finished Apr 28 04:24:48 PM PDT 24
Peak memory 248780 kb
Host smart-e7a4d36f-1ec7-4eb3-b749-6fb066d7de7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45104
12 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.4510412
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.3083480275
Short name T270
Test name
Test status
Simulation time 3091699094 ps
CPU time 52.54 seconds
Started Apr 28 04:24:05 PM PDT 24
Finished Apr 28 04:24:58 PM PDT 24
Peak memory 248764 kb
Host smart-26e8c941-4526-4e44-a625-2e6530210bfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30834
80275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.3083480275
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.1839680057
Short name T606
Test name
Test status
Simulation time 945306081 ps
CPU time 23.48 seconds
Started Apr 28 04:24:04 PM PDT 24
Finished Apr 28 04:24:28 PM PDT 24
Peak memory 248704 kb
Host smart-b10331b0-71a0-49c4-82d7-79876b7ab82b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18396
80057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.1839680057
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.2737942321
Short name T63
Test name
Test status
Simulation time 53610320006 ps
CPU time 3431.21 seconds
Started Apr 28 04:24:11 PM PDT 24
Finished Apr 28 05:21:23 PM PDT 24
Peak memory 303812 kb
Host smart-43c74ba5-0508-4ff9-998e-38fa32f1e5e9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737942321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.2737942321
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.4280681687
Short name T298
Test name
Test status
Simulation time 32273612027 ps
CPU time 842.54 seconds
Started Apr 28 04:24:22 PM PDT 24
Finished Apr 28 04:38:25 PM PDT 24
Peak memory 265272 kb
Host smart-21aa6cbd-5cbe-454c-8b8f-83f1f3346dee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280681687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.4280681687
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.740655970
Short name T409
Test name
Test status
Simulation time 26695274707 ps
CPU time 167.23 seconds
Started Apr 28 04:24:23 PM PDT 24
Finished Apr 28 04:27:11 PM PDT 24
Peak memory 248756 kb
Host smart-f578fafc-4dbc-468d-bef9-f28208dc352b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74065
5970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.740655970
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.944093487
Short name T678
Test name
Test status
Simulation time 639043407 ps
CPU time 11.78 seconds
Started Apr 28 04:24:20 PM PDT 24
Finished Apr 28 04:24:32 PM PDT 24
Peak memory 252968 kb
Host smart-6dc01f32-2d3c-47e0-8951-6c204d5f547a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94409
3487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.944093487
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.4055556523
Short name T505
Test name
Test status
Simulation time 39749525210 ps
CPU time 1466.06 seconds
Started Apr 28 04:24:24 PM PDT 24
Finished Apr 28 04:48:50 PM PDT 24
Peak memory 273380 kb
Host smart-a6672131-1e75-45d4-bcc5-93b5eda3060a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055556523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.4055556523
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.598215348
Short name T660
Test name
Test status
Simulation time 45487592676 ps
CPU time 2509.96 seconds
Started Apr 28 04:24:24 PM PDT 24
Finished Apr 28 05:06:15 PM PDT 24
Peak memory 281584 kb
Host smart-8bc3868d-9c74-4a6a-bf35-1ba0837a496f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598215348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.598215348
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.3371073345
Short name T329
Test name
Test status
Simulation time 61096579651 ps
CPU time 426.86 seconds
Started Apr 28 04:24:24 PM PDT 24
Finished Apr 28 04:31:31 PM PDT 24
Peak memory 248116 kb
Host smart-a36fcf1c-7ac6-4876-bb6e-67da2f79181b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371073345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.3371073345
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.403952717
Short name T498
Test name
Test status
Simulation time 344480032 ps
CPU time 21.03 seconds
Started Apr 28 04:24:20 PM PDT 24
Finished Apr 28 04:24:41 PM PDT 24
Peak memory 255660 kb
Host smart-14a4893f-1341-4e6b-b118-c284bccd8434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40395
2717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.403952717
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.919024994
Short name T77
Test name
Test status
Simulation time 589224463 ps
CPU time 52.54 seconds
Started Apr 28 04:24:19 PM PDT 24
Finished Apr 28 04:25:12 PM PDT 24
Peak memory 248708 kb
Host smart-dd4e2e62-bc84-4574-8a46-182b03e91d3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91902
4994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.919024994
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.2746935182
Short name T584
Test name
Test status
Simulation time 310711916 ps
CPU time 22.52 seconds
Started Apr 28 04:24:23 PM PDT 24
Finished Apr 28 04:24:46 PM PDT 24
Peak memory 256812 kb
Host smart-681785d7-d480-413a-9b1c-f5d7e9d43f3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27469
35182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.2746935182
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.281681842
Short name T625
Test name
Test status
Simulation time 8693347642 ps
CPU time 47.17 seconds
Started Apr 28 04:24:14 PM PDT 24
Finished Apr 28 04:25:01 PM PDT 24
Peak memory 248788 kb
Host smart-e7c0d3fc-d03e-42d0-bc2d-75093e9538ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28168
1842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.281681842
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.964432604
Short name T25
Test name
Test status
Simulation time 68545158243 ps
CPU time 3857.64 seconds
Started Apr 28 04:24:23 PM PDT 24
Finished Apr 28 05:28:42 PM PDT 24
Peak memory 302140 kb
Host smart-efd730d1-9b0e-445b-934d-7246f8078adb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964432604 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.964432604
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.3652011394
Short name T508
Test name
Test status
Simulation time 23272789079 ps
CPU time 1545.7 seconds
Started Apr 28 04:24:38 PM PDT 24
Finished Apr 28 04:50:24 PM PDT 24
Peak memory 273412 kb
Host smart-625b09d8-6c25-4391-b38e-d6865bbb1bfb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652011394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.3652011394
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.3997582516
Short name T629
Test name
Test status
Simulation time 655342075 ps
CPU time 56.71 seconds
Started Apr 28 04:24:32 PM PDT 24
Finished Apr 28 04:25:29 PM PDT 24
Peak memory 256816 kb
Host smart-4ede6cce-8557-4607-9562-c91ed3365260
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39975
82516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.3997582516
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.3372767285
Short name T411
Test name
Test status
Simulation time 6971527993 ps
CPU time 69.54 seconds
Started Apr 28 04:24:32 PM PDT 24
Finished Apr 28 04:25:41 PM PDT 24
Peak memory 256144 kb
Host smart-f581ca10-4893-4e5c-b77e-3bb675ae81d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33727
67285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.3372767285
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.1041645284
Short name T295
Test name
Test status
Simulation time 103015815814 ps
CPU time 1293.46 seconds
Started Apr 28 04:24:37 PM PDT 24
Finished Apr 28 04:46:11 PM PDT 24
Peak memory 281596 kb
Host smart-b98d8bd8-cae6-47f5-878f-df2d9fd2adc4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041645284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.1041645284
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.545310483
Short name T50
Test name
Test status
Simulation time 64993772408 ps
CPU time 910.46 seconds
Started Apr 28 04:24:38 PM PDT 24
Finished Apr 28 04:39:49 PM PDT 24
Peak memory 270592 kb
Host smart-3b37981d-77a9-45fb-b675-22f12a08c327
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545310483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.545310483
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.1233383907
Short name T634
Test name
Test status
Simulation time 4564405984 ps
CPU time 196 seconds
Started Apr 28 04:24:37 PM PDT 24
Finished Apr 28 04:27:53 PM PDT 24
Peak memory 248004 kb
Host smart-162fa33e-245a-4e45-9941-4a2f25679487
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233383907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.1233383907
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.908630802
Short name T458
Test name
Test status
Simulation time 1800111057 ps
CPU time 29.82 seconds
Started Apr 28 04:24:28 PM PDT 24
Finished Apr 28 04:24:58 PM PDT 24
Peak memory 248688 kb
Host smart-57b90bd4-bc22-4683-8f07-308baf17cc6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90863
0802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.908630802
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.2992706112
Short name T497
Test name
Test status
Simulation time 848322318 ps
CPU time 64 seconds
Started Apr 28 04:24:28 PM PDT 24
Finished Apr 28 04:25:32 PM PDT 24
Peak memory 255852 kb
Host smart-9b617503-22ca-48eb-a5af-bb03e67165d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29927
06112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.2992706112
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.1055405901
Short name T560
Test name
Test status
Simulation time 332727252 ps
CPU time 24.6 seconds
Started Apr 28 04:24:38 PM PDT 24
Finished Apr 28 04:25:03 PM PDT 24
Peak memory 255856 kb
Host smart-30cc3dce-f669-4220-a059-ea92509b8f89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10554
05901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.1055405901
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.2732424540
Short name T480
Test name
Test status
Simulation time 991622900 ps
CPU time 35.88 seconds
Started Apr 28 04:24:24 PM PDT 24
Finished Apr 28 04:25:00 PM PDT 24
Peak memory 255908 kb
Host smart-736dc3cb-f2ac-4a44-9a31-31d463b612fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27324
24540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.2732424540
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.2905217679
Short name T103
Test name
Test status
Simulation time 40039637088 ps
CPU time 2861.96 seconds
Started Apr 28 04:24:39 PM PDT 24
Finished Apr 28 05:12:21 PM PDT 24
Peak memory 289696 kb
Host smart-8589e4f1-771f-4ac2-a09e-431463874e61
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905217679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.2905217679
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.395232748
Short name T545
Test name
Test status
Simulation time 246693639487 ps
CPU time 2472.07 seconds
Started Apr 28 04:24:50 PM PDT 24
Finished Apr 28 05:06:03 PM PDT 24
Peak memory 273372 kb
Host smart-77dfff22-b52d-42b2-9588-f96430f442c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395232748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.395232748
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.1782215964
Short name T238
Test name
Test status
Simulation time 16855937315 ps
CPU time 284.6 seconds
Started Apr 28 04:24:44 PM PDT 24
Finished Apr 28 04:29:29 PM PDT 24
Peak memory 256920 kb
Host smart-7dba5034-d56f-4b9d-a8f0-6e2efa996b18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17822
15964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.1782215964
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.2760048932
Short name T389
Test name
Test status
Simulation time 1376682525 ps
CPU time 33.07 seconds
Started Apr 28 04:24:44 PM PDT 24
Finished Apr 28 04:25:18 PM PDT 24
Peak memory 255772 kb
Host smart-7668bc43-678a-4c8c-b3cf-cb2881b5d78c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27600
48932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.2760048932
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.3968903963
Short name T312
Test name
Test status
Simulation time 213389501556 ps
CPU time 3111.27 seconds
Started Apr 28 04:24:50 PM PDT 24
Finished Apr 28 05:16:42 PM PDT 24
Peak memory 289052 kb
Host smart-100dc7a9-4bdd-45da-a622-6b7047fb7910
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968903963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.3968903963
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2713733667
Short name T452
Test name
Test status
Simulation time 442104093093 ps
CPU time 2466.88 seconds
Started Apr 28 04:24:55 PM PDT 24
Finished Apr 28 05:06:02 PM PDT 24
Peak memory 288616 kb
Host smart-4d343e93-c6b4-47d0-93a6-01dde6f480b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713733667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2713733667
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.2780466253
Short name T315
Test name
Test status
Simulation time 14779321579 ps
CPU time 407.09 seconds
Started Apr 28 04:24:50 PM PDT 24
Finished Apr 28 04:31:37 PM PDT 24
Peak memory 248080 kb
Host smart-a1fc92ff-16e2-4bb4-a8a0-288a5f62d620
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780466253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.2780466253
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.3044179206
Short name T535
Test name
Test status
Simulation time 1099383719 ps
CPU time 31.21 seconds
Started Apr 28 04:24:45 PM PDT 24
Finished Apr 28 04:25:17 PM PDT 24
Peak memory 256052 kb
Host smart-f369307b-0f25-4d8d-bdce-fcadaff4b1be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30441
79206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.3044179206
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.1529746768
Short name T491
Test name
Test status
Simulation time 53394130 ps
CPU time 5.71 seconds
Started Apr 28 04:24:47 PM PDT 24
Finished Apr 28 04:24:53 PM PDT 24
Peak memory 240440 kb
Host smart-5331870a-2e47-42a3-bfac-845acc910951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15297
46768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.1529746768
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.3416454985
Short name T570
Test name
Test status
Simulation time 2573361611 ps
CPU time 43.83 seconds
Started Apr 28 04:24:43 PM PDT 24
Finished Apr 28 04:25:27 PM PDT 24
Peak memory 256224 kb
Host smart-eb9ed002-623f-4252-9338-e0d614e69ed1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34164
54985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.3416454985
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.2456484745
Short name T435
Test name
Test status
Simulation time 134088725070 ps
CPU time 3843.31 seconds
Started Apr 28 04:24:55 PM PDT 24
Finished Apr 28 05:28:59 PM PDT 24
Peak memory 305468 kb
Host smart-9ec2379f-fbcb-4702-88a8-e6fd460d9fca
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456484745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.2456484745
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.723963328
Short name T566
Test name
Test status
Simulation time 15144025597 ps
CPU time 824.07 seconds
Started Apr 28 04:25:02 PM PDT 24
Finished Apr 28 04:38:47 PM PDT 24
Peak memory 265232 kb
Host smart-b4d7e133-8c4e-4f92-90ef-baa20d2f35e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723963328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.723963328
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.602637616
Short name T437
Test name
Test status
Simulation time 4736452428 ps
CPU time 299.48 seconds
Started Apr 28 04:25:02 PM PDT 24
Finished Apr 28 04:30:02 PM PDT 24
Peak memory 256464 kb
Host smart-fc63918e-7167-4abe-bf8f-7030126ce480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60263
7616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.602637616
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.1040111491
Short name T225
Test name
Test status
Simulation time 55459499 ps
CPU time 7.95 seconds
Started Apr 28 04:24:58 PM PDT 24
Finished Apr 28 04:25:06 PM PDT 24
Peak memory 248720 kb
Host smart-3aed7425-f67e-4f92-a889-68804cc51c14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10401
11491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.1040111491
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.2132524267
Short name T682
Test name
Test status
Simulation time 36096453482 ps
CPU time 1391.07 seconds
Started Apr 28 04:25:02 PM PDT 24
Finished Apr 28 04:48:14 PM PDT 24
Peak memory 288880 kb
Host smart-dd7b0c0a-6304-4b74-a79a-99a2317a3bee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132524267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.2132524267
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.427528250
Short name T221
Test name
Test status
Simulation time 69584687600 ps
CPU time 2295 seconds
Started Apr 28 04:25:02 PM PDT 24
Finished Apr 28 05:03:17 PM PDT 24
Peak memory 289004 kb
Host smart-d043c569-d502-4fcd-adf3-16b622263647
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427528250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.427528250
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.465354381
Short name T36
Test name
Test status
Simulation time 52365896486 ps
CPU time 574.77 seconds
Started Apr 28 04:25:03 PM PDT 24
Finished Apr 28 04:34:38 PM PDT 24
Peak memory 247996 kb
Host smart-bfcdf308-b84e-42da-a362-3082e75154f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465354381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.465354381
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.1341433479
Short name T651
Test name
Test status
Simulation time 409055633 ps
CPU time 45.31 seconds
Started Apr 28 04:24:58 PM PDT 24
Finished Apr 28 04:25:44 PM PDT 24
Peak memory 255904 kb
Host smart-9116a157-3ebe-4608-a0e5-6a555af4baf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13414
33479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.1341433479
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.2858002901
Short name T85
Test name
Test status
Simulation time 1639167246 ps
CPU time 27.56 seconds
Started Apr 28 04:24:58 PM PDT 24
Finished Apr 28 04:25:26 PM PDT 24
Peak memory 248696 kb
Host smart-f99c9473-3b96-4f79-a5a5-3668ffee182a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28580
02901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.2858002901
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.3072739951
Short name T113
Test name
Test status
Simulation time 745444961 ps
CPU time 44.92 seconds
Started Apr 28 04:25:02 PM PDT 24
Finished Apr 28 04:25:47 PM PDT 24
Peak memory 248676 kb
Host smart-29288c95-09d3-4c02-a9d5-7c9d640ff822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30727
39951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.3072739951
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.1338167469
Short name T441
Test name
Test status
Simulation time 3012551531 ps
CPU time 54.5 seconds
Started Apr 28 04:24:58 PM PDT 24
Finished Apr 28 04:25:53 PM PDT 24
Peak memory 248800 kb
Host smart-01b261ce-2be6-49c8-8f12-5af15c66cdf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13381
67469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1338167469
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.2955127491
Short name T119
Test name
Test status
Simulation time 16904286236 ps
CPU time 243.68 seconds
Started Apr 28 04:25:02 PM PDT 24
Finished Apr 28 04:29:06 PM PDT 24
Peak memory 255580 kb
Host smart-c2c60620-e699-428b-aee9-791147d2aaa7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955127491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.2955127491
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.3594145964
Short name T5
Test name
Test status
Simulation time 85063107365 ps
CPU time 6666.98 seconds
Started Apr 28 04:25:07 PM PDT 24
Finished Apr 28 06:16:15 PM PDT 24
Peak memory 354740 kb
Host smart-74d26dcd-31f8-4acf-8adc-0452b1f63e2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594145964 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.3594145964
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.2420306735
Short name T211
Test name
Test status
Simulation time 39122920 ps
CPU time 2.39 seconds
Started Apr 28 04:13:11 PM PDT 24
Finished Apr 28 04:13:13 PM PDT 24
Peak memory 248880 kb
Host smart-055b1dc6-ee30-4063-addc-3318d8ad34d8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2420306735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.2420306735
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.866308682
Short name T470
Test name
Test status
Simulation time 51650453663 ps
CPU time 1024.06 seconds
Started Apr 28 04:12:55 PM PDT 24
Finished Apr 28 04:30:00 PM PDT 24
Peak memory 271552 kb
Host smart-43b842e1-22c0-469b-baba-5f103d20dc6f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866308682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.866308682
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.1765401719
Short name T407
Test name
Test status
Simulation time 2892161206 ps
CPU time 34.2 seconds
Started Apr 28 04:13:12 PM PDT 24
Finished Apr 28 04:13:47 PM PDT 24
Peak memory 248736 kb
Host smart-d4c1a014-7ad2-47a0-a4ed-c6b3655c7e1f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1765401719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1765401719
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.4139536366
Short name T15
Test name
Test status
Simulation time 8240411710 ps
CPU time 141.56 seconds
Started Apr 28 04:12:53 PM PDT 24
Finished Apr 28 04:15:14 PM PDT 24
Peak memory 249328 kb
Host smart-fa1fb4e5-9cc3-4bcf-8110-20cb68ac7953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41395
36366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.4139536366
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.2255067803
Short name T233
Test name
Test status
Simulation time 177116266 ps
CPU time 13.31 seconds
Started Apr 28 04:12:55 PM PDT 24
Finished Apr 28 04:13:09 PM PDT 24
Peak memory 254036 kb
Host smart-211ac4a6-e867-4181-a43c-04bbbd51136d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22550
67803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.2255067803
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.2989467058
Short name T338
Test name
Test status
Simulation time 57137947050 ps
CPU time 1818.88 seconds
Started Apr 28 04:12:58 PM PDT 24
Finished Apr 28 04:43:18 PM PDT 24
Peak memory 281524 kb
Host smart-d5b00943-f5d5-4d49-8c09-f44ec8f58b03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989467058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2989467058
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.4200709423
Short name T105
Test name
Test status
Simulation time 88674627764 ps
CPU time 1976.53 seconds
Started Apr 28 04:13:00 PM PDT 24
Finished Apr 28 04:45:57 PM PDT 24
Peak memory 273424 kb
Host smart-485f78bc-f370-4c1c-9819-c7c693661073
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200709423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.4200709423
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.1802009145
Short name T311
Test name
Test status
Simulation time 15241254755 ps
CPU time 598.47 seconds
Started Apr 28 04:12:54 PM PDT 24
Finished Apr 28 04:22:52 PM PDT 24
Peak memory 248052 kb
Host smart-a38e6298-d4d6-40c4-9703-6be1f43d05e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802009145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.1802009145
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.1958181040
Short name T79
Test name
Test status
Simulation time 352380923 ps
CPU time 24.15 seconds
Started Apr 28 04:12:39 PM PDT 24
Finished Apr 28 04:13:03 PM PDT 24
Peak memory 248668 kb
Host smart-b546f9de-3cbd-4264-af15-6bc2f7effdcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19581
81040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1958181040
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.1816581152
Short name T486
Test name
Test status
Simulation time 719331387 ps
CPU time 37.49 seconds
Started Apr 28 04:12:44 PM PDT 24
Finished Apr 28 04:13:22 PM PDT 24
Peak memory 248696 kb
Host smart-b8d9e2d1-c98e-4548-ac4d-2ba98d48c429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18165
81152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.1816581152
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.35676121
Short name T469
Test name
Test status
Simulation time 950028420 ps
CPU time 67.52 seconds
Started Apr 28 04:12:51 PM PDT 24
Finished Apr 28 04:13:59 PM PDT 24
Peak memory 248924 kb
Host smart-5aa80e9a-534e-4689-beea-a82d944a62e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35676
121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.35676121
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.3132272154
Short name T419
Test name
Test status
Simulation time 660906712 ps
CPU time 42.57 seconds
Started Apr 28 04:12:28 PM PDT 24
Finished Apr 28 04:13:11 PM PDT 24
Peak memory 256004 kb
Host smart-029cf92b-3ca0-4851-9fbb-7362456866f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31322
72154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.3132272154
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.4040470502
Short name T108
Test name
Test status
Simulation time 47632987064 ps
CPU time 3324.6 seconds
Started Apr 28 04:13:13 PM PDT 24
Finished Apr 28 05:08:39 PM PDT 24
Peak memory 297884 kb
Host smart-8bcebebd-f83c-4417-9b51-4aae832dc1aa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040470502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.4040470502
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.3977712176
Short name T215
Test name
Test status
Simulation time 41780835 ps
CPU time 4.14 seconds
Started Apr 28 04:13:52 PM PDT 24
Finished Apr 28 04:13:57 PM PDT 24
Peak memory 248852 kb
Host smart-78c48ef5-2f0b-43a9-93a8-0a193db7d78c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3977712176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.3977712176
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.1950460335
Short name T45
Test name
Test status
Simulation time 243951057958 ps
CPU time 1973.4 seconds
Started Apr 28 04:13:34 PM PDT 24
Finished Apr 28 04:46:28 PM PDT 24
Peak memory 272600 kb
Host smart-2f28d979-4c28-4bc2-acd2-7e6c5c9e105f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950460335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.1950460335
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.306732606
Short name T54
Test name
Test status
Simulation time 176793825 ps
CPU time 11.1 seconds
Started Apr 28 04:13:43 PM PDT 24
Finished Apr 28 04:13:54 PM PDT 24
Peak memory 248736 kb
Host smart-fd29a525-ae03-48f2-a7ff-4605c5323b5f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=306732606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.306732606
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.787115462
Short name T432
Test name
Test status
Simulation time 34835388016 ps
CPU time 174.04 seconds
Started Apr 28 04:13:29 PM PDT 24
Finished Apr 28 04:16:24 PM PDT 24
Peak memory 249720 kb
Host smart-943774e3-4738-4569-96d9-234dbad7e2d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78711
5462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.787115462
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.1083847613
Short name T530
Test name
Test status
Simulation time 2642688589 ps
CPU time 45.54 seconds
Started Apr 28 04:13:23 PM PDT 24
Finished Apr 28 04:14:09 PM PDT 24
Peak memory 256912 kb
Host smart-a1e9c559-512e-4bd3-8b9e-8d99dd7ff179
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10838
47613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.1083847613
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.1797097565
Short name T439
Test name
Test status
Simulation time 100246375292 ps
CPU time 2826.63 seconds
Started Apr 28 04:13:43 PM PDT 24
Finished Apr 28 05:00:50 PM PDT 24
Peak memory 289104 kb
Host smart-17a0ae39-dbc8-4869-baee-dde7cb60d5a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797097565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.1797097565
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.3232263639
Short name T303
Test name
Test status
Simulation time 9454854113 ps
CPU time 199.74 seconds
Started Apr 28 04:13:42 PM PDT 24
Finished Apr 28 04:17:02 PM PDT 24
Peak memory 255816 kb
Host smart-68aed8c9-1688-4957-ab51-93b98efb8532
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232263639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.3232263639
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.2947781731
Short name T496
Test name
Test status
Simulation time 1876243619 ps
CPU time 64.79 seconds
Started Apr 28 04:13:29 PM PDT 24
Finished Apr 28 04:14:34 PM PDT 24
Peak memory 255860 kb
Host smart-ad2d40a3-daa4-44f2-8124-c8da663578f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29477
81731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.2947781731
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.3753198555
Short name T76
Test name
Test status
Simulation time 1142656887 ps
CPU time 14.83 seconds
Started Apr 28 04:13:23 PM PDT 24
Finished Apr 28 04:13:38 PM PDT 24
Peak memory 252668 kb
Host smart-728f48c8-e4e2-4bfa-aa09-f9c49fdf7b25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37531
98555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.3753198555
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.1045765522
Short name T393
Test name
Test status
Simulation time 2492854032 ps
CPU time 25.79 seconds
Started Apr 28 04:13:36 PM PDT 24
Finished Apr 28 04:14:02 PM PDT 24
Peak memory 256040 kb
Host smart-0c541de0-aaf6-4139-be58-24617ae1d387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10457
65522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.1045765522
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.2095892980
Short name T192
Test name
Test status
Simulation time 1194806903 ps
CPU time 30.68 seconds
Started Apr 28 04:13:16 PM PDT 24
Finished Apr 28 04:13:47 PM PDT 24
Peak memory 248712 kb
Host smart-4cb92d66-7204-4886-b029-1757461808a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20958
92980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.2095892980
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.940619641
Short name T121
Test name
Test status
Simulation time 6874012419 ps
CPU time 300.39 seconds
Started Apr 28 04:13:52 PM PDT 24
Finished Apr 28 04:18:53 PM PDT 24
Peak memory 265144 kb
Host smart-d0a46829-c1ab-4024-97b1-5f68257461c4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940619641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_hand
ler_stress_all.940619641
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.86312157
Short name T210
Test name
Test status
Simulation time 23840256 ps
CPU time 3.15 seconds
Started Apr 28 04:14:32 PM PDT 24
Finished Apr 28 04:14:35 PM PDT 24
Peak memory 248880 kb
Host smart-ab0887cd-a270-4ae5-b7ea-0912a2c9d0e8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=86312157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.86312157
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.1964646787
Short name T608
Test name
Test status
Simulation time 31568383567 ps
CPU time 1807.65 seconds
Started Apr 28 04:14:24 PM PDT 24
Finished Apr 28 04:44:32 PM PDT 24
Peak memory 285240 kb
Host smart-673153ff-a60f-4c02-9a32-b05a2c0b514f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964646787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.1964646787
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.2496868429
Short name T573
Test name
Test status
Simulation time 580507076 ps
CPU time 31.21 seconds
Started Apr 28 04:15:06 PM PDT 24
Finished Apr 28 04:15:38 PM PDT 24
Peak memory 248724 kb
Host smart-dc89804d-2851-4792-85cc-614b2cbfa88c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2496868429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.2496868429
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.3089235041
Short name T283
Test name
Test status
Simulation time 1988341293 ps
CPU time 66.31 seconds
Started Apr 28 04:14:13 PM PDT 24
Finished Apr 28 04:15:19 PM PDT 24
Peak memory 248752 kb
Host smart-8fb39232-7150-4cda-b343-66bd29e1bd14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30892
35041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.3089235041
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.1266546273
Short name T401
Test name
Test status
Simulation time 398502090 ps
CPU time 15.84 seconds
Started Apr 28 04:14:11 PM PDT 24
Finished Apr 28 04:14:27 PM PDT 24
Peak memory 255984 kb
Host smart-03004a4f-e489-4bb4-84af-0e8cf47e5808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12665
46273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.1266546273
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.2473893782
Short name T694
Test name
Test status
Simulation time 192914941063 ps
CPU time 2692.72 seconds
Started Apr 28 04:14:33 PM PDT 24
Finished Apr 28 04:59:26 PM PDT 24
Peak memory 286736 kb
Host smart-e9a6846a-2722-4aeb-a9b0-381da1b24aa7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473893782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.2473893782
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.4050102646
Short name T494
Test name
Test status
Simulation time 8422238286 ps
CPU time 792.11 seconds
Started Apr 28 04:14:43 PM PDT 24
Finished Apr 28 04:27:56 PM PDT 24
Peak memory 268324 kb
Host smart-93dd0989-c6f2-4a85-91c2-fcf9faf94726
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050102646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.4050102646
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.2346970141
Short name T325
Test name
Test status
Simulation time 12494394870 ps
CPU time 145.4 seconds
Started Apr 28 04:14:29 PM PDT 24
Finished Apr 28 04:16:55 PM PDT 24
Peak memory 248112 kb
Host smart-4e0b4644-70c1-4171-af8d-827f5322433d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346970141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.2346970141
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.242224471
Short name T410
Test name
Test status
Simulation time 870484661 ps
CPU time 19.05 seconds
Started Apr 28 04:14:10 PM PDT 24
Finished Apr 28 04:14:29 PM PDT 24
Peak memory 248736 kb
Host smart-78fa3693-96df-4416-bc5b-8dda9b8e5ae9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24222
4471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.242224471
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.2517633177
Short name T382
Test name
Test status
Simulation time 137739148 ps
CPU time 8.29 seconds
Started Apr 28 04:14:00 PM PDT 24
Finished Apr 28 04:14:09 PM PDT 24
Peak memory 252076 kb
Host smart-31a6b3bd-b02e-45b4-864f-811d0de8c0fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25176
33177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.2517633177
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.112100137
Short name T265
Test name
Test status
Simulation time 2071511770 ps
CPU time 64.13 seconds
Started Apr 28 04:14:18 PM PDT 24
Finished Apr 28 04:15:23 PM PDT 24
Peak memory 247576 kb
Host smart-540fb5d2-216d-43e9-9ce7-852107123c21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11210
0137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.112100137
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.3667729786
Short name T622
Test name
Test status
Simulation time 1180763337 ps
CPU time 37.86 seconds
Started Apr 28 04:13:50 PM PDT 24
Finished Apr 28 04:14:28 PM PDT 24
Peak memory 248688 kb
Host smart-5415fa89-e80c-496a-994a-e672aa1cc9f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36677
29786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.3667729786
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.451109486
Short name T112
Test name
Test status
Simulation time 89905082852 ps
CPU time 2713.64 seconds
Started Apr 28 04:14:35 PM PDT 24
Finished Apr 28 04:59:49 PM PDT 24
Peak memory 299588 kb
Host smart-586766c2-37a2-4fc2-a037-0dbcf0cec506
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451109486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_hand
ler_stress_all.451109486
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.1432514995
Short name T683
Test name
Test status
Simulation time 48768206524 ps
CPU time 1480.74 seconds
Started Apr 28 04:15:02 PM PDT 24
Finished Apr 28 04:39:43 PM PDT 24
Peak memory 289684 kb
Host smart-2defc6a1-c167-41f5-a884-46f3c92f6a66
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432514995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.1432514995
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.1197136777
Short name T40
Test name
Test status
Simulation time 835465354 ps
CPU time 12.94 seconds
Started Apr 28 04:15:07 PM PDT 24
Finished Apr 28 04:15:20 PM PDT 24
Peak memory 251288 kb
Host smart-fa13ad97-2e02-432f-b387-9631d0dfddb6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1197136777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.1197136777
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.2921401672
Short name T648
Test name
Test status
Simulation time 14820302590 ps
CPU time 181.64 seconds
Started Apr 28 04:14:55 PM PDT 24
Finished Apr 28 04:17:57 PM PDT 24
Peak memory 251368 kb
Host smart-fa52912f-fe92-475b-b0e9-d730495d10a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29214
01672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.2921401672
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.3943629805
Short name T397
Test name
Test status
Simulation time 1012224700 ps
CPU time 19.39 seconds
Started Apr 28 04:14:44 PM PDT 24
Finished Apr 28 04:15:04 PM PDT 24
Peak memory 255900 kb
Host smart-cae78322-4e74-460a-be46-beba5bda667d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39436
29805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3943629805
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.2705247950
Short name T343
Test name
Test status
Simulation time 34811604951 ps
CPU time 2379.7 seconds
Started Apr 28 04:15:22 PM PDT 24
Finished Apr 28 04:55:03 PM PDT 24
Peak memory 289112 kb
Host smart-75ec76cf-86d9-4e34-94ef-946d3baaa629
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705247950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.2705247950
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.4149414903
Short name T52
Test name
Test status
Simulation time 56672588592 ps
CPU time 1546.75 seconds
Started Apr 28 04:15:01 PM PDT 24
Finished Apr 28 04:40:48 PM PDT 24
Peak memory 281576 kb
Host smart-c50ea767-2f57-4f4b-b873-eab0de597677
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149414903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.4149414903
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.2766179535
Short name T395
Test name
Test status
Simulation time 2536035463 ps
CPU time 112.13 seconds
Started Apr 28 04:15:22 PM PDT 24
Finished Apr 28 04:17:14 PM PDT 24
Peak memory 254532 kb
Host smart-bfea9b7a-f81e-45d6-a6f3-e5d139df8ec5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766179535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.2766179535
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.3126747787
Short name T55
Test name
Test status
Simulation time 1000288819 ps
CPU time 48.22 seconds
Started Apr 28 04:14:42 PM PDT 24
Finished Apr 28 04:15:31 PM PDT 24
Peak memory 256020 kb
Host smart-80d4565f-f28a-4013-8d8f-459ec82f15f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31267
47787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.3126747787
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.574520792
Short name T417
Test name
Test status
Simulation time 971731254 ps
CPU time 16.88 seconds
Started Apr 28 04:14:46 PM PDT 24
Finished Apr 28 04:15:04 PM PDT 24
Peak memory 248984 kb
Host smart-b50da57c-8a8d-4aa4-a5eb-c254a53d140b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57452
0792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.574520792
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.181774020
Short name T404
Test name
Test status
Simulation time 161590175 ps
CPU time 11.59 seconds
Started Apr 28 04:15:02 PM PDT 24
Finished Apr 28 04:15:14 PM PDT 24
Peak memory 248700 kb
Host smart-d3123840-b5d8-4b6c-98cc-5b5dd1c45df8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18177
4020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.181774020
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.3013886146
Short name T380
Test name
Test status
Simulation time 99175199 ps
CPU time 11.11 seconds
Started Apr 28 04:14:38 PM PDT 24
Finished Apr 28 04:14:49 PM PDT 24
Peak memory 256040 kb
Host smart-147ac2e8-f13e-4469-bfed-2ef0a527b8d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30138
86146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.3013886146
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.2577370630
Short name T203
Test name
Test status
Simulation time 34535173 ps
CPU time 3.78 seconds
Started Apr 28 04:15:35 PM PDT 24
Finished Apr 28 04:15:40 PM PDT 24
Peak memory 248860 kb
Host smart-ecc6355a-5465-465e-a1a6-ea1c9c1bc12c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2577370630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.2577370630
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.1521010958
Short name T379
Test name
Test status
Simulation time 11772045914 ps
CPU time 961.8 seconds
Started Apr 28 04:15:38 PM PDT 24
Finished Apr 28 04:31:40 PM PDT 24
Peak memory 272820 kb
Host smart-3e6e71dc-e7d8-4cf1-97a8-9201efc30193
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521010958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.1521010958
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.360633784
Short name T388
Test name
Test status
Simulation time 1138798614 ps
CPU time 16.76 seconds
Started Apr 28 04:15:31 PM PDT 24
Finished Apr 28 04:15:48 PM PDT 24
Peak memory 248712 kb
Host smart-cc15cc31-90ba-4151-ad8d-72cec65315e9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=360633784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.360633784
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.2798867776
Short name T364
Test name
Test status
Simulation time 151021958 ps
CPU time 9.2 seconds
Started Apr 28 04:15:30 PM PDT 24
Finished Apr 28 04:15:40 PM PDT 24
Peak memory 249020 kb
Host smart-a218eb6b-9b48-4e63-ae7c-f29ac5795d05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27988
67776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.2798867776
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.2524590138
Short name T539
Test name
Test status
Simulation time 835660117 ps
CPU time 56.93 seconds
Started Apr 28 04:15:34 PM PDT 24
Finished Apr 28 04:16:32 PM PDT 24
Peak memory 256108 kb
Host smart-2853bd33-278f-439a-bef1-f41566ddf378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25245
90138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.2524590138
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.4089190202
Short name T589
Test name
Test status
Simulation time 75748029086 ps
CPU time 904.8 seconds
Started Apr 28 04:15:37 PM PDT 24
Finished Apr 28 04:30:43 PM PDT 24
Peak memory 272496 kb
Host smart-544dee02-ecf5-4f76-9c80-40148bc9851b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089190202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.4089190202
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.2627274911
Short name T630
Test name
Test status
Simulation time 106572618657 ps
CPU time 1666.15 seconds
Started Apr 28 04:15:35 PM PDT 24
Finished Apr 28 04:43:22 PM PDT 24
Peak memory 271864 kb
Host smart-8e9bb7b2-9643-4200-9e2e-a253cdaab181
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627274911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2627274911
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.2385690186
Short name T305
Test name
Test status
Simulation time 21996011890 ps
CPU time 235.24 seconds
Started Apr 28 04:15:34 PM PDT 24
Finished Apr 28 04:19:30 PM PDT 24
Peak memory 247012 kb
Host smart-c7e13685-7dc1-4af2-b6d2-aabd84932033
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385690186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.2385690186
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.1735193107
Short name T456
Test name
Test status
Simulation time 248887227 ps
CPU time 31.6 seconds
Started Apr 28 04:15:23 PM PDT 24
Finished Apr 28 04:15:54 PM PDT 24
Peak memory 255904 kb
Host smart-af20a3dd-909e-49bc-9010-c5f8b745c043
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17351
93107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.1735193107
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.4047178226
Short name T490
Test name
Test status
Simulation time 115452681 ps
CPU time 14.74 seconds
Started Apr 28 04:15:24 PM PDT 24
Finished Apr 28 04:15:39 PM PDT 24
Peak memory 248692 kb
Host smart-ac5c874b-6070-4ae0-beee-7fac5577b9ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40471
78226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.4047178226
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.1121879225
Short name T474
Test name
Test status
Simulation time 877483856 ps
CPU time 64.98 seconds
Started Apr 28 04:15:24 PM PDT 24
Finished Apr 28 04:16:29 PM PDT 24
Peak memory 255684 kb
Host smart-b44cda39-0dc5-47ef-b930-51e3e707bbcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11218
79225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.1121879225
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.4042696227
Short name T680
Test name
Test status
Simulation time 5587394304 ps
CPU time 464.96 seconds
Started Apr 28 04:15:32 PM PDT 24
Finished Apr 28 04:23:17 PM PDT 24
Peak memory 265168 kb
Host smart-04c22db3-5130-41d7-adc5-a52e42bbb689
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042696227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.4042696227
Directory /workspace/9.alert_handler_stress_all/latest
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