Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	89061	1			T48	7		T5	10		T6	123
class_i[0x1]	55619	1			T4	25		T5	53		T55	5
class_i[0x2]	60950	1			T19	4382		T4	16		T91	9
class_i[0x3]	55023	1			T5	19		T55	6		T95	191

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	64456	1			T19	1057		T4	9		T48	1
alert[0x1]	65296	1			T19	1151		T4	22		T48	1
alert[0x2]	63601	1			T19	1102		T4	7		T48	1
alert[0x3]	67300	1			T19	1072		T4	3		T48	4

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

260361

1

T19

4382

T4

41

T5

82

esc_ping_fail

292

1

T48

7

T49

3

T50

3

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	64367	1			T19	1057		T4	9		T5	21
esc_integrity_fail	alert[0x1]	65227	1			T19	1151		T4	22		T5	24
esc_integrity_fail	alert[0x2]	63528	1			T19	1102		T4	7		T5	18
esc_integrity_fail	alert[0x3]	67239	1			T19	1072		T4	3		T5	19
esc_ping_fail	alert[0x0]	89	1			T48	1		T50	1		T73	1
esc_ping_fail	alert[0x1]	69	1			T48	1		T49	1		T50	1
esc_ping_fail	alert[0x2]	73	1			T48	1		T49	1		T50	1
esc_ping_fail	alert[0x3]	61	1			T48	4		T49	1		T51	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	88998	1			T5	10		T6	123		T95	5
esc_integrity_fail	class_i[0x1]	55524	1			T4	25		T5	53		T55	5
esc_integrity_fail	class_i[0x2]	60894	1			T19	4382		T4	16		T91	9
esc_integrity_fail	class_i[0x3]	54945	1			T5	19		T55	6		T95	191
esc_ping_fail	class_i[0x0]	63	1			T48	7		T50	1		T26	1
esc_ping_fail	class_i[0x1]	95	1			T49	3		T50	1		T51	3
esc_ping_fail	class_i[0x2]	56	1			T50	1		T69	2		T298	1
esc_ping_fail	class_i[0x3]	78	1			T73	9		T69	1		T306	1