Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	2	38	95.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	2	38	95.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	74	1			T4	3		T15	1		T102	1
class_index[0x1]	55	1			T1	1		T10	1		T102	1
class_index[0x2]	68	1			T1	2		T44	1		T5	1
class_index[0x3]	75	1			T3	1		T10	1		T91	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	99	1			T10	1		T4	3		T44	1
intr_timeout_cnt[1]	60	1			T1	3		T10	1		T101	1
intr_timeout_cnt[2]	29	1			T91	1		T103	1		T22	1
intr_timeout_cnt[3]	19	1			T15	1		T102	1		T103	1
intr_timeout_cnt[4]	13	1			T3	1		T74	1		T257	1
intr_timeout_cnt[5]	10	1			T123	1		T124	1		T28	1
intr_timeout_cnt[6]	14	1			T103	1		T82	1		T124	2
intr_timeout_cnt[7]	11	1			T22	2		T193	1		T82	1
intr_timeout_cnt[8]	9	1			T102	1		T54	1		T28	1
intr_timeout_cnt[9]	8	1			T82	1		T258	1		T253	3

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	2	38	95.00	2

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x3]]	[intr_timeout_cnt[5]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	22	1			T4	3		T54	1		T105	1
class_index[0x0]	intr_timeout_cnt[1]	20	1			T22	1		T105	1		T81	2
class_index[0x0]	intr_timeout_cnt[2]	8	1			T22	1		T259	1		T258	2
class_index[0x0]	intr_timeout_cnt[3]	7	1			T15	1		T102	1		T260	1
class_index[0x0]	intr_timeout_cnt[4]	5	1			T261	1		T262	1		T263	2
class_index[0x0]	intr_timeout_cnt[5]	1	1			T264	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[6]	3	1			T103	1		T124	1		T41	1
class_index[0x0]	intr_timeout_cnt[7]	3	1			T22	1		T265	1		T30	1
class_index[0x0]	intr_timeout_cnt[8]	1	1			T28	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[9]	4	1			T82	1		T253	1		T43	1
class_index[0x1]	intr_timeout_cnt[0]	22	1			T68	1		T84	1		T257	1
class_index[0x1]	intr_timeout_cnt[1]	9	1			T1	1		T10	1		T104	1
class_index[0x1]	intr_timeout_cnt[2]	3	1			T120	1		T266	1		T267	1
class_index[0x1]	intr_timeout_cnt[3]	4	1			T103	1		T81	1		T75	1
class_index[0x1]	intr_timeout_cnt[4]	1	1			T118	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[5]	5	1			T124	1		T28	1		T118	1
class_index[0x1]	intr_timeout_cnt[6]	5	1			T265	2		T268	1		T31	1
class_index[0x1]	intr_timeout_cnt[7]	1	1			T82	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	3	1			T102	1		T54	1		T255	1
class_index[0x1]	intr_timeout_cnt[9]	2	1			T253	2		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	27	1			T44	1		T5	1		T20	1
class_index[0x2]	intr_timeout_cnt[1]	14	1			T1	2		T54	1		T124	1
class_index[0x2]	intr_timeout_cnt[2]	7	1			T91	1		T54	1		T81	1
class_index[0x2]	intr_timeout_cnt[3]	4	1			T193	1		T131	1		T255	2
class_index[0x2]	intr_timeout_cnt[4]	2	1			T74	1		T269	1		-	-
class_index[0x2]	intr_timeout_cnt[5]	4	1			T123	1		T39	1		T270	1
class_index[0x2]	intr_timeout_cnt[6]	5	1			T82	1		T124	1		T126	1
class_index[0x2]	intr_timeout_cnt[7]	2	1			T271	1		T255	1		-	-
class_index[0x2]	intr_timeout_cnt[8]	1	1			T272	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[9]	2	1			T258	1		T270	1		-	-
class_index[0x3]	intr_timeout_cnt[0]	28	1			T10	1		T91	1		T65	1
class_index[0x3]	intr_timeout_cnt[1]	17	1			T101	1		T133	2		T54	1
class_index[0x3]	intr_timeout_cnt[2]	11	1			T103	1		T85	1		T126	1
class_index[0x3]	intr_timeout_cnt[3]	4	1			T123	1		T47	1		T273	1
class_index[0x3]	intr_timeout_cnt[4]	5	1			T3	1		T257	1		T28	1
class_index[0x3]	intr_timeout_cnt[6]	1	1			T272	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[7]	5	1			T22	1		T193	1		T41	1
class_index[0x3]	intr_timeout_cnt[8]	4	1			T75	4		-	-		-	-