Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	363527	1			T1	29		T2	17		T3	8
all_values[1]	363527	1			T1	29		T2	17		T3	8
all_values[2]	363527	1			T1	29		T2	17		T3	8
all_values[3]	363527	1			T1	29		T2	17		T3	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

723451

1

T1

47

T2

18

T3

18

auto[1]

730657

1

T1

69

T2

50

T3

14

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

864070

1

T1

60

T2

62

T3

6

auto[1]

590038

1

T1

56

T2

6

T3

26

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	102746	1			T1	5		T2	1		T3	2
all_values[0]	auto[0]	auto[1]	78047	1			T1	5		T2	1		T3	4
all_values[0]	auto[1]	auto[0]	104260	1			T1	10		T2	10		T7	652
all_values[0]	auto[1]	auto[1]	78474	1			T1	9		T2	5		T3	2
all_values[1]	auto[0]	auto[0]	108253	1			T1	6		T2	2		T3	1
all_values[1]	auto[0]	auto[1]	72229	1			T1	6		T3	3		T7	215
all_values[1]	auto[1]	auto[0]	110403	1			T1	9		T2	15		T7	689
all_values[1]	auto[1]	auto[1]	72642	1			T1	8		T3	4		T7	234
all_values[2]	auto[0]	auto[0]	110109	1			T1	7		T2	10		T3	1
all_values[2]	auto[0]	auto[1]	71214	1			T1	6		T3	3		T7	351
all_values[2]	auto[1]	auto[0]	111115	1			T1	8		T2	7		T7	544
all_values[2]	auto[1]	auto[1]	71089	1			T1	8		T3	4		T7	322
all_values[3]	auto[0]	auto[0]	107773	1			T1	6		T2	4		T3	1
all_values[3]	auto[0]	auto[1]	73080	1			T1	6		T3	3		T7	1
all_values[3]	auto[1]	auto[0]	109411	1			T1	9		T2	13		T3	1
all_values[3]	auto[1]	auto[1]	73263	1			T1	8		T3	3		T7	1