Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	363527	1			T1	29		T2	17		T3	8
all_pins[1]	363527	1			T1	29		T2	17		T3	8
all_pins[2]	363527	1			T1	29		T2	17		T3	8
all_pins[3]	363527	1			T1	29		T2	17		T3	8

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1158640	1			T1	83		T2	63		T3	19
values[0x1]	295468	1			T1	33		T2	5		T3	13
transitions[0x0=>0x1]	196918	1			T1	21		T2	5		T3	6
transitions[0x1=>0x0]	197162	1			T1	21		T2	5		T3	6

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	285053	1			T1	20		T2	12		T3	6
all_pins[0]	values[0x1]	78474	1			T1	9		T2	5		T3	2
all_pins[0]	transitions[0x0=>0x1]	77797	1			T1	9		T2	5		T3	1
all_pins[0]	transitions[0x1=>0x0]	72830	1			T1	8		T3	2		T7	1
all_pins[1]	values[0x0]	290885	1			T1	21		T2	17		T3	4
all_pins[1]	values[0x1]	72642	1			T1	8		T3	4		T7	234
all_pins[1]	transitions[0x0=>0x1]	39626	1			T1	2		T3	3		T7	167
all_pins[1]	transitions[0x1=>0x0]	45458	1			T1	3		T2	5		T3	1
all_pins[2]	values[0x0]	292438	1			T1	21		T2	17		T3	4
all_pins[2]	values[0x1]	71089	1			T1	8		T3	4		T7	322
all_pins[2]	transitions[0x0=>0x1]	38711	1			T1	6		T3	1		T7	236
all_pins[2]	transitions[0x1=>0x0]	40264	1			T1	6		T3	1		T7	148
all_pins[3]	values[0x0]	290264	1			T1	21		T2	17		T3	5
all_pins[3]	values[0x1]	73263	1			T1	8		T3	3		T7	1
all_pins[3]	transitions[0x0=>0x1]	40784	1			T1	4		T3	1		T7	1
all_pins[3]	transitions[0x1=>0x0]	38610	1			T1	4		T3	2		T7	322