Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	275	1			T172	7		T173	4		T174	7
all_values[1]	275	1			T172	7		T173	4		T174	7
all_values[2]	275	1			T172	7		T173	4		T174	7
all_values[3]	275	1			T172	7		T173	4		T174	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

572

1

T172

17

T173

4

T174

11

auto[1]

528

1

T172

11

T173

12

T174

17

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

458

1

T172

16

T173

12

T174

13

auto[1]

642

1

T172

12

T173

4

T174

15

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

648

1

T172

18

T173

13

T174

17

auto[1]

452

1

T172

10

T173

3

T174

11

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

74

1

T172

1

T173

1

T174

1

all_values[0]

auto[0]

auto[0]

auto[1]

21

1

T172

1

T174

1

T341

1

all_values[0]

auto[0]

auto[1]

auto[0]

58

1

T172

2

T173

3

T174

1

all_values[0]

auto[0]

auto[1]

auto[1]

16

1

T252

1

T342

1

T343

1

all_values[0]

auto[1]

auto[0]

auto[1]

52

1

T172

2

T174

2

T252

1

all_values[0]

auto[1]

auto[1]

auto[1]

54

1

T172

1

T174

2

T252

1

all_values[1]

auto[0]

auto[0]

auto[0]

50

1

T172

1

T174

1

T344

2

all_values[1]

auto[0]

auto[0]

auto[1]

25

1

T172

1

T341

2

T345

1

all_values[1]

auto[0]

auto[1]

auto[0]

57

1

T172

3

T174

2

T252

2

all_values[1]

auto[0]

auto[1]

auto[1]

35

1

T173

1

T174

2

T252

1

all_values[1]

auto[1]

auto[0]

auto[1]

61

1

T172

2

T173

3

T252

1

all_values[1]

auto[1]

auto[1]

auto[1]

47

1

T174

2

T344

2

T346

3

all_values[2]

auto[0]

auto[0]

auto[0]

60

1

T172

5

T174

3

T344

2

all_values[2]

auto[0]

auto[0]

auto[1]

23

1

T347

1

T348

1

T341

1

all_values[2]

auto[0]

auto[1]

auto[0]

58

1

T173

4

T174

2

T346

1

all_values[2]

auto[0]

auto[1]

auto[1]

21

1

T252

1

T344

1

T346

1

all_values[2]

auto[1]

auto[0]

auto[1]

61

1

T172

2

T174

1

T347

1

all_values[2]

auto[1]

auto[1]

auto[1]

52

1

T174

1

T252

3

T344

1

all_values[3]

auto[0]

auto[0]

auto[0]

59

1

T174

1

T346

2

T348

1

all_values[3]

auto[0]

auto[0]

auto[1]

22

1

T174

1

T342

1

T348

1

all_values[3]

auto[0]

auto[1]

auto[0]

42

1

T172

4

T173

4

T174

2

all_values[3]

auto[0]

auto[1]

auto[1]

27

1

T252

1

T344

1

T341

1

all_values[3]

auto[1]

auto[0]

auto[1]

64

1

T172

2

T252

1

T344

2

all_values[3]

auto[1]

auto[1]

auto[1]

61

1

T172

1

T174

3

T252

2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal