Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	93599	1			T8	909		T19	1206		T52	549
accum_cnt_1000	240323	1			T7	2243		T8	1417		T9	803
accum_cnt_100	28867	1			T7	239		T8	82		T16	11
accum_cnt_50	61416	1			T1	20		T7	164		T10	22
accum_cnt_10	161726	1			T1	38		T2	7		T3	30
accum_cnt_0	435598	1			T1	54		T2	53		T3	6

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	267522	1			T1	28		T2	15		T3	9
class_index[0x1]	267522	1			T1	28		T2	15		T3	9
class_index[0x2]	267522	1			T1	28		T2	15		T3	9
class_index[0x3]	267522	1			T1	28		T2	15		T3	9

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	26711	1			T8	320		T55	315		T56	598
class_index[0x0]	accum_cnt_1000	67959	1			T8	827		T9	803		T4	510
class_index[0x0]	accum_cnt_100	7922	1			T8	52		T16	11		T9	147
class_index[0x0]	accum_cnt_50	13933	1			T1	12		T8	35		T16	9
class_index[0x0]	accum_cnt_10	46545	1			T1	15		T2	7		T3	7
class_index[0x0]	accum_cnt_0	90007	1			T1	1		T2	8		T3	2
class_index[0x1]	accum_cnt_2000	23085	1			T8	589		T19	626		T52	549
class_index[0x1]	accum_cnt_1000	56263	1			T7	1051		T8	590		T19	549
class_index[0x1]	accum_cnt_100	6063	1			T7	163		T8	30		T19	30
class_index[0x1]	accum_cnt_50	11379	1			T7	104		T8	29		T19	28
class_index[0x1]	accum_cnt_10	46011	1			T1	7		T3	9		T7	27
class_index[0x1]	accum_cnt_0	112151	1			T1	21		T2	15		T7	5
class_index[0x2]	accum_cnt_2000	20199	1			T56	577		T27	300		T54	88
class_index[0x2]	accum_cnt_1000	49372	1			T7	1192		T4	294		T77	4
class_index[0x2]	accum_cnt_100	6075	1			T7	76		T4	184		T77	27
class_index[0x2]	accum_cnt_50	16480	1			T1	8		T7	60		T10	22
class_index[0x2]	accum_cnt_10	43513	1			T1	16		T3	7		T7	14
class_index[0x2]	accum_cnt_0	121972	1			T1	4		T2	15		T3	2
class_index[0x3]	accum_cnt_2000	23604	1			T19	580		T58	608		T63	494
class_index[0x3]	accum_cnt_1000	66729	1			T19	515		T72	906		T77	4
class_index[0x3]	accum_cnt_100	8807	1			T19	29		T4	162		T72	94
class_index[0x3]	accum_cnt_50	19624	1			T8	1243		T19	25		T4	135
class_index[0x3]	accum_cnt_10	25657	1			T3	7		T10	30		T8	11
class_index[0x3]	accum_cnt_0	111468	1			T1	28		T2	15		T3	2