Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	69	0	69	100.00
Crosses	260	0	260	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_cause_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
alert_cause_cross_class_index	260	0	260	100.00	100	1	1	0

Summary for Variable alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	31731	1			T10	5		T19	238		T4	107
alert[0x1]	31028	1			T1	1		T3	2		T10	8
alert[0x2]	29514	1			T10	8		T19	187		T4	262
alert[0x3]	32989	1			T3	1		T10	7		T8	217
alert[0x4]	30190	1			T3	1		T10	1		T8	193
alert[0x5]	36701	1			T1	9		T3	2		T7	451
alert[0x6]	33567	1			T10	3		T16	1		T19	187
alert[0x7]	35389	1			T3	1		T10	11		T8	222
alert[0x8]	35163	1			T1	1		T3	2		T7	1
alert[0x9]	31218	1			T10	1		T8	210		T19	222
alert[0xa]	39417	1			T3	2		T10	6		T8	208
alert[0xb]	30512	1			T1	8		T3	1		T10	3
alert[0xc]	30853	1			T1	5		T3	1		T10	7
alert[0xd]	33816	1			T1	7		T10	10		T8	227
alert[0xe]	32032	1			T1	7		T3	1		T10	1
alert[0xf]	30306	1			T1	4		T3	1		T10	1
alert[0x10]	30915	1			T10	3		T19	191		T4	72
alert[0x11]	30208	1			T1	2		T3	1		T10	3
alert[0x12]	31266	1			T1	10		T3	1		T10	4
alert[0x13]	34452	1			T1	2		T10	1		T8	208
alert[0x14]	35936	1			T3	2		T7	447		T10	7
alert[0x15]	38186	1			T1	11		T10	4		T8	1
alert[0x16]	36135	1			T1	1		T10	2		T8	237
alert[0x17]	31194	1			T1	8		T3	1		T10	2
alert[0x18]	31198	1			T1	4		T10	8		T8	1
alert[0x19]	32239	1			T3	2		T10	10		T8	207
alert[0x1a]	32460	1			T1	3		T10	4		T8	222
alert[0x1b]	30793	1			T1	8		T10	2		T8	205
alert[0x1c]	33939	1			T1	10		T3	2		T10	4
alert[0x1d]	35274	1			T3	1		T10	5		T9	5
alert[0x1e]	31848	1			T1	5		T10	1		T8	1
alert[0x1f]	33886	1			T1	6		T10	4		T16	8
alert[0x20]	33687	1			T1	6		T10	1		T8	240
alert[0x21]	31505	1			T1	5		T10	9		T16	8
alert[0x22]	36069	1			T1	1		T3	2		T10	2
alert[0x23]	30202	1			T1	2		T10	2		T8	216
alert[0x24]	31072	1			T1	7		T3	2		T10	6
alert[0x25]	32479	1			T1	3		T3	1		T10	6
alert[0x26]	31918	1			T1	1		T3	1		T8	217
alert[0x27]	29153	1			T8	231		T16	1		T19	200
alert[0x28]	32935	1			T3	2		T7	1		T10	1
alert[0x29]	32483	1			T10	3		T8	222		T16	5
alert[0x2a]	33971	1			T3	3		T10	5		T8	210
alert[0x2b]	35340	1			T1	1		T3	2		T10	2
alert[0x2c]	38006	1			T1	8		T7	2		T10	2
alert[0x2d]	33252	1			T1	8		T3	1		T7	1
alert[0x2e]	34683	1			T1	7		T7	2		T10	7
alert[0x2f]	33109	1			T1	7		T7	446		T10	4
alert[0x30]	35001	1			T1	6		T7	450		T10	5
alert[0x31]	28944	1			T1	8		T3	3		T10	3
alert[0x32]	32966	1			T1	1		T19	211		T4	218
alert[0x33]	30182	1			T1	2		T3	1		T10	7
alert[0x34]	33358	1			T3	2		T10	8		T8	227
alert[0x35]	31808	1			T1	1		T3	1		T10	9
alert[0x36]	30215	1			T2	6		T10	6		T8	1
alert[0x37]	30506	1			T1	8		T10	9		T16	5
alert[0x38]	33022	1			T10	1		T8	225		T16	9
alert[0x39]	31250	1			T1	8		T3	4		T16	7
alert[0x3a]	30729	1			T1	4		T3	2		T10	2
alert[0x3b]	29818	1			T3	2		T10	6		T16	9
alert[0x3c]	32059	1			T3	1		T10	2		T8	223
alert[0x3d]	31759	1			T1	3		T10	1		T8	236
alert[0x3e]	30774	1			T1	2		T3	1		T10	3
alert[0x3f]	31079	1			T1	4		T3	1		T10	4
alert[0x40]	34731	1			T3	1		T10	1		T8	210

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	607465	1			T1	57		T2	6		T3	7
class_i[0x1]	514036	1			T1	53		T3	21		T7	447
class_i[0x2]	499147	1			T1	36		T3	12		T7	899
class_i[0x3]	501772	1			T1	69		T3	18		T7	2

---

Summary for Cross alert_cause_cross_class_index

Samples crossed: alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	260	0	260	100.00

Automatically Generated Cross Bins for alert_cause_cross_class_index

Bins

alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	class_i[0x0]	10116	1			T4	33		T44	5		T34	4
alert[0x0]	class_i[0x1]	7697	1			T10	5		T34	1		T35	1
alert[0x0]	class_i[0x2]	7584	1			T19	238		T4	73		T24	8
alert[0x0]	class_i[0x3]	6334	1			T4	1		T35	35		T40	35
alert[0x1]	class_i[0x0]	9642	1			T10	1		T16	1		T19	182
alert[0x1]	class_i[0x1]	7909	1			T3	2		T8	1		T4	137
alert[0x1]	class_i[0x2]	7720	1			T1	1		T10	6		T8	214
alert[0x1]	class_i[0x3]	5757	1			T10	1		T4	2		T35	3
alert[0x2]	class_i[0x0]	9233	1			T4	65		T17	8		T34	1
alert[0x2]	class_i[0x1]	8340	1			T19	187		T4	156		T24	4
alert[0x2]	class_i[0x2]	5084	1			T4	37		T34	3		T5	3
alert[0x2]	class_i[0x3]	6857	1			T10	8		T4	4		T44	1
alert[0x3]	class_i[0x0]	6925	1			T10	2		T16	8		T4	83
alert[0x3]	class_i[0x1]	9037	1			T8	217		T4	46		T44	1
alert[0x3]	class_i[0x2]	8701	1			T10	5		T19	206		T34	3
alert[0x3]	class_i[0x3]	8326	1			T3	1		T4	1		T52	505
alert[0x4]	class_i[0x0]	8163	1			T8	193		T16	8		T4	59
alert[0x4]	class_i[0x1]	8777	1			T10	1		T19	1		T4	84
alert[0x4]	class_i[0x2]	8316	1			T4	37		T24	2		T35	2
alert[0x4]	class_i[0x3]	4934	1			T3	1		T19	211		T4	3
alert[0x5]	class_i[0x0]	9788	1			T7	451		T16	3		T19	1
alert[0x5]	class_i[0x1]	10923	1			T10	2		T4	35		T24	1
alert[0x5]	class_i[0x2]	8100	1			T19	199		T4	17		T52	1
alert[0x5]	class_i[0x3]	7890	1			T1	9		T3	2		T4	2
alert[0x6]	class_i[0x0]	9092	1			T16	1		T4	48		T34	4
alert[0x6]	class_i[0x1]	8598	1			T4	4		T24	7		T52	1
alert[0x6]	class_i[0x2]	9497	1			T10	1		T19	187		T4	1
alert[0x6]	class_i[0x3]	6380	1			T10	2		T4	66		T34	2
alert[0x7]	class_i[0x0]	10223	1			T10	7		T16	1		T4	63
alert[0x7]	class_i[0x1]	9025	1			T3	1		T10	1		T19	191
alert[0x7]	class_i[0x2]	6959	1			T10	1		T4	1		T34	1
alert[0x7]	class_i[0x3]	9182	1			T10	2		T8	222		T4	54
alert[0x8]	class_i[0x0]	9875	1			T16	6		T19	207		T4	4
alert[0x8]	class_i[0x1]	8649	1			T1	1		T8	208		T4	131
alert[0x8]	class_i[0x2]	8499	1			T3	2		T7	1		T10	2
alert[0x8]	class_i[0x3]	8140	1			T10	1		T4	1		T34	1
alert[0x9]	class_i[0x0]	7870	1			T19	222		T4	39		T17	1
alert[0x9]	class_i[0x1]	9826	1			T8	210		T76	1		T35	2
alert[0x9]	class_i[0x2]	6850	1			T4	2		T18	1		T35	32
alert[0x9]	class_i[0x3]	6672	1			T10	1		T4	59		T44	4
alert[0xa]	class_i[0x0]	12410	1			T3	1		T10	1		T9	357
alert[0xa]	class_i[0x1]	9428	1			T3	1		T10	2		T19	178
alert[0xa]	class_i[0x2]	8588	1			T10	3		T8	1		T24	1
alert[0xa]	class_i[0x3]	8991	1			T8	207		T19	1		T24	1
alert[0xb]	class_i[0x0]	6933	1			T4	7		T17	6		T34	2
alert[0xb]	class_i[0x1]	7620	1			T4	2		T34	1		T76	1
alert[0xb]	class_i[0x2]	7545	1			T1	8		T10	1		T8	1
alert[0xb]	class_i[0x3]	8414	1			T3	1		T10	2		T19	216
alert[0xc]	class_i[0x0]	8603	1			T10	7		T16	1		T4	5
alert[0xc]	class_i[0x1]	7773	1			T19	184		T4	19		T24	6
alert[0xc]	class_i[0x2]	7264	1			T1	5		T3	1		T8	225
alert[0xc]	class_i[0x3]	7213	1			T4	2		T40	31		T55	172
alert[0xd]	class_i[0x0]	8450	1			T16	10		T19	209		T4	6
alert[0xd]	class_i[0x1]	8731	1			T10	10		T8	227		T19	1
alert[0xd]	class_i[0x2]	7850	1			T1	7		T4	56		T34	1
alert[0xd]	class_i[0x3]	8785	1			T4	3		T34	1		T76	4
alert[0xe]	class_i[0x0]	10791	1			T10	1		T16	6		T4	13
alert[0xe]	class_i[0x1]	6960	1			T19	206		T4	82		T34	1
alert[0xe]	class_i[0x2]	6490	1			T24	1		T35	1		T58	1
alert[0xe]	class_i[0x3]	7791	1			T1	7		T3	1		T8	250
alert[0xf]	class_i[0x0]	9020	1			T1	3		T8	190		T16	7
alert[0xf]	class_i[0x1]	8050	1			T4	1		T24	1		T44	5
alert[0xf]	class_i[0x2]	7398	1			T3	1		T4	1		T24	2
alert[0xf]	class_i[0x3]	5838	1			T1	1		T10	1		T19	175
alert[0x10]	class_i[0x0]	9096	1			T4	68		T40	30		T297	1
alert[0x10]	class_i[0x1]	6900	1			T4	1		T34	2		T52	464
alert[0x10]	class_i[0x2]	9006	1			T10	2		T19	191		T4	1
alert[0x10]	class_i[0x3]	5913	1			T10	1		T4	2		T58	1
alert[0x11]	class_i[0x0]	9213	1			T10	2		T16	7		T4	15
alert[0x11]	class_i[0x1]	7520	1			T1	2		T19	209		T4	62
alert[0x11]	class_i[0x2]	6081	1			T10	1		T4	67		T34	1
alert[0x11]	class_i[0x3]	7394	1			T3	1		T44	7		T52	501
alert[0x12]	class_i[0x0]	10943	1			T1	10		T10	3		T16	1
alert[0x12]	class_i[0x1]	7578	1			T3	1		T4	1		T34	3
alert[0x12]	class_i[0x2]	6929	1			T4	2		T44	1		T52	1
alert[0x12]	class_i[0x3]	5816	1			T10	1		T19	1		T4	13
alert[0x13]	class_i[0x0]	9489	1			T16	5		T9	2		T4	4
alert[0x13]	class_i[0x1]	9035	1			T1	1		T8	1		T9	1
alert[0x13]	class_i[0x2]	7220	1			T8	207		T4	196		T34	4
alert[0x13]	class_i[0x3]	8708	1			T1	1		T10	1		T4	69
alert[0x14]	class_i[0x0]	7195	1			T3	1		T8	201		T4	8
alert[0x14]	class_i[0x1]	8112	1			T3	1		T7	446		T10	7
alert[0x14]	class_i[0x2]	10852	1			T4	22		T24	4		T34	7
alert[0x14]	class_i[0x3]	9777	1			T7	1		T8	1		T19	199
alert[0x15]	class_i[0x0]	9423	1			T10	3		T16	9		T19	1
alert[0x15]	class_i[0x1]	10530	1			T1	11		T19	202		T4	46
alert[0x15]	class_i[0x2]	8661	1			T10	1		T8	1		T4	1
alert[0x15]	class_i[0x3]	9572	1			T4	1		T44	2		T35	1
alert[0x16]	class_i[0x0]	11320	1			T16	6		T4	8		T17	7
alert[0x16]	class_i[0x1]	8695	1			T10	2		T8	237		T4	148
alert[0x16]	class_i[0x2]	7587	1			T34	1		T18	3		T77	31
alert[0x16]	class_i[0x3]	8533	1			T1	1		T19	225		T4	1
alert[0x17]	class_i[0x0]	9768	1			T10	1		T16	6		T4	69
alert[0x17]	class_i[0x1]	7574	1			T1	8		T10	1		T8	221
alert[0x17]	class_i[0x2]	7731	1			T4	2		T34	1		T76	1
alert[0x17]	class_i[0x3]	6121	1			T3	1		T34	8		T35	1
alert[0x18]	class_i[0x0]	10589	1			T1	2		T10	1		T16	5
alert[0x18]	class_i[0x1]	7706	1			T10	6		T19	231		T4	146
alert[0x18]	class_i[0x2]	6931	1			T1	2		T10	1		T4	57
alert[0x18]	class_i[0x3]	5972	1			T8	1		T24	1		T76	2
alert[0x19]	class_i[0x0]	7879	1			T16	6		T4	109		T17	8
alert[0x19]	class_i[0x1]	7485	1			T3	2		T4	74		T24	2
alert[0x19]	class_i[0x2]	7171	1			T10	10		T4	41		T24	1
alert[0x19]	class_i[0x3]	9704	1			T8	207		T19	195		T4	54
alert[0x1a]	class_i[0x0]	8946	1			T16	6		T4	4		T17	4
alert[0x1a]	class_i[0x1]	6181	1			T1	1		T4	81		T5	35
alert[0x1a]	class_i[0x2]	7156	1			T1	2		T10	4		T44	1
alert[0x1a]	class_i[0x3]	10177	1			T8	222		T19	214		T4	1
alert[0x1b]	class_i[0x0]	9102	1			T4	58		T44	4		T18	33
alert[0x1b]	class_i[0x1]	7154	1			T1	8		T8	205		T4	4
alert[0x1b]	class_i[0x2]	7721	1			T10	1		T19	204		T34	4
alert[0x1b]	class_i[0x3]	6816	1			T10	1		T4	1		T24	6
alert[0x1c]	class_i[0x0]	11200	1			T1	1		T10	4		T16	3
alert[0x1c]	class_i[0x1]	6928	1			T8	228		T34	3		T52	1
alert[0x1c]	class_i[0x2]	7251	1			T3	1		T4	15		T34	1
alert[0x1c]	class_i[0x3]	8560	1			T1	9		T3	1		T19	194
alert[0x1d]	class_i[0x0]	7604	1			T10	4		T9	1		T4	6
alert[0x1d]	class_i[0x1]	7405	1			T9	1		T4	64		T5	4
alert[0x1d]	class_i[0x2]	9822	1			T10	1		T9	2		T34	1
alert[0x1d]	class_i[0x3]	10443	1			T3	1		T9	1		T19	218
alert[0x1e]	class_i[0x0]	10049	1			T8	1		T16	1		T19	202
alert[0x1e]	class_i[0x1]	6596	1			T19	1		T4	1		T34	1
alert[0x1e]	class_i[0x2]	8085	1			T10	1		T34	1		T58	1
alert[0x1e]	class_i[0x3]	7118	1			T1	5		T4	88		T35	1
alert[0x1f]	class_i[0x0]	10211	1			T1	6		T16	8		T4	6
alert[0x1f]	class_i[0x1]	8100	1			T4	74		T76	1		T18	33
alert[0x1f]	class_i[0x2]	6969	1			T4	2		T77	2		T5	34
alert[0x1f]	class_i[0x3]	8606	1			T10	4		T19	224		T4	1
alert[0x20]	class_i[0x0]	9324	1			T1	1		T16	1		T19	223
alert[0x20]	class_i[0x1]	8852	1			T1	3		T4	1		T24	1
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alert[0x24]	class_i[0x2]	7004	1			T4	1		T40	33		T5	2
alert[0x24]	class_i[0x3]	8280	1			T10	6		T8	218		T4	69
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alert[0x25]	class_i[0x1]	9396	1			T3	1		T10	1		T24	4
alert[0x25]	class_i[0x2]	6083	1			T10	3		T19	194		T4	143
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