Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	3445	1			T27	2		T54	608		T36	62
alert[0x1]	5784	1			T48	1		T5	9		T55	20
alert[0x2]	3188	1			T4	24		T65	10		T27	50
alert[0x3]	6743	1			T8	2		T5	153		T55	16
alert[0x4]	3637	1			T55	159		T27	111		T73	1
alert[0x5]	1574	1			T7	3		T68	5		T22	48
alert[0x6]	10550	1			T56	50		T27	6		T54	171
alert[0x7]	4533	1			T5	15		T55	177		T22	2
alert[0x8]	6120	1			T95	7		T298	1		T296	1
alert[0x9]	4908	1			T55	28		T250	1		T51	1
alert[0xa]	2782	1			T296	1		T70	1		T249	1
alert[0xb]	5991	1			T55	10		T15	3		T26	1
alert[0xc]	5635	1			T48	1		T22	154		T36	80
alert[0xd]	12439	1			T8	9		T55	12		T50	1
alert[0xe]	8527	1			T55	48		T250	1		T68	4
alert[0xf]	8733	1			T3	2		T48	1		T5	419
alert[0x10]	3425	1			T48	1		T55	37		T103	1
alert[0x11]	4339	1			T5	2		T68	2		T36	8
alert[0x12]	15403	1			T36	70		T81	117		T11	31
alert[0x13]	3225	1			T48	1		T5	20		T54	13
alert[0x14]	8146	1			T4	14		T48	1		T55	18
alert[0x15]	4999	1			T55	159		T22	125		T36	312
alert[0x16]	5576	1			T48	1		T49	1		T67	1
alert[0x17]	6615	1			T48	1		T5	64		T55	27
alert[0x18]	3725	1			T55	33		T26	2		T22	39
alert[0x19]	8052	1			T49	2		T250	1		T26	13
alert[0x1a]	8279	1			T55	175		T49	1		T250	3
alert[0x1b]	4392	1			T49	1		T50	1		T54	88
alert[0x1c]	8243	1			T8	1		T48	1		T5	5
alert[0x1d]	9097	1			T5	11		T68	2		T22	43
alert[0x1e]	8765	1			T5	14		T56	2		T51	1
alert[0x1f]	3396	1			T4	4		T48	1		T55	239
alert[0x20]	2035	1			T27	10		T54	3		T298	1
alert[0x21]	9926	1			T5	2		T15	4		T68	1
alert[0x22]	4486	1			T5	11		T68	1		T67	1
alert[0x23]	3632	1			T5	7		T65	5		T27	25
alert[0x24]	4336	1			T48	1		T5	55		T65	3
alert[0x25]	3820	1			T4	13		T5	23		T95	33
alert[0x26]	4291	1			T54	154		T36	131		T105	1
alert[0x27]	2887	1			T48	1		T5	12		T65	1
alert[0x28]	7138	1			T72	1		T5	8		T55	87
alert[0x29]	7447	1			T5	58		T51	1		T54	31
alert[0x2a]	7506	1			T26	1		T27	3		T36	69
alert[0x2b]	4065	1			T5	25		T55	82		T49	1
alert[0x2c]	6049	1			T48	1		T95	3		T54	26
alert[0x2d]	4528	1			T55	9		T49	1		T22	2
alert[0x2e]	8963	1			T55	42		T95	1		T56	2
alert[0x2f]	7120	1			T19	1		T4	1		T55	34
alert[0x30]	8477	1			T7	1		T4	1		T5	21
alert[0x31]	14016	1			T5	29		T51	1		T22	4305
alert[0x32]	7795	1			T55	2		T36	2512		T239	3
alert[0x33]	9724	1			T8	1		T48	1		T5	8
alert[0x34]	8435	1			T5	7		T55	12		T65	2
alert[0x35]	10602	1			T65	2		T27	4		T54	447
alert[0x36]	3446	1			T4	36		T5	1		T55	6
alert[0x37]	3428	1			T3	2		T48	1		T55	61
alert[0x38]	6369	1			T36	230		T298	1		T53	2685
alert[0x39]	1167	1			T26	2		T27	4		T73	1
alert[0x3a]	6566	1			T8	13		T48	1		T5	2
alert[0x3b]	4419	1			T91	6		T55	32		T65	32
alert[0x3c]	4700	1			T49	1		T26	2		T22	7
alert[0x3d]	5462	1			T48	1		T5	29		T55	16
alert[0x3e]	9138	1			T5	81		T55	5		T27	4
alert[0x3f]	3042	1			T91	1		T55	3		T95	9
alert[0x40]	5471	1			T95	4		T64	12		T54	137

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	70202	1			T3	4		T8	1		T19	1
class_i[0x1]	97590	1			T7	4		T8	25		T55	1588
class_i[0x2]	104371	1			T4	4		T5	1054		T95	40
class_i[0x3]	128589	1			T4	53		T72	1		T48	15

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

400020

1

T3

4

T8

26

T19

1

alert_ping_fail

732

1

T7

4

T72

1

T48

17

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	3437	1			T27	2		T54	608		T36	62
alert_integrity_fail	alert[0x1]	5765	1			T5	9		T55	20		T54	8
alert_integrity_fail	alert[0x2]	3178	1			T4	24		T65	10		T27	50
alert_integrity_fail	alert[0x3]	6736	1			T8	2		T5	153		T55	16
alert_integrity_fail	alert[0x4]	3624	1			T55	159		T27	111		T36	20
alert_integrity_fail	alert[0x5]	1559	1			T68	5		T22	48		T47	1
alert_integrity_fail	alert[0x6]	10539	1			T56	50		T27	6		T54	171
alert_integrity_fail	alert[0x7]	4524	1			T5	15		T55	177		T22	2
alert_integrity_fail	alert[0x8]	6104	1			T95	7		T53	135		T74	3
alert_integrity_fail	alert[0x9]	4897	1			T55	28		T250	1		T36	101
alert_integrity_fail	alert[0xa]	2768	1			T11	123		T299	42		T294	110
alert_integrity_fail	alert[0xb]	5978	1			T55	10		T15	3		T26	1
alert_integrity_fail	alert[0xc]	5626	1			T22	154		T36	80		T105	2
alert_integrity_fail	alert[0xd]	12422	1			T8	9		T55	12		T65	1
alert_integrity_fail	alert[0xe]	8520	1			T55	48		T250	1		T68	4
alert_integrity_fail	alert[0xf]	8722	1			T3	2		T5	419		T27	8
alert_integrity_fail	alert[0x10]	3416	1			T55	37		T103	1		T27	35
alert_integrity_fail	alert[0x11]	4330	1			T5	2		T68	2		T36	8
alert_integrity_fail	alert[0x12]	15398	1			T36	70		T81	117		T11	31
alert_integrity_fail	alert[0x13]	3212	1			T5	20		T54	13		T81	90
alert_integrity_fail	alert[0x14]	8135	1			T4	14		T55	18		T65	1
alert_integrity_fail	alert[0x15]	4982	1			T55	159		T22	125		T36	312
alert_integrity_fail	alert[0x16]	5563	1			T54	38		T74	1		T37	3
alert_integrity_fail	alert[0x17]	6602	1			T5	64		T55	27		T68	1
alert_integrity_fail	alert[0x18]	3720	1			T55	33		T26	2		T22	39
alert_integrity_fail	alert[0x19]	8042	1			T250	1		T26	13		T54	87
alert_integrity_fail	alert[0x1a]	8270	1			T55	175		T250	3		T36	33
alert_integrity_fail	alert[0x1b]	4380	1			T54	88		T36	8		T53	157
alert_integrity_fail	alert[0x1c]	8229	1			T8	1		T5	5		T65	2
alert_integrity_fail	alert[0x1d]	9091	1			T5	11		T68	2		T22	43
alert_integrity_fail	alert[0x1e]	8753	1			T5	14		T56	2		T54	26
alert_integrity_fail	alert[0x1f]	3377	1			T4	4		T55	239		T68	1
alert_integrity_fail	alert[0x20]	2025	1			T27	10		T54	3		T105	9
alert_integrity_fail	alert[0x21]	9915	1			T5	2		T15	4		T68	1
alert_integrity_fail	alert[0x22]	4467	1			T5	11		T68	1		T53	49
alert_integrity_fail	alert[0x23]	3619	1			T5	7		T65	5		T27	25
alert_integrity_fail	alert[0x24]	4326	1			T5	55		T65	3		T27	69
alert_integrity_fail	alert[0x25]	3811	1			T4	13		T5	23		T95	33
alert_integrity_fail	alert[0x26]	4285	1			T54	154		T36	131		T105	1
alert_integrity_fail	alert[0x27]	2880	1			T5	12		T65	1		T26	5
alert_integrity_fail	alert[0x28]	7125	1			T5	8		T55	87		T26	2
alert_integrity_fail	alert[0x29]	7438	1			T5	58		T54	31		T53	730
alert_integrity_fail	alert[0x2a]	7495	1			T26	1		T27	3		T36	69
alert_integrity_fail	alert[0x2b]	4051	1			T5	25		T55	82		T27	3
alert_integrity_fail	alert[0x2c]	6031	1			T95	3		T54	26		T239	7
alert_integrity_fail	alert[0x2d]	4516	1			T55	9		T22	2		T81	1
alert_integrity_fail	alert[0x2e]	8948	1			T55	42		T95	1		T56	2
alert_integrity_fail	alert[0x2f]	7100	1			T19	1		T4	1		T55	34
alert_integrity_fail	alert[0x30]	8462	1			T4	1		T5	21		T95	2
alert_integrity_fail	alert[0x31]	14007	1			T5	29		T22	4305		T54	15
alert_integrity_fail	alert[0x32]	7783	1			T55	2		T36	2512		T239	3
alert_integrity_fail	alert[0x33]	9715	1			T8	1		T5	8		T55	46
alert_integrity_fail	alert[0x34]	8427	1			T5	7		T55	12		T65	2
alert_integrity_fail	alert[0x35]	10596	1			T65	2		T27	4		T54	447
alert_integrity_fail	alert[0x36]	3436	1			T4	36		T5	1		T55	6
alert_integrity_fail	alert[0x37]	3418	1			T3	2		T55	61		T15	5
alert_integrity_fail	alert[0x38]	6359	1			T36	230		T53	2685		T74	21
alert_integrity_fail	alert[0x39]	1156	1			T26	2		T27	4		T300	4
alert_integrity_fail	alert[0x3a]	6553	1			T8	13		T5	2		T27	25
alert_integrity_fail	alert[0x3b]	4405	1			T91	6		T55	32		T65	32
alert_integrity_fail	alert[0x3c]	4688	1			T26	2		T22	7		T54	847
alert_integrity_fail	alert[0x3d]	5450	1			T5	29		T55	16		T64	5
alert_integrity_fail	alert[0x3e]	9129	1			T5	81		T55	5		T27	4
alert_integrity_fail	alert[0x3f]	3038	1			T91	1		T55	3		T95	9
alert_integrity_fail	alert[0x40]	5467	1			T95	4		T64	12		T54	137
alert_ping_fail	alert[0x0]	8	1			T70	1		T194	2		T301	1
alert_ping_fail	alert[0x1]	19	1			T48	1		T50	1		T70	1
alert_ping_fail	alert[0x2]	10	1			T302	1		T303	1		T242	1
alert_ping_fail	alert[0x3]	7	1			T73	1		T69	1		T304	1
alert_ping_fail	alert[0x4]	13	1			T73	1		T304	1		T305	1
alert_ping_fail	alert[0x5]	15	1			T7	3		T295	1		T302	2
alert_ping_fail	alert[0x6]	11	1			T306	1		T307	1		T304	1
alert_ping_fail	alert[0x7]	9	1			T306	1		T296	2		T70	1
alert_ping_fail	alert[0x8]	16	1			T298	1		T296	1		T70	1
alert_ping_fail	alert[0x9]	11	1			T51	1		T249	1		T194	1
alert_ping_fail	alert[0xa]	14	1			T296	1		T70	1		T249	1
alert_ping_fail	alert[0xb]	13	1			T73	1		T241	1		T249	1
alert_ping_fail	alert[0xc]	9	1			T48	1		T70	1		T194	1
alert_ping_fail	alert[0xd]	17	1			T50	1		T51	1		T69	2
alert_ping_fail	alert[0xe]	7	1			T249	1		T303	1		T308	1
alert_ping_fail	alert[0xf]	11	1			T48	1		T70	1		T302	1
alert_ping_fail	alert[0x10]	9	1			T48	1		T73	2		T303	1
alert_ping_fail	alert[0x11]	9	1			T70	1		T241	2		T249	2
alert_ping_fail	alert[0x12]	5	1			T304	1		T309	1		T305	1
alert_ping_fail	alert[0x13]	13	1			T48	1		T69	1		T306	1
alert_ping_fail	alert[0x14]	11	1			T48	1		T73	1		T66	1
alert_ping_fail	alert[0x15]	17	1			T241	1		T249	1		T309	1
alert_ping_fail	alert[0x16]	13	1			T48	1		T49	1		T67	1
alert_ping_fail	alert[0x17]	13	1			T48	1		T306	1		T70	1
alert_ping_fail	alert[0x18]	5	1			T73	1		T69	1		T310	1
alert_ping_fail	alert[0x19]	10	1			T49	2		T298	1		T194	1
alert_ping_fail	alert[0x1a]	9	1			T49	1		T306	1		T241	1
alert_ping_fail	alert[0x1b]	12	1			T49	1		T50	1		T241	1
alert_ping_fail	alert[0x1c]	14	1			T48	1		T308	1		T311	1
alert_ping_fail	alert[0x1d]	6	1			T312	1		T305	1		T313	1
alert_ping_fail	alert[0x1e]	12	1			T51	1		T314	3		T315	1
alert_ping_fail	alert[0x1f]	19	1			T48	1		T67	1		T69	3
alert_ping_fail	alert[0x20]	10	1			T298	1		T301	1		T316	1
alert_ping_fail	alert[0x21]	11	1			T298	1		T241	1		T249	1
alert_ping_fail	alert[0x22]	19	1			T67	1		T241	1		T301	2
alert_ping_fail	alert[0x23]	13	1			T70	1		T194	1		T302	2
alert_ping_fail	alert[0x24]	10	1			T48	1		T73	1		T306	2
alert_ping_fail	alert[0x25]	9	1			T73	2		T241	1		T249	1
alert_ping_fail	alert[0x26]	6	1			T317	1		T318	1		T319	1
alert_ping_fail	alert[0x27]	7	1			T48	1		T302	1		T301	1
alert_ping_fail	alert[0x28]	13	1			T72	1		T306	1		T194	1
alert_ping_fail	alert[0x29]	9	1			T51	1		T306	1		T241	1
alert_ping_fail	alert[0x2a]	11	1			T249	1		T317	1		T314	1
alert_ping_fail	alert[0x2b]	14	1			T49	1		T298	1		T70	1
alert_ping_fail	alert[0x2c]	18	1			T48	1		T320	2		T309	1
alert_ping_fail	alert[0x2d]	12	1			T49	1		T249	1		T308	1
alert_ping_fail	alert[0x2e]	15	1			T49	1		T69	1		T241	1
alert_ping_fail	alert[0x2f]	20	1			T73	1		T69	1		T66	2
alert_ping_fail	alert[0x30]	15	1			T7	1		T73	1		T194	1
alert_ping_fail	alert[0x31]	9	1			T51	1		T194	1		T302	1
alert_ping_fail	alert[0x32]	12	1			T70	1		T194	1		T321	1
alert_ping_fail	alert[0x33]	9	1			T48	1		T73	2		T70	1
alert_ping_fail	alert[0x34]	8	1			T305	1		T242	1		T322	1
alert_ping_fail	alert[0x35]	6	1			T194	1		T302	1		T315	2
alert_ping_fail	alert[0x36]	10	1			T73	1		T306	1		T70	1
alert_ping_fail	alert[0x37]	10	1			T48	1		T73	1		T302	1
alert_ping_fail	alert[0x38]	10	1			T298	1		T70	1		T194	1
alert_ping_fail	alert[0x39]	11	1			T73	1		T306	1		T194	1
alert_ping_fail	alert[0x3a]	13	1			T48	1		T249	1		T304	1
alert_ping_fail	alert[0x3b]	14	1			T70	1		T241	1		T308	2
alert_ping_fail	alert[0x3c]	12	1			T49	1		T73	1		T298	1
alert_ping_fail	alert[0x3d]	12	1			T48	1		T50	1		T73	1
alert_ping_fail	alert[0x3e]	9	1			T241	1		T304	1		T309	1
alert_ping_fail	alert[0x3f]	4	1			T73	1		T318	1		T305	1
alert_ping_fail	alert[0x40]	4	1			T249	1		T323	1		T324	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	70045	1			T3	4		T8	1		T19	1
alert_integrity_fail	class_i[0x1]	97408	1			T8	25		T55	1588		T26	20
alert_integrity_fail	class_i[0x2]	104119	1			T4	4		T5	1054		T95	40
alert_integrity_fail	class_i[0x3]	128448	1			T4	53		T5	20		T56	4
alert_ping_fail	class_i[0x0]	157	1			T48	2		T49	1		T50	1
alert_ping_fail	class_i[0x1]	182	1			T7	4		T50	2		T51	4
alert_ping_fail	class_i[0x2]	252	1			T49	8		T67	3		T73	1
alert_ping_fail	class_i[0x3]	141	1			T72	1		T48	15		T50	1