Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	77292	1			T8	5		T11	10		T142	18
class_i[0x1]	58161	1			T9	4		T16	2		T11	2
class_i[0x2]	59091	1			T16	11		T142	6		T245	11
class_i[0x3]	75468	1			T8	13		T9	2		T16	2970

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	68658	1			T8	6		T16	664		T11	3
alert[0x1]	69179	1			T8	4		T16	777		T142	5
alert[0x2]	64751	1			T8	5		T9	4		T16	774
alert[0x3]	67424	1			T8	3		T9	2		T16	768

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

269727

1

T8

13

T9

4

T16

2983

esc_ping_fail

285

1

T8

5

T9

2

T11

4

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	68577	1			T8	4		T16	664		T11	2
esc_integrity_fail	alert[0x1]	69105	1			T8	3		T16	777		T142	3
esc_integrity_fail	alert[0x2]	64684	1			T8	4		T9	3		T16	774
esc_integrity_fail	alert[0x3]	67361	1			T8	2		T9	1		T16	768
esc_ping_fail	alert[0x0]	81	1			T8	2		T11	1		T142	2
esc_ping_fail	alert[0x1]	74	1			T8	1		T142	2		T245	2
esc_ping_fail	alert[0x2]	67	1			T8	1		T9	1		T11	1
esc_ping_fail	alert[0x3]	63	1			T8	1		T9	1		T11	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	77215	1			T11	8		T142	18		T101	67
esc_integrity_fail	class_i[0x1]	58112	1			T9	4		T16	2		T24	4024
esc_integrity_fail	class_i[0x2]	58988	1			T16	11		T25	1679		T33	4470
esc_integrity_fail	class_i[0x3]	75412	1			T8	13		T16	2970		T101	3
esc_ping_fail	class_i[0x0]	77	1			T8	5		T11	2		T68	4
esc_ping_fail	class_i[0x1]	49	1			T11	2		T142	2		T143	4
esc_ping_fail	class_i[0x2]	103	1			T142	6		T245	11		T118	2
esc_ping_fail	class_i[0x3]	56	1			T9	2		T245	1		T118	1