Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.61	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	2	42	95.45

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	2	42	95.45	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	153	1			T8	2		T20	1		T10	1
index[0x1]	166	1			T8	2		T9	1		T41	1
index[0x2]	178	1			T6	1		T21	1		T16	2
index[0x3]	156	1			T8	1		T37	1		T251	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	209	1			T8	1		T20	1		T16	2
lens_less_than_1000[1]	124	1			T6	1		T41	1		T273	1
lens_less_than_1000[2]	77	1			T8	4		T142	1		T25	1
lens_less_than_1000[3]	78	1			T21	1		T251	1		T34	1
lens_less_than_1000[4]	50	1			T9	1		T251	1		T25	1
lens_less_than_1000[5]	50	1			T25	1		T28	1		T46	2
lens_less_than_1000[6]	26	1			T142	1		T274	1		T48	2
lens_less_than_1000[7]	18	1			T77	1		T44	1		T74	1
lens_less_than_1000[8]	8	1			T10	1		T44	1		T49	1
lens_less_than_1000[9]	3	1			T275	1		T57	1		T276	1
len_2	10	1			T82	1		T277	1		T278	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	2	42	95.45	2

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0]]	[lens_less_than_1000[9]]	0	1	1
[index[0x3]]	[lens_less_than_1000[9]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	51	1			T20	1		T37	1		T41	2
index[0x0]	lens_less_than_1000[1]	28	1			T80	2		T47	1		T274	1
index[0x0]	lens_less_than_1000[2]	23	1			T8	2		T142	1		T46	1
index[0x0]	lens_less_than_1000[3]	13	1			T251	1		T114	1		T47	1
index[0x0]	lens_less_than_1000[4]	15	1			T47	2		T202	1		T210	1
index[0x0]	lens_less_than_1000[5]	7	1			T46	2		T139	1		T279	1
index[0x0]	lens_less_than_1000[6]	5	1			T274	1		T280	1		T281	1
index[0x0]	lens_less_than_1000[7]	5	1			T74	1		T85	1		T282	1
index[0x0]	lens_less_than_1000[8]	2	1			T10	1		T49	1		-	-
index[0x0]	len_2	4	1			T82	1		T278	1		T283	1
index[0x1]	lens_less_than_1000[0]	55	1			T80	1		T46	1		T47	6
index[0x1]	lens_less_than_1000[1]	30	1			T41	1		T44	1		T28	2
index[0x1]	lens_less_than_1000[2]	15	1			T8	2		T82	1		T203	1
index[0x1]	lens_less_than_1000[3]	23	1			T34	1		T81	1		T133	1
index[0x1]	lens_less_than_1000[4]	11	1			T9	1		T26	1		T284	1
index[0x1]	lens_less_than_1000[5]	14	1			T28	1		T85	1		T285	1
index[0x1]	lens_less_than_1000[6]	10	1			T75	1		T203	1		T286	1
index[0x1]	lens_less_than_1000[7]	3	1			T287	1		T288	1		T289	1
index[0x1]	lens_less_than_1000[8]	2	1			T88	1		T57	1		-	-
index[0x1]	lens_less_than_1000[9]	2	1			T57	1		T276	1		-	-
index[0x1]	len_2	1	1			T254	1		-	-		-	-
index[0x2]	lens_less_than_1000[0]	58	1			T16	2		T43	1		T80	1
index[0x2]	lens_less_than_1000[1]	33	1			T6	1		T273	1		T119	2
index[0x2]	lens_less_than_1000[2]	19	1			T273	1		T46	1		T82	2
index[0x2]	lens_less_than_1000[3]	24	1			T21	1		T290	1		T274	1
index[0x2]	lens_less_than_1000[4]	9	1			T25	1		T70	1		T86	1
index[0x2]	lens_less_than_1000[5]	17	1			T25	1		T48	1		T49	1
index[0x2]	lens_less_than_1000[6]	7	1			T48	2		T100	1		T141	1
index[0x2]	lens_less_than_1000[7]	5	1			T291	1		T292	1		T272	1
index[0x2]	lens_less_than_1000[8]	3	1			T44	1		T100	1		T293	1
index[0x2]	lens_less_than_1000[9]	1	1			T275	1		-	-		-	-
index[0x2]	len_2	2	1			T277	1		T53	1		-	-
index[0x3]	lens_less_than_1000[0]	45	1			T8	1		T37	1		T101	1
index[0x3]	lens_less_than_1000[1]	33	1			T44	1		T28	3		T46	2
index[0x3]	lens_less_than_1000[2]	20	1			T25	1		T34	2		T46	1
index[0x3]	lens_less_than_1000[3]	18	1			T128	1		T116	1		T100	1
index[0x3]	lens_less_than_1000[4]	15	1			T251	1		T28	1		T46	1
index[0x3]	lens_less_than_1000[5]	12	1			T274	1		T106	5		T100	1
index[0x3]	lens_less_than_1000[6]	4	1			T142	1		T293	1		T110	1
index[0x3]	lens_less_than_1000[7]	5	1			T77	1		T44	1		T270	1
index[0x3]	lens_less_than_1000[8]	1	1			T113	1		-	-		-	-
index[0x3]	len_2	3	1			T53	1		T294	2		-	-