Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.74	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	5	35	87.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	5	35	87.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	66	1			T18	1		T24	1		T25	3
class_index[0x1]	57	1			T21	1		T34	1		T28	2
class_index[0x2]	77	1			T23	2		T80	1		T34	1
class_index[0x3]	56	1			T44	1		T28	2		T82	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	115	1			T18	1		T21	1		T23	2
intr_timeout_cnt[1]	47	1			T24	1		T34	2		T81	1
intr_timeout_cnt[2]	22	1			T28	1		T48	1		T83	1
intr_timeout_cnt[3]	22	1			T25	2		T44	1		T48	1
intr_timeout_cnt[4]	15	1			T82	3		T83	1		T86	1
intr_timeout_cnt[5]	7	1			T28	1		T86	1		T100	1
intr_timeout_cnt[6]	9	1			T28	1		T84	1		T88	1
intr_timeout_cnt[7]	12	1			T25	1		T48	2		T124	1
intr_timeout_cnt[8]	2	1			T255	1		T256	1		-	-
intr_timeout_cnt[9]	5	1			T44	1		T86	1		T139	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	5	35	87.50	5

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[8]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[5]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[8]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[8]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	22	1			T18	1		T86	1		T257	1
class_index[0x0]	intr_timeout_cnt[1]	15	1			T24	1		T28	1		T87	2
class_index[0x0]	intr_timeout_cnt[2]	2	1			T105	2		-	-		-	-
class_index[0x0]	intr_timeout_cnt[3]	8	1			T25	2		T44	1		T134	1
class_index[0x0]	intr_timeout_cnt[4]	3	1			T258	1		T259	1		T260	1
class_index[0x0]	intr_timeout_cnt[5]	4	1			T100	1		T261	1		T52	1
class_index[0x0]	intr_timeout_cnt[6]	4	1			T88	1		T125	1		T113	1
class_index[0x0]	intr_timeout_cnt[7]	6	1			T25	1		T48	1		T262	2
class_index[0x0]	intr_timeout_cnt[9]	2	1			T86	1		T263	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	23	1			T21	1		T28	1		T46	1
class_index[0x1]	intr_timeout_cnt[1]	12	1			T34	1		T85	1		T86	1
class_index[0x1]	intr_timeout_cnt[2]	8	1			T48	1		T87	1		T88	1
class_index[0x1]	intr_timeout_cnt[3]	3	1			T264	2		T265	1		-	-
class_index[0x1]	intr_timeout_cnt[4]	5	1			T82	1		T86	1		T262	1
class_index[0x1]	intr_timeout_cnt[6]	4	1			T28	1		T84	1		T266	1
class_index[0x1]	intr_timeout_cnt[7]	1	1			T267	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[9]	1	1			T139	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	43	1			T23	2		T80	1		T44	1
class_index[0x2]	intr_timeout_cnt[1]	11	1			T34	1		T81	1		T104	2
class_index[0x2]	intr_timeout_cnt[2]	4	1			T28	1		T88	1		T105	1
class_index[0x2]	intr_timeout_cnt[3]	7	1			T48	1		T139	1		T100	1
class_index[0x2]	intr_timeout_cnt[4]	5	1			T82	2		T83	1		T141	1
class_index[0x2]	intr_timeout_cnt[5]	1	1			T86	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[6]	1	1			T113	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[7]	2	1			T135	1		T267	1		-	-
class_index[0x2]	intr_timeout_cnt[8]	2	1			T255	1		T256	1		-	-
class_index[0x2]	intr_timeout_cnt[9]	1	1			T268	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	27	1			T82	1		T67	1		T123	1
class_index[0x3]	intr_timeout_cnt[1]	9	1			T28	1		T100	1		T269	1
class_index[0x3]	intr_timeout_cnt[2]	8	1			T83	1		T270	1		T271	1
class_index[0x3]	intr_timeout_cnt[3]	4	1			T86	1		T125	2		T272	1
class_index[0x3]	intr_timeout_cnt[4]	2	1			T100	1		T104	1		-	-
class_index[0x3]	intr_timeout_cnt[5]	2	1			T28	1		T99	1		-	-
class_index[0x3]	intr_timeout_cnt[7]	3	1			T48	1		T124	1		T104	1
class_index[0x3]	intr_timeout_cnt[9]	1	1			T44	1		-	-		-	-