Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	357069	1			T1	11		T2	41		T3	3
all_values[1]	357069	1			T1	11		T2	41		T3	3
all_values[2]	357069	1			T1	11		T2	41		T3	3
all_values[3]	357069	1			T1	11		T2	41		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

710497

1

T1

26

T2

93

T3

3

auto[1]

717779

1

T1

18

T2

71

T3

9

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

850685

1

T1

24

T2

151

T3

8

auto[1]

577591

1

T1

20

T2

13

T3

4

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	102640	1			T1	3		T2	17		T6	244
all_values[0]	auto[0]	auto[1]	74300	1			T1	2		T2	7		T6	241
all_values[0]	auto[1]	auto[0]	105123	1			T1	3		T2	11		T3	2
all_values[0]	auto[1]	auto[1]	75006	1			T1	3		T2	6		T3	1
all_values[1]	auto[0]	auto[0]	106633	1			T1	3		T2	21		T6	207
all_values[1]	auto[0]	auto[1]	70973	1			T1	2		T6	196		T18	6
all_values[1]	auto[1]	auto[0]	108369	1			T1	3		T2	20		T3	2
all_values[1]	auto[1]	auto[1]	71094	1			T1	3		T3	1		T6	257
all_values[2]	auto[0]	auto[0]	106213	1			T1	5		T2	21		T3	2
all_values[2]	auto[0]	auto[1]	71615	1			T1	4		T3	1		T6	237
all_values[2]	auto[1]	auto[0]	107555	1			T1	1		T2	20		T6	228
all_values[2]	auto[1]	auto[1]	71686	1			T1	1		T6	227		T18	6
all_values[3]	auto[0]	auto[0]	106647	1			T1	4		T2	27		T6	258
all_values[3]	auto[0]	auto[1]	71476	1			T1	3		T6	249		T18	3
all_values[3]	auto[1]	auto[0]	107505	1			T1	2		T2	14		T3	2
all_values[3]	auto[1]	auto[1]	71441	1			T1	2		T3	1		T6	207