Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	357069	1			T1	11		T2	41		T3	3
all_pins[1]	357069	1			T1	11		T2	41		T3	3
all_pins[2]	357069	1			T1	11		T2	41		T3	3
all_pins[3]	357069	1			T1	11		T2	41		T3	3

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1139049	1			T1	35		T2	158		T3	9
values[0x1]	289227	1			T1	9		T2	6		T3	3
transitions[0x0=>0x1]	191837	1			T1	5		T2	6		T3	1
transitions[0x1=>0x0]	192099	1			T1	6		T2	6		T3	2

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	282063	1			T1	8		T2	35		T3	2
all_pins[0]	values[0x1]	75006	1			T1	3		T2	6		T3	1
all_pins[0]	transitions[0x0=>0x1]	74303	1			T1	2		T2	6		T6	222
all_pins[0]	transitions[0x1=>0x0]	71000	1			T1	2		T3	1		T6	207
all_pins[1]	values[0x0]	285975	1			T1	8		T2	41		T3	2
all_pins[1]	values[0x1]	71094	1			T1	3		T3	1		T6	257
all_pins[1]	transitions[0x0=>0x1]	38779	1			T1	1		T6	144		T18	1
all_pins[1]	transitions[0x1=>0x0]	42691	1			T1	1		T2	6		T6	109
all_pins[2]	values[0x0]	285383	1			T1	10		T2	41		T3	3
all_pins[2]	values[0x1]	71686	1			T1	1		T6	227		T18	6
all_pins[2]	transitions[0x0=>0x1]	39382	1			T6	103		T18	3		T7	153
all_pins[2]	transitions[0x1=>0x0]	38790	1			T1	2		T3	1		T6	133
all_pins[3]	values[0x0]	285628	1			T1	9		T2	41		T3	2
all_pins[3]	values[0x1]	71441	1			T1	2		T3	1		T6	207
all_pins[3]	transitions[0x0=>0x1]	39373	1			T1	2		T3	1		T6	103
all_pins[3]	transitions[0x1=>0x0]	39618	1			T1	1		T6	123		T18	1