Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	275	1			T183	4		T184	4		T185	4
all_values[1]	275	1			T183	4		T184	4		T185	4
all_values[2]	275	1			T183	4		T184	4		T185	4
all_values[3]	275	1			T183	4		T184	4		T185	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

586

1

T183

9

T184

8

T185

11

auto[1]

514

1

T183

7

T184

8

T185

5

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

436

1

T183

9

T184

7

T185

9

auto[1]

664

1

T183

7

T184

9

T185

7

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

659

1

T183

10

T184

11

T185

10

auto[1]

441

1

T183

6

T184

5

T185

6

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

59

1

T183

2

T184

2

T332

2

all_values[0]

auto[0]

auto[0]

auto[1]

26

1

T185

1

T244

1

T333

2

all_values[0]

auto[0]

auto[1]

auto[0]

64

1

T183

1

T184

1

T244

3

all_values[0]

auto[0]

auto[1]

auto[1]

27

1

T244

1

T334

1

T333

1

all_values[0]

auto[1]

auto[0]

auto[1]

54

1

T185

3

T244

2

T332

2

all_values[0]

auto[1]

auto[1]

auto[1]

45

1

T183

1

T184

1

T334

1

all_values[1]

auto[0]

auto[0]

auto[0]

49

1

T184

1

T185

2

T244

2

all_values[1]

auto[0]

auto[0]

auto[1]

31

1

T183

1

T244

2

T335

1

all_values[1]

auto[0]

auto[1]

auto[0]

42

1

T183

1

T185

2

T244

2

all_values[1]

auto[0]

auto[1]

auto[1]

32

1

T184

2

T332

2

T333

2

all_values[1]

auto[1]

auto[0]

auto[1]

72

1

T244

1

T334

1

T335

3

all_values[1]

auto[1]

auto[1]

auto[1]

49

1

T183

2

T184

1

T332

2

all_values[2]

auto[0]

auto[0]

auto[0]

56

1

T183

1

T185

1

T244

2

all_values[2]

auto[0]

auto[0]

auto[1]

25

1

T244

4

T250

1

T336

2

all_values[2]

auto[0]

auto[1]

auto[0]

56

1

T183

1

T185

3

T332

2

all_values[2]

auto[0]

auto[1]

auto[1]

26

1

T184

2

T334

1

T337

1

all_values[2]

auto[1]

auto[0]

auto[1]

71

1

T183

2

T184

2

T244

1

all_values[2]

auto[1]

auto[1]

auto[1]

41

1

T332

2

T335

1

T333

1

all_values[3]

auto[0]

auto[0]

auto[0]

60

1

T183

2

T184

3

T185

1

all_values[3]

auto[0]

auto[0]

auto[1]

27

1

T332

1

T335

2

T333

1

all_values[3]

auto[0]

auto[1]

auto[0]

50

1

T183

1

T244

1

T335

2

all_values[3]

auto[0]

auto[1]

auto[1]

29

1

T244

1

T332

1

T334

1

all_values[3]

auto[1]

auto[0]

auto[1]

56

1

T183

1

T185

3

T332

1

all_values[3]

auto[1]

auto[1]

auto[1]

53

1

T184

1

T244

3

T332

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal