Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	84094	1			T6	421		T10	25		T41	233
accum_cnt_1000	216654	1			T6	1511		T15	1407		T10	1969
accum_cnt_100	24368	1			T6	85		T15	240		T10	140
accum_cnt_50	69151	1			T6	64		T18	6		T8	4
accum_cnt_10	191040	1			T1	9		T2	17		T3	2
accum_cnt_0	423592	1			T1	31		T2	99		T3	6

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	263845	1			T1	10		T2	29		T3	2
class_index[0x1]	263845	1			T1	10		T2	29		T3	2
class_index[0x2]	263845	1			T1	10		T2	29		T3	2
class_index[0x3]	263845	1			T1	10		T2	29		T3	2

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	20407	1			T6	209		T10	25		T29	442
class_index[0x0]	accum_cnt_1000	57104	1			T6	443		T10	1008		T16	752
class_index[0x0]	accum_cnt_100	6851	1			T6	24		T10	52		T16	44
class_index[0x0]	accum_cnt_50	21662	1			T6	20		T21	19		T10	42
class_index[0x0]	accum_cnt_10	43518	1			T2	17		T6	6		T18	6
class_index[0x0]	accum_cnt_0	101976	1			T1	10		T2	12		T3	2
class_index[0x1]	accum_cnt_2000	19820	1			T41	162		T29	424		T23	601
class_index[0x1]	accum_cnt_1000	48613	1			T15	772		T41	420		T29	671
class_index[0x1]	accum_cnt_100	5381	1			T15	85		T41	22		T29	38
class_index[0x1]	accum_cnt_50	18331	1			T18	6		T8	4		T20	3
class_index[0x1]	accum_cnt_10	46701	1			T1	7		T3	1		T18	10
class_index[0x1]	accum_cnt_0	113836	1			T1	3		T2	29		T3	1
class_index[0x2]	accum_cnt_2000	20874	1			T6	178		T41	71		T23	489
class_index[0x2]	accum_cnt_1000	55615	1			T6	467		T15	635		T10	961
class_index[0x2]	accum_cnt_100	6431	1			T6	26		T15	155		T10	88
class_index[0x2]	accum_cnt_50	13305	1			T6	20		T15	118		T21	21
class_index[0x2]	accum_cnt_10	50138	1			T1	2		T6	9		T18	2
class_index[0x2]	accum_cnt_0	108610	1			T1	8		T2	29		T3	2
class_index[0x3]	accum_cnt_2000	22993	1			T6	34		T42	482		T29	574
class_index[0x3]	accum_cnt_1000	55322	1			T6	601		T17	522		T42	416
class_index[0x3]	accum_cnt_100	5705	1			T6	35		T17	80		T41	2
class_index[0x3]	accum_cnt_50	15853	1			T6	24		T21	20		T17	71
class_index[0x3]	accum_cnt_10	50683	1			T3	1		T6	8		T18	13
class_index[0x3]	accum_cnt_0	99170	1			T1	10		T2	29		T3	1